1 /*
2  * Copyright (c) 2024 Microchip
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #ifndef _MICROCHIP_PIC32CXSG_RAMECC_COMPONENT_FIXUP_H_
8 #define _MICROCHIP_PIC32CXSG_RAMECC_COMPONENT_FIXUP_H_
9 
10 /* -------- RAMECC_INTENCLR : (RAMECC Offset: 0x00) (R/W 8) Interrupt Enable Clear -------- */
11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
12 typedef union {
13   struct {
14     uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt Enable Clear */
15     uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt Enable Clear */
16     uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
17   } bit;                       /*!< Structure used for bit  access                  */
18   uint8_t reg;                 /*!< Type      used for register access              */
19 } RAMECC_INTENCLR_Type;
20 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
21 
22 /* -------- RAMECC_INTENSET : (RAMECC Offset: 0x01) (R/W 8) Interrupt Enable Set -------- */
23 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
24 typedef union {
25   struct {
26     uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt Enable Set */
27     uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt Enable Set */
28     uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
29   } bit;                       /*!< Structure used for bit  access                  */
30   uint8_t reg;                 /*!< Type      used for register access              */
31 } RAMECC_INTENSET_Type;
32 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
33 
34 /* -------- RAMECC_INTFLAG : (RAMECC Offset: 0x02) (R/W 8) Interrupt Flag -------- */
35 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
36 typedef union { // __I to avoid read-modify-write on write-to-clear register
37   struct {
38     __I uint8_t  SINGLEE:1;        /*!< bit:      0  Single Bit ECC Error Interrupt     */
39     __I uint8_t  DUALE:1;          /*!< bit:      1  Dual Bit ECC Error Interrupt       */
40     __I uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
41   } bit;                       /*!< Structure used for bit  access                  */
42   uint8_t reg;                 /*!< Type      used for register access              */
43 } RAMECC_INTFLAG_Type;
44 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
45 
46 /* -------- RAMECC_STATUS : (RAMECC Offset: 0x03) ( R/ 8) Status -------- */
47 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
48 typedef union {
49   struct {
50     uint8_t  ECCDIS:1;         /*!< bit:      0  ECC Disable                        */
51     uint8_t  :7;               /*!< bit:  1.. 7  Reserved                           */
52   } bit;                       /*!< Structure used for bit  access                  */
53   uint8_t reg;                 /*!< Type      used for register access              */
54 } RAMECC_STATUS_Type;
55 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
56 
57 /* -------- RAMECC_ERRADDR : (RAMECC Offset: 0x04) ( R/ 32) Error Address -------- */
58 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
59 typedef union {
60   struct {
61     uint32_t ERRADDR:17;       /*!< bit:  0..16  Error Address                      */
62     uint32_t :15;              /*!< bit: 17..31  Reserved                           */
63   } bit;                       /*!< Structure used for bit  access                  */
64   uint32_t reg;                /*!< Type      used for register access              */
65 } RAMECC_ERRADDR_Type;
66 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
67 
68 /* -------- RAMECC_DBGCTRL : (RAMECC Offset: 0x0F) (R/W 8) Debug Control -------- */
69 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
70 typedef union {
71   struct {
72     uint8_t  ECCDIS:1;         /*!< bit:      0  ECC Disable                        */
73     uint8_t  ECCELOG:1;        /*!< bit:      1  ECC Error Log                      */
74     uint8_t  :6;               /*!< bit:  2.. 7  Reserved                           */
75   } bit;                       /*!< Structure used for bit  access                  */
76   uint8_t reg;                 /*!< Type      used for register access              */
77 } RAMECC_DBGCTRL_Type;
78 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
79 
80 /** \brief RAMECC hardware registers */
81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
82 typedef struct {
83   __IO RAMECC_INTENCLR_Type      INTENCLR;    /**< \brief Offset: 0x0 (R/W  8) Interrupt Enable Clear */
84   __IO RAMECC_INTENSET_Type      INTENSET;    /**< \brief Offset: 0x1 (R/W  8) Interrupt Enable Set */
85   __IO RAMECC_INTFLAG_Type       INTFLAG;     /**< \brief Offset: 0x2 (R/W  8) Interrupt Flag */
86   __I  RAMECC_STATUS_Type        STATUS;      /**< \brief Offset: 0x3 (R/   8) Status */
87   __I  RAMECC_ERRADDR_Type       ERRADDR;     /**< \brief Offset: 0x4 (R/  32) Error Address */
88        RoReg8                    Reserved1[0x7];
89   __IO RAMECC_DBGCTRL_Type       DBGCTRL;     /**< \brief Offset: 0xF (R/W  8) Debug Control */
90 } Ramecc;
91 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
92 
93 #endif /* _MICROCHIP_PIC32CXSG_RAMECC_COMPONENT_FIXUP_H_ */
94