Searched refs:REG_DMAC_CHINTENSET3 (Results 1 – 1 of 1) sorted by relevance
56 #define REG_DMAC_CHINTENSET3 (0x4100A07D) /**< \brief (DMAC) Channel 3 Interrupt Enable Set */ macro328 #define REG_DMAC_CHINTENSET3 (*(RwReg8 *)0x4100A07DUL) /**< \brief (DMAC) Channel 3 Interrupt… macro
