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Searched refs:QUE_THLD_CTRL (Results 1 – 3 of 3) sorted by relevance

/hal_microchip-latest/mec5/drivers/
Dmec_i3c_pvt.c139 regs->QUE_THLD_CTRL &= (uint32_t)~(0xFFu << QUEUE_THLD_RESP_QUEUE_BITPOS); in _i3c_resp_queue_threshold_set()
140 regs->QUE_THLD_CTRL |= (threshold << QUEUE_THLD_RESP_QUEUE_BITPOS); in _i3c_resp_queue_threshold_set()
240 regs->QUE_THLD_CTRL &= (uint32_t)~(0xFFu << QUEUE_THLD_CMD_QUEUE_BITPOS); in _i3c_cmd_queue_threshold_set()
241 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_CMD_QUEUE_BITPOS); in _i3c_cmd_queue_threshold_set()
251 regs->QUE_THLD_CTRL &= (uint32_t)~(0xFFu << QUEUE_THLD_IBI_DATA_BITPOS); in _i3c_ibi_data_threshold_set()
252 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_IBI_DATA_BITPOS); in _i3c_ibi_data_threshold_set()
262 regs->QUE_THLD_CTRL &= (uint32_t)~(0xFFu << QUEUE_THLD_IBI_STATUS_BITPOS); in _i3c_ibi_status_threshold_set()
263 regs->QUE_THLD_CTRL |= (val << QUEUE_THLD_IBI_STATUS_BITPOS); in _i3c_ibi_status_threshold_set()
/hal_microchip-latest/mec5/devices/common/
Dmec5_i3c_host_v2.h28 …__IOM uint32_t QUE_THLD_CTRL; /*!< (@ 0x0000001C) Queue threshold control register… member
Dmec5_i3c_sec_v2.h28 …__IOM uint32_t QUE_THLD_CTRL; /*!< (@ 0x0000001C) Queue threshold control register… member