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Searched refs:PLL_DIV_0_1 (Results 1 – 3 of 3) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_pll.c442 MSS_SCB_MSS_PLL->PLL_DIV_0_1 = LIBERO_SETTING_MSS_PLL_DIV_0_1; in mss_pll_config()
527 MSS_SCB_DDR_PLL->PLL_DIV_0_1 = LIBERO_SETTING_DDR_PLL_DIV_0_1; in ddr_pll_config()
647 MSS_SCB_SGMII_PLL->PLL_DIV_0_1 = LIBERO_SETTING_SGMII_PLL_DIV_0_1; in sgmii_pll_config_scb()
Dmss_scb_nwc_regs.h45 __IO uint32_t PLL_DIV_0_1; /*!< Offset: 0x10 */ member
Dmss_ddr.c1682 MSS_SCB_DDR_PLL->PLL_DIV_0_1); in ddr_setup()