1 /*******************************************************************************
2  * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions.
3  *
4  * SPDX-License-Identifier: MIT
5  *
6  * PolarFire and PolarFire SoC PCIe subsystem software driver public
7  * data structures.
8  *
9  */
10 #ifndef PF_PCIESS_TYPES_H_
11 #define PF_PCIESS_TYPES_H_
12 
13 #include <stdint.h>
14 
15 #ifdef __cplusplus
16 extern "C" {
17 #endif
18 
19 /*****************************************************************************
20   PCIe AXI master and slave table size enum i.e PCIe ATR_SIZE
21   PCIe ATR_SIZE is 6 bits long and defines the Address Translation Space Size.
22   This space size in bytes is equal to 2^(ATR_SIZE +1).
23 
24   The pf_pcie_atr_size_t type specifies the table sizes supported by the
25   PolarFire PCIe driver for the initialization of the PCIe AXI4 master and
26   slave address translation tables.
27 */
28 typedef enum
29 {
30     PF_PCIE_SIZE_4KB = 11,
31     PF_PCIE_SIZE_8KB,
32     PF_PCIE_SIZE_16KB,
33     PF_PCIE_SIZE_32KB,
34     PF_PCIE_SIZE_64KB,
35     PF_PCIE_SIZE_128KB,
36     PF_PCIE_SIZE_256KB,
37     PF_PCIE_SIZE_512KB,
38     PF_PCIE_SIZE_1MB,
39     PF_PCIE_SIZE_2MB,
40     PF_PCIE_SIZE_4MB,
41     PF_PCIE_SIZE_8MB,
42     PF_PCIE_SIZE_16MB,
43     PF_PCIE_SIZE_32MB,
44     PF_PCIE_SIZE_64MB,
45     PF_PCIE_SIZE_128MB,
46     PF_PCIE_SIZE_256MB,
47     PF_PCIE_SIZE_512MB,
48     PF_PCIE_SIZE_1GB,
49     PF_PCIE_SIZE_2GB,
50     PF_PCIE_SIZE_4GB,
51     PF_PCIE_SIZE_8GB,
52     PF_PCIE_SIZE_16GB,
53     PF_PCIE_SIZE_32GB,
54     PF_PCIE_SIZE_64GB,
55     PF_PCIE_SIZE_128GB,
56     PF_PCIE_SIZE_256GB,
57     PF_PCIE_SIZE_512GB,
58     PF_PCIE_SIZE_1TB,
59     PF_PCIE_SIZE_2TB,
60     PF_PCIE_SIZE_4TB,
61     PF_PCIE_SIZE_8TB,
62     PF_PCIE_SIZE_16TB,
63     PF_PCIE_SIZE_32TB,
64     PF_PCIE_SIZE_64TB,
65     PF_PCIE_SIZE_128TB,
66     PF_PCIE_SIZE_256TB,
67     PF_PCIE_SIZE_512TB
68 } pf_pcie_atr_size_t;
69 
70 /*****************************************************************************
71   The pf_pcie_bar_type_t type specifies the bar types supported by the driver
72   for the initialization of the PCIe AXI4 master address translation table.
73 
74   PCIe BAR type enum for 32-bit and 64-bit memory.
75 */
76 typedef enum
77 {
78     PF_PCIE_BAR_TYPE_32BIT_MEM = 0x0,
79     PF_PCIE_BAR_TYPE_32BIT_PREFET_MEM = 0x8,
80     PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM = 0xC
81 } pf_pcie_bar_type_t;
82 
83 /*****************************************************************************
84   The pf_pcie_tlp_type_t type specifies the transaction layer packet types
85   supported by the driver for the initialization of the PCIe AXI4 master and
86   slave address translation tables.
87 */
88 typedef enum
89 {
90     PF_PCIE_TLP_MEM = 0,
91     PF_PCIE_TLP_MEM_LOCKED = 1,
92     PF_PCIE_TLP_IO = 2,
93     PF_PCIE_TLP_TRSNL_REQUEST = 3,
94     PF_PCIE_TLP_MESSAGE = 4,
95     PF_PCIE_TLP_MEM_TRSNL_REQUEST = 5
96 } pf_pcie_tlp_type_t;
97 
98 /*****************************************************************************
99   The pf_pcie_ep_dma_status_t type communicates the status of the DMA transfer
100   initiated by the most recent call to the PF_PCIE_dma_write() or
101   PF_PCIE_dma_read() function. It indicates if a transfer is in progress, and
102   if this is not the case, indicates the outcome of the latest transfer. This
103   type is returned by the PF_PCIE_dma_get_transfer_status() function and used
104   as a parameter for the handler functions registered with the PCIe driver.
105   The following table shows the different statuses of an endpoint DMA transfer
106   indicated by the pf_pcie_ep_dma_status_t type.
107 
108   - PF_PCIE_EP_DMA_NOT_INITIALIZED   - The DMA controller is not initialized
109   - PF_PCIE_EP_DMA_IN_PROGRESS       - A DMA transfer is in progress.
110   - PF_PCIE_EP_DMA_COMPLETED         - The most recent DMA transfer initiated
111                                        by a call to PF_PCIE_dma_write() or
112                                        PF_PCIE_dma_read() has completed successfully.
113   - PF_PCIE_EP_DMA_ERROR             - An error is detected in a DMA controller
114                                        transfer, source, or destination completion.
115  */
116 typedef enum
117 {
118     PF_PCIE_EP_DMA_NOT_INITIALIZED = 0,
119     PF_PCIE_EP_DMA_IN_PROGRESS,
120     PF_PCIE_EP_DMA_COMPLETED,
121     PF_PCIE_EP_DMA_ERROR
122 }pf_pcie_ep_dma_status_t;
123 
124 /***************************************************************************//**
125   The pf_pcie_write_callback_t type defines the function prototype that must be
126   followed by PolarFire PCIe End Point DMA write completion handler function.
127 
128   Declaring and Implementing the write call-back function:
129   The write call-back function should follow the following prototype:
130         void transmit_callback(pf_pcie_ep_dma_status_t status);
131   The actual name of the call-back function is unimportant. You can use any name
132   of your choice for the write call-back function.
133 
134  */
135 typedef void (*pf_pcie_write_callback_t)(pf_pcie_ep_dma_status_t status);
136 
137 /***************************************************************************//**
138   The pf_pcie_read_callback_t type defines the function prototype that must be
139   followed by PolarFire PCIe End Point DMA read completion handler function.
140 
141   Declaring and Implementing the read call-back function:
142   The read call-back function should follow the following prototype:
143     void receive_callback(pf_pcie_ep_dma_status_t status);
144   The actual name of the call-back function is unimportant. You can use any
145   name of your choice for the read call-back function.
146 
147  */
148 typedef void (*pf_pcie_read_callback_t)(pf_pcie_ep_dma_status_t status);
149 
150 /*****************************************************************************
151   The pf_pcie_info_t structure contains the PCIe system(device or bridge) vendor id,
152   bus, device and function number.
153 
154   bus_num
155     Specifies the bus number of the PCIe system.
156 
157   device_num
158     Specifies the device number of the PCIe system.
159 
160   fun_num
161     Specifies the function number of the PCIe system.
162 
163   vendor_id
164     Specifies the vendor id of PCIe endpoint or bridge or switch.
165 
166 */
167 typedef struct
168 {
169     uint16_t bus_num;
170     uint8_t  dev_num;
171     uint8_t  fun_num;
172     uint16_t vendor_id;
173 } pf_pcie_info_t;
174 
175 /*****************************************************************************
176   The pf_pcie_bar_info_t structure contains information about the memory
177   allocated on the host processor for the PCIe endpoint. It is used in the
178   PF_PCIE_allocate_memory() function.
179 
180   bar_address
181     Specifies the memory address allocated on the host processor for the
182     PCIe endpoint BAR.
183 
184   bar_size
185     Specifies the size of the memory allocated on the host processor for
186     the PCIe endpoint BAR.
187 
188 */
189 typedef struct
190 {
191     uint32_t bar0_address;
192     uint32_t bar0_size;
193     uint32_t bar1_address;
194     uint32_t bar1_size;
195     uint32_t bar2_address;
196     uint32_t bar2_size;
197     uint32_t bar3_address;
198     uint32_t bar3_size;
199     uint32_t bar4_address;
200     uint32_t bar4_size;
201     uint32_t bar5_address;
202     uint32_t bar5_size;
203 }pf_pcie_bar_info_t;
204 
205 /******************************************************************************
206   The pf_pcie_ebuff_t structure is used in PCIe enumeration process to store
207   the number of bridges and devices attached to the PCIe root port. The
208   PF_PCIE_enumeration() function returns this structure to the application
209   during PCIe enumeration.
210 
211   bridges
212     Contains information about the attached PCIe bridge or switch, such as the
213     bus number, device number, function number, and vendor ID.
214 
215   devices
216     Contains information about the attached PCIe devices, such as the bus number,
217     device number, function number, and vendor ID.
218 
219   no_of_bridges_attached
220     Specifies the numbers of PCIe bridges attached to the PCIe system.
221 
222   no_of_devices_attached
223     Specifies the numbers of PCIe endpoints attached on the PCIe system.
224 
225 */
226 typedef struct
227 {
228     pf_pcie_info_t bridges[8u];
229     pf_pcie_info_t devices[8u];
230     uint8_t no_of_bridges_attached;
231     uint8_t no_of_devices_attached;
232 } pf_pcie_ebuff_t;
233 /*****************************************************************************
234 PCIe AXI4 Master ATR table configuration structure.
235   The user must create a record of the pf_pcie_master_atr_cfg_t type to hold
236   the configuration of the PCIe AXI4 master ATR table. The
237   PF_PCIE_master_atr_table_init() function is used to create this configuration
238   record by entering the desired values.
239 
240   state
241     Enables and disables the translation address table implementation.
242         • PF_PCIE_ATR_TABLE_ENABLE
243         • PF_PCIE_ATR_TABLE_DISABLE
244   bar_type
245     Sets the PCIe BAR type memory on AXI4 master ATR table to 32-bit or
246     64-bit memory.
247         • PF_PCIE_BAR_TYPE_32BIT_MEM
248         • PF_PCIE_BAR_TYPE_32BIT_PREFET_MEM
249         • PF_PCIE_BAR_TYPE_64BIT_PREFET_MEM
250   bar_size
251     Specifies the size of the PCIe BAR space. The pf_pcie_atr_size_t type is
252     used assign the bar size.
253 
254         • PF_PCIE_SIZE_4KB
255         • PF_PCIE_SIZE_8KB
256         • PF_PCIE_SIZE_16KB
257         • PF_PCIE_SIZE_32KB
258         • PF_PCIE_SIZE_64KB
259         • PF_PCIE_SIZE_128KB
260         ............
261         ............
262         • PF_PCIE_SIZE_512TB
263 
264   table_size
265     Specifies the size of the PCIe AXI4 master address translation table.
266     The pf_pcie_atr_size_t type is used to assign the table size.
267         • PF_PCIE_SIZE_4KB
268         • PF_PCIE_SIZE_8KB
269         • PF_PCIE_SIZE_16KB
270         • PF_PCIE_SIZE_32KB
271         • PF_PCIE_SIZE_64KB
272         • PF_PCIE_SIZE_128KB
273         ............
274         ............
275         • PF_PCIE_SIZE_512TB
276   src_addr
277     Specifies the lower 32-bit source address of the PCIe AXI4 master address
278     translation space.
279 
280   src_addr_msb
281     Specifies the upper 32-bit (63:32-bit) source address of the PCIe AXI4
282     master address translation space.
283 
284   trns_addr
285     Specifies the translated lower 32-bit address of the PCIe AXI4 master
286     address translation space.
287 
288   trns_addr_msb
289     Specifies the translated upper 32-bit(63:32-bit) address of the PCIe AXI4
290     master address translation space.
291 
292 */
293 typedef struct
294 {
295     uint32_t state;
296     pf_pcie_bar_type_t bar_type;
297     pf_pcie_atr_size_t bar_size;
298     pf_pcie_atr_size_t table_size;
299     uint32_t src_addr;
300     uint32_t src_addr_msb;
301     uint32_t trns_addr;
302     uint32_t trns_addr_msb;
303 } pf_pcie_master_atr_cfg_t;
304 /*****************************************************************************
305 PCIe AXI4 Slave ATR table configuration structure.
306   The user must create a record of the pf_pcie_slave_atr_cfg_t type to hold the
307   configuration of the PCIe AXI4 slave ATR table. The PF_PCIE_slave_atr_table_init()
308   function is used to craete this configuration record by entering the desired values.
309 
310   state
311     Enables and disables the translation address table implementation.
312         • PF_PCIE_ATR_TABLE_ENABLE
313         • PF_PCIE_ATR_TABLE_DISABLE
314   size
315     Specifies the size of the PCIe AXI4 slave address translation table.
316     The pf_pcie_atr_size_t type is used to assign the table size.
317         • PF_PCIE_SIZE_4KB
318         • PF_PCIE_SIZE_8KB
319         • PF_PCIE_SIZE_16KB
320         • PF_PCIE_SIZE_32KB
321         • PF_PCIE_SIZE_64KB
322         • PF_PCIE_SIZE_128KB
323         ............
324         ............
325         • PF_PCIE_SIZE_512TB
326 
327   src_addr
328     Specifies the lower 32-bit source address of the PCIe AXI4 slave address
329     translation space.
330 
331   src_addr_msb
332     Specifies the upper 32-bit (63:32-bit) source address of the PCIe AXI4
333     slave address translation space.
334 
335   trns_addr
336     Specifies the translated lower 32-bit address of the PCIe AXI4 slave
337     address translation space.
338 
339   trns_addr_msb
340     Specifies the translated upper 32-bit (63:32-bit) address of the PCIe
341     AXI4 slave address translation space.
342 
343 */
344 typedef struct
345 {
346     uint32_t state;
347     pf_pcie_atr_size_t size;
348     uint32_t src_addr;
349     uint32_t src_addr_msb;
350     uint32_t trns_addr;
351     uint32_t trns_addr_msb;
352 } pf_pcie_slave_atr_cfg_t;
353 
354 #ifdef __cplusplus
355 }
356 #endif
357 
358 #endif /* PF_PCIESS_H_ */
359