1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_TFDP_V1_H 7 #define _MEC5_TFDP_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief Trace FIFO Debug Port (MEC_TFDP) 15 */ 16 17 typedef struct mec_tfdp_regs { /*!< (@ 0x40008C00) MEC_TFDP Structure */ 18 __IOM uint8_t DATA; /*!< (@ 0x00000000) TFDP data */ 19 __IM uint8_t RESERVED[3]; 20 __IOM uint8_t CTRL; /*!< (@ 0x00000004) TFDP control */ 21 } MEC_TFDP_Type; /*!< Size = 5 (0x5) */ 22 23 /** @} */ /* End of group Device_Peripheral_peripherals */ 24 25 /** @addtogroup PosMask_peripherals 26 * @{ 27 */ 28 /* ========================================================= CTRL ========================================================== */ 29 #define MEC_TFDP_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ 30 #define MEC_TFDP_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 31 #define MEC_TFDP_CTRL_EDGE_SEL_Pos (1UL) /*!< EDGE_SEL (Bit 1) */ 32 #define MEC_TFDP_CTRL_EDGE_SEL_Msk (0x2UL) /*!< EDGE_SEL (Bitfield-Mask: 0x01) */ 33 #define MEC_TFDP_CTRL_CLKDIV_Pos (2UL) /*!< CLKDIV (Bit 2) */ 34 #define MEC_TFDP_CTRL_CLKDIV_Msk (0xcUL) /*!< CLKDIV (Bitfield-Mask: 0x03) */ 35 #define MEC_TFDP_CTRL_IPDLY_Pos (4UL) /*!< IPDLY (Bit 4) */ 36 #define MEC_TFDP_CTRL_IPDLY_Msk (0x70UL) /*!< IPDLY (Bitfield-Mask: 0x07) */ 37 38 /** @} */ /* End of group PosMask_peripherals */ 39 40 /** @addtogroup EnumValue_peripherals 41 * @{ 42 */ 43 /* ========================================================= CTRL ========================================================== */ 44 /* ============================================= MEC_TFDP CTRL ENABLE [0..0] ============================================== */ 45 typedef enum { /*!< MEC_TFDP_CTRL_ENABLE */ 46 MEC_TFDP_CTRL_ENABLE_ON = 1, /*!< ON : Enable */ 47 } MEC_TFDP_CTRL_ENABLE_Enum; 48 49 /* ============================================ MEC_TFDP CTRL EDGE_SEL [1..1] ============================================= */ 50 typedef enum { /*!< MEC_TFDP_CTRL_EDGE_SEL */ 51 MEC_TFDP_CTRL_EDGE_SEL_RISING = 0, /*!< RISING : Rising Edge */ 52 MEC_TFDP_CTRL_EDGE_SEL_FALLING = 1, /*!< FALLING : Falling Edge */ 53 } MEC_TFDP_CTRL_EDGE_SEL_Enum; 54 55 /* ============================================= MEC_TFDP CTRL CLKDIV [2..3] ============================================== */ 56 typedef enum { /*!< MEC_TFDP_CTRL_CLKDIV */ 57 MEC_TFDP_CTRL_CLKDIV_24M = 0, /*!< 24M : 24MHz */ 58 MEC_TFDP_CTRL_CLKDIV_12M = 1, /*!< 12M : 12MHz */ 59 MEC_TFDP_CTRL_CLKDIV_6M = 2, /*!< 6M : 6MHz */ 60 } MEC_TFDP_CTRL_CLKDIV_Enum; 61 62 /* ============================================== MEC_TFDP CTRL IPDLY [4..6] ============================================== */ 63 typedef enum { /*!< MEC_TFDP_CTRL_IPDLY */ 64 MEC_TFDP_CTRL_IPDLY_1CLK = 0, /*!< 1CLK : 1 TFDP clock1 delay */ 65 MEC_TFDP_CTRL_IPDLY_2CLK = 1, /*!< 2CLK : 2 TFDP clocks delay */ 66 MEC_TFDP_CTRL_IPDLY_3CLK = 2, /*!< 3CLK : 3 TFDP clocks delay */ 67 MEC_TFDP_CTRL_IPDLY_4CLK = 3, /*!< 4CLK : 4 TFDP clocks delay */ 68 MEC_TFDP_CTRL_IPDLY_5CLK = 4, /*!< 5CLK : 5 TFDP clocks delay */ 69 MEC_TFDP_CTRL_IPDLY_6CLK = 5, /*!< 6CLK : 6 TFDP clocks delay */ 70 MEC_TFDP_CTRL_IPDLY_7CLK = 6, /*!< 7CLK : 7 TFDP clocks delay */ 71 MEC_TFDP_CTRL_IPDLY_8CLK = 7, /*!< 8CLK : 8 TFDP clocks delay */ 72 } MEC_TFDP_CTRL_IPDLY_Enum; 73 74 /** @} */ /* End of group EnumValue_peripherals */ 75 76 #endif /* _MEC5_TFDP_V1_H */ 77
