1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_ESPI_TAF_H 7 #define _MEC_ESPI_TAF_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 13 #include "mec_qspi_api.h" 14 15 /* Interfaces to any C modules */ 16 #ifdef __cplusplus 17 extern "C" 18 { 19 #endif 20 21 /* forward declarations */ 22 struct mec_espi_io_regs; 23 struct mec_espi_mem_regs; 24 struct mec_espi_vw_regs; 25 struct mec_espi_taf_regs; 26 27 /* ---- eSPI Target Attached Flash (TAF) ---- */ 28 enum mec_espi_taf_intr { 29 MEC_ESPI_TAF_INTR_ECP_DONE_POS = 0, 30 MEC_ESPI_TAF_INTR_HWMON_ERR_POS, 31 MEC_ESPI_TAF_INTR_POS_MAX, 32 }; 33 34 #define MEC_ESPI_TAF_HW_CFG_FLAG_FREQ_POS 0 35 #define MEC_ESPI_TAF_HW_CFG_FLAG_CPHA_POS 1 36 #define MEC_ESPI_TAF_HW_CFG_FLAG_CSTM_POS 2 37 #define MEC_ESPI_TAF_HW_CFG_FLAG_TAPS_POS 3 38 39 /* enable TAF prefetch */ 40 #define MEC_ESPI_TAF_HW_CFG_FLAG_PFEN_POS 4 41 /* Use expedited prefetch instead of default */ 42 #define MEC_ESPI_TAF_HW_CFG_FLAG_PFEXP_POS 5 43 44 #define MEC_ESPI_TAF_VERSION 3 45 #define MEC_ESPI_TAF_GENERIC_DESCR_MAX 4 46 #define MEC_ESPI_TAF_TAGMAP_MAX 3 47 #define MEC_ESPI_TAF_PROT_REG_MAX 17 48 49 /* TAF engine start indices of descriptor chains */ 50 #define MCHP_TAF_CM_EXIT_START_DESCR 12u 51 #define MCHP_TAF_CM_EXIT_LAST_DESCR 13u 52 #define MCHP_TAF_POLL_STS_START_DESCR 14u 53 #define MCHP_TAF_POLL_STS_END_DESCR 15u 54 55 struct espi_taf_hw_cfg { 56 uint8_t version; 57 uint8_t flags; 58 uint8_t qspi_freq_mhz; 59 uint8_t qspi_cpha; 60 uint16_t qtaps_sel; 61 uint32_t qspi_cs_timing; 62 uint16_t flash_pd_timeout; 63 uint16_t flash_pd_min_interval; 64 uint32_t generic_descr[MEC_ESPI_TAF_GENERIC_DESCR_MAX]; 65 uint32_t tag_map[MEC_ESPI_TAF_TAGMAP_MAX]; 66 }; 67 68 /* Until Zephyr renames SAF to TAF we need this hack */ 69 #define espi_saf_hw_cfg espi_taf_hw_cfg 70 71 /* Flags */ 72 #define MCHP_FLASH_FLAG_ADDR32 MEC_BIT(0) 73 #define MCHP_FLASH_FLAG_V1_MSK 0xffu 74 #define MCHP_FLASH_FLAG_V2_MSK 0xff00u 75 #define MCHP_FLASH_FLAG_V2_PD_CS0_EN MEC_BIT(8) 76 #define MCHP_FLASH_FLAG_V2_PD_CS1_EN MEC_BIT(9) 77 #define MCHP_FLASH_FLAG_V2_PD_CS0_EC_WK_EN MEC_BIT(10) 78 #define MCHP_FLASH_FLAG_V2_PD_CS1_EC_WK_EN MEC_BIT(11) 79 80 #define MEC_ESPI_TAF_QSPI_FLASH_DESCR_MAX 6u 81 82 struct espi_taf_flash_cfg { 83 uint8_t version; 84 uint8_t rsvd1; 85 uint16_t flags; 86 uint32_t flashsz; 87 uint8_t rd_freq_mhz; 88 uint8_t freq_mhz; 89 uint8_t rsvd2[2]; 90 uint32_t opa; 91 uint32_t opb; 92 uint32_t opc; 93 uint32_t opd; 94 uint32_t rpmc_op1; 95 uint16_t poll2_mask; 96 uint16_t cont_prefix; 97 uint16_t cs_cfg_descr_ids; 98 uint16_t rsvd3; 99 uint32_t descr[MEC_ESPI_TAF_QSPI_FLASH_DESCR_MAX]; 100 }; 101 102 /* EC Portal interrupt status and enables */ 103 enum mec_taf_ecp_intr_status { 104 MEC_TAF_ECP_STS_DONE_POS = 0, /* The only EC port interrupt enable */ 105 MEC_TAF_ECP_STS_DONE_AN_POS, 106 MEC_TAF_ECP_STS_TIMEOUT_POS, 107 MEC_TAF_ECP_STS_OOR_POS, 108 MEC_TAF_ECP_STS_AVL_POS, 109 MEC_TAF_ECP_STS_CROSS_4KB_POS, 110 MEC_TAF_ECP_STS_INVAL_ERSZ_POS, 111 MEC_TAF_ECP_STS_START_OVFL_POS, 112 MEC_TAF_ECP_STS_BAD_REQ_POS, 113 }; 114 115 /* Host monitor error interrupt status and enables */ 116 enum mec_taf_hmon_intr_status { 117 MEC_TAF_HMON_STS_TIMEOUT_POS = 0, 118 MEC_TAF_HMON_STS_OOR_POS, 119 MEC_TAF_HMON_STS_AVL_POS, 120 MEC_TAF_HMON_STS_CROSS_4KB_POS, 121 MEC_TAF_HMON_STS_INVAL_ERSZ_POS, 122 }; 123 124 enum mec_taf_protection_region_index { 125 MEC_TAF_PR0_IDX = 0, 126 MEC_TAF_PR1_IDX, 127 MEC_TAF_PR2_IDX, 128 MEC_TAF_PR3_IDX, 129 MEC_TAF_PR4_IDX, 130 MEC_TAF_PR5_IDX, 131 MEC_TAF_PR6_IDX, 132 MEC_TAF_PR7_IDX, 133 MEC_TAF_PR8_IDX, 134 MEC_TAF_PR9_IDX, 135 MEC_TAF_PR10_IDX, 136 MEC_TAF_PR11_IDX, 137 MEC_TAF_PR12_IDX, 138 MEC_TAF_PR13_IDX, 139 MEC_TAF_PR14_IDX, 140 MEC_TAF_PR15_IDX, 141 MEC_TAF_PR16_IDX, 142 MEC_TAF_PR_IDX_MAX, 143 }; 144 145 /* 146 * 17 flash protection regions 147 * Each region is described by: 148 * SPI start address. 20-bits = bits[31:12] of SPI address 149 * SPI limit address. 20-bits = bits[31:12] of last SPI address 150 * 8-bit bit map of eSPI master write-erase permission 151 * 8-bit bit map of eSPI maste read permission 152 * eSPI master numbers 0 - 7 correspond to bits 0 - 7. 153 * 154 * Protection region lock: 155 * One 32-bit register with bits[16:0] -> protection regions 16:0 156 * 157 * eSPI Host maps threads by a tag number to master numbers. 158 * Thread numbers are 4-bit 159 * Master numbers are 3-bit 160 * Master number Thread numbers Description 161 * 0 0h, 1h Host PCH HW init 162 * 1 2h, 3h Host CPU access(HW/BIOS/SMM/SW) 163 * 2 4h, 5h Host PCH ME 164 * 3 6h Host PCH LAN 165 * 4 N/A Not defined/used 166 * 5 N/A EC Firmware portal access 167 * 6 9h, Dh Host PCH IE 168 * 7 N/A Not defined/used 169 * 170 * NOTE: eSPI SAF specification allows master 0 (Host PCH HW) full 171 * access to all protection regions. 172 * 173 * SAF TAG Map registers 0 - 2 map eSPI TAG values 0h - Fh to 174 * the three bit master number. Each 32-bit register contains 3-bit 175 * fields aligned on nibble boundaries holding the master number 176 * associated with the eSPI tag (thread) number. 177 * A master value of 7h in a field indicates a non-existent map entry. 178 * 179 * bit map of registers to program 180 * b[2:0] = TAG Map[2:0] 181 * b[20:4] = ProtectionRegions[16:0] 182 * bit map of PR's to lock 183 * b[20:4] = ProtectionRegions[16:0] 184 * 185 */ 186 #define MCHP_TAF_PR_FLAG_ENABLE 0x01U 187 #define MCHP_TAF_PR_FLAG_LOCK 0x02U 188 189 #define MCHP_TAF_REQ_FROM_HOST_PCH 0U 190 #define MCHP_TAF_REQ_FROM_HOST_CPU 1U 191 #define MCHP_TAF_REQ_FROM_HOST_PCH_ME 2U 192 #define MCHP_TAF_REQ_FROM_HOST_PCH_LAN 3U 193 #define MCHP_TAF_REQ_FROM_RSVD4 4U 194 #define MCHP_TAF_REQ_FROM_EC 5U 195 #define MCHP_TAF_REQ_FROM_HOST_PCH_IE 6U 196 197 struct espi_taf_pr { 198 uint32_t start; 199 uint32_t size; 200 uint8_t req_bm_we; 201 uint8_t req_bm_rd; 202 uint8_t pr_num; 203 uint8_t flags; /* bit[0]==1 is lock the region */ 204 }; 205 206 struct espi_taf_protection { 207 size_t nregions; 208 const struct espi_taf_pr *pregions; 209 }; 210 211 /* future eSPI name change */ 212 #define espi_saf_protection espi_taf_protection 213 214 /* API */ 215 void mec_hal_espi_taf_girq_ctrl(uint8_t enable, uint32_t flags); 216 void mec_hal_espi_taf_girq_status_clr(uint32_t flags); 217 uint32_t mec_hal_espi_taf_girq_status(void); 218 uint32_t mec_hal_espi_taf_girq_result(void); 219 220 bool mec_hal_espi_taf_is_activated(void); 221 void mec_hal_espi_taf_activate(uint8_t enable); 222 223 /* TAF initialization */ 224 #define MEC_ESPI_TAF_INIT_RESET_POS 0 225 #define MEC_ESPI_TAF_CAF_SHARE_POS 1 226 227 int mec_hal_espi_taf_init(struct mec_espi_taf_regs *regs, uint32_t initflags); 228 229 /* TAF configuration */ 230 int mec_hal_espi_taf_qspi_init(struct mec_espi_taf_regs *tregs, struct mec_qspi_regs *qregs, 231 const struct espi_taf_hw_cfg *thwcfg); 232 233 /* TAF protection regions */ 234 bool mec_hal_espi_taf_pr_is_dirty(struct mec_espi_taf_regs *regs, uint8_t pr_idx); 235 int mec_hal_espi_taf_pr_dirty_clr(struct mec_espi_taf_regs *regs, uint8_t pr_idx); 236 int mec_hal_espi_taf_pr_dirty_clr_mask(struct mec_espi_taf_regs *regs, uint32_t mask); 237 238 uint32_t mec_hal_espi_taf_pr_lock_get(struct mec_espi_taf_regs *regs); 239 int mec_hal_espi_taf_pr_lock(struct mec_espi_taf_regs *regs, uint32_t lockmap); 240 241 int mec_hal_espi_taf_pr_set(struct mec_espi_taf_regs *regs, struct espi_taf_pr *pr); 242 243 #ifdef __cplusplus 244 } 245 #endif 246 247 #endif /* #ifndef _MEC_ESPI_TAF_H */ 248
