1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_RCID_V1_H 7 #define _MEC5_RCID_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief RC ID (MEC_RCID) 15 */ 16 17 typedef struct mec_rcid_regs { /*!< (@ 0x40001400) MEC_RCID Structure */ 18 __IOM uint32_t CTRL; /*!< (@ 0x00000000) RC ID control */ 19 __IOM uint32_t DATA; /*!< (@ 0x00000004) RC ID 16-bit data */ 20 } MEC_RCID_Type; /*!< Size = 8 (0x8) */ 21 22 /** @} */ /* End of group Device_Peripheral_peripherals */ 23 24 /** @addtogroup PosMask_peripherals 25 * @{ 26 */ 27 /* ========================================================= CTRL ========================================================== */ 28 #define MEC_RCID_CTRL_DONE_Pos (0UL) /*!< DONE (Bit 0) */ 29 #define MEC_RCID_CTRL_DONE_Msk (0x1UL) /*!< DONE (Bitfield-Mask: 0x01) */ 30 #define MEC_RCID_CTRL_TC_Pos (1UL) /*!< TC (Bit 1) */ 31 #define MEC_RCID_CTRL_TC_Msk (0x2UL) /*!< TC (Bitfield-Mask: 0x01) */ 32 #define MEC_RCID_CTRL_CY_Pos (2UL) /*!< CY (Bit 2) */ 33 #define MEC_RCID_CTRL_CY_Msk (0x4UL) /*!< CY (Bitfield-Mask: 0x01) */ 34 #define MEC_RCID_CTRL_START_Pos (6UL) /*!< START (Bit 6) */ 35 #define MEC_RCID_CTRL_START_Msk (0x40UL) /*!< START (Bitfield-Mask: 0x01) */ 36 #define MEC_RCID_CTRL_ENABLE_Pos (7UL) /*!< ENABLE (Bit 7) */ 37 #define MEC_RCID_CTRL_ENABLE_Msk (0x80UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 38 #define MEC_RCID_CTRL_CLKSEL_Pos (8UL) /*!< CLKSEL (Bit 8) */ 39 #define MEC_RCID_CTRL_CLKSEL_Msk (0x300UL) /*!< CLKSEL (Bitfield-Mask: 0x03) */ 40 41 /** @} */ /* End of group PosMask_peripherals */ 42 43 /** @addtogroup EnumValue_peripherals 44 * @{ 45 */ 46 /* ========================================================= CTRL ========================================================== */ 47 /* ============================================== MEC_RCID CTRL DONE [0..0] =============================================== */ 48 typedef enum { /*!< MEC_RCID_CTRL_DONE */ 49 MEC_RCID_CTRL_DONE_ACTIVE = 1, /*!< ACTIVE : Done status is active */ 50 } MEC_RCID_CTRL_DONE_Enum; 51 52 /* =============================================== MEC_RCID CTRL TC [1..1] ================================================ */ 53 typedef enum { /*!< MEC_RCID_CTRL_TC */ 54 MEC_RCID_CTRL_TC_ACTIVE = 1, /*!< ACTIVE : Discharge phase is complete status */ 55 } MEC_RCID_CTRL_TC_Enum; 56 57 /* =============================================== MEC_RCID CTRL CY [2..2] ================================================ */ 58 typedef enum { /*!< MEC_RCID_CTRL_CY */ 59 MEC_RCID_CTRL_CY_ACTIVE = 1, /*!< ACTIVE : Measurement error status is active */ 60 } MEC_RCID_CTRL_CY_Enum; 61 62 /* ============================================== MEC_RCID CTRL START [6..6] ============================================== */ 63 typedef enum { /*!< MEC_RCID_CTRL_START */ 64 MEC_RCID_CTRL_START_MEAS = 1, /*!< MEAS : Measurement start */ 65 } MEC_RCID_CTRL_START_Enum; 66 67 /* ============================================= MEC_RCID CTRL ENABLE [7..7] ============================================== */ 68 typedef enum { /*!< MEC_RCID_CTRL_ENABLE */ 69 MEC_RCID_CTRL_ENABLE_ON = 1, /*!< ON : Enable RC-ID block(ungate clocks) */ 70 } MEC_RCID_CTRL_ENABLE_Enum; 71 72 /* ============================================= MEC_RCID CTRL CLKSEL [8..9] ============================================== */ 73 typedef enum { /*!< MEC_RCID_CTRL_CLKSEL */ 74 MEC_RCID_CTRL_CLKSEL_48M = 0, /*!< 48M : Select 48MHz clock */ 75 MEC_RCID_CTRL_CLKSEL_24M = 1, /*!< 24M : Select 24MHz clock */ 76 MEC_RCID_CTRL_CLKSEL_12M = 2, /*!< 12M : Select 12MHz clock */ 77 MEC_RCID_CTRL_CLKSEL_6M = 3, /*!< 6M : Select 6MHz clock */ 78 } MEC_RCID_CTRL_CLKSEL_Enum; 79 80 /** @} */ /* End of group EnumValue_peripherals */ 81 82 #endif /* _MEC5_RCID_V1_H */ 83
