1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_PS2_API_H 7 #define _MEC_PS2_API_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 13 #include "mec_defs.h" 14 #include "mec_dmac_api.h" 15 #include "mec_retval.h" 16 17 #if MEC5_PS2_INSTANCES 18 19 /* Interfaces to any C modules */ 20 #ifdef __cplusplus 21 extern "C" 22 { 23 #endif 24 25 /* PS/2 Controller with wake capability */ 26 27 struct mec_ps2_regs; /* forward reference */ 28 29 enum mec_ps2_ports { 30 MEC5_PS2_PORT_A = 0, 31 MEC5_PS2_PORT_B, 32 MEC5_PS2_PORT_MAX, 33 }; 34 35 enum mec_ps2_status { 36 MEC_PS2_STS_DATA_RDY = MEC_BIT(0), 37 MEC_PS2_STS_RX_TMOUT = MEC_BIT(1), 38 MEC_PS2_STS_PARITY_ERR = MEC_BIT(2), 39 MEC_PS2_STS_FRAME_ERR = MEC_BIT(3), 40 MEC_PS2_STS_TX_IDLE = MEC_BIT(4), 41 MEC_PS2_STS_TX_TMOUT = MEC_BIT(5), 42 MEC_PS2_STS_RX_BUSY = MEC_BIT(6), 43 MEC_PS2_STS_TX_START_TMOUT = MEC_BIT(7), 44 }; 45 46 #define MEC_PS2_STATUS_ALL 0xffu 47 48 #define MEC_PS2_FLAGS_ENABLE 0x01u 49 #define MEC_PS2_FLAGS_RESET 0x02u 50 #define MEC_PS2_FLAGS_PARITY_POS 2 51 #define MEC_PS2_FLAGS_PARITY_MSK 0xcu 52 #define MEC_PS2_FLAGS_PARITY_ODD 0 53 #define MEC_PS2_FLAGS_PARITY_EVEN 0x4u 54 #define MEC_PS2_FLAGS_PARITY_NONE 0x8u 55 #define MEC_PS2_FLAGS_STOP_BITS_POS 4 56 #define MEC_PS2_FLAGS_STOP_BITS_MSK 0x30u 57 #define MEC_PS2_FLAGS_STOP_BIT_HI 0 58 #define MEC_PS2_FLAGS_STOP_BIT_LO 0x10u 59 #define MEC_PS2_FLAGS_STOP_BIT_NONE 0x20u 60 #define MEC_PS2_FLAGS_INTR_EN 0x100u 61 62 int mec_hal_ps2_init(struct mec_ps2_regs *base, uint32_t flags); 63 64 #define MEC_PS2_CTRL_OP_DIR_RX 0 65 #define MEC_PS2_CTRL_OP_DIR_TX 1 66 #define MEC_PS2_CTRL_OP_DISABLE 0 67 #define MEC_PS2_CTRL_OP_ENABLE 2 68 69 #define MEC_PS2_CTRL_OP_MSK_DIR 0x01u 70 #define MEC_PS2_CTRL_OP_MSK_EN 0x02u 71 72 int mec_hal_ps2_control(struct mec_ps2_regs *regs, uint8_t operand, uint8_t opmask); 73 74 bool mec_hal_ps2_is_enabled(struct mec_ps2_regs *regs); 75 76 int mec_hal_ps2_girq_ctrl(struct mec_ps2_regs *base, uint8_t enable); 77 uint32_t mec_hal_ps2_girq_result(struct mec_ps2_regs *base); 78 int mec_hal_ps2_girq_clr(struct mec_ps2_regs *base); 79 80 int mec_hal_ps2_girq_wake_enable(struct mec_ps2_regs *base, uint8_t port, uint8_t enable); 81 uint32_t mec_hal_ps2_girq_wake_result(struct mec_ps2_regs *base, uint8_t port); 82 void mec_hal_ps2_girq_wake_clr(struct mec_ps2_regs *base, uint8_t port); 83 84 uint32_t mec_hal_ps2_get_status(struct mec_ps2_regs *regs); 85 void mec_hal_ps2_clr_status(struct mec_ps2_regs *regs, uint32_t clrmsk); 86 uint8_t mec_hal_ps2_read_data(struct mec_ps2_regs *regs); 87 void mec_hal_ps2_send_data(struct mec_ps2_regs *regs, uint8_t data); 88 89 /* Enable/disable port wake by zero based controller instance number */ 90 int mec_hal_ps2_inst_wake_enable(uint8_t instance, uint8_t port, uint8_t enable); 91 int mec_hal_ps2_inst_wake_status_clr(uint8_t instance, uint8_t port); 92 93 /* For all PS/2 controllers in the SoC enable or disable the wake 94 * GIRQ for all ports. If disable also clear the GIRQ latched status. 95 * NOTE: if a port is not enabled by pinctrl the port should not cause 96 * a wake event. 97 */ 98 void mec_hal_ps2_wake_enables(uint8_t enable); 99 100 #ifdef __cplusplus 101 } 102 #endif 103 104 #endif /* MEC5_PS2_INSTANCES */ 105 #endif /* #ifndef _MEC_PS2_API_H */ 106
