1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_I3C_HOST_V2_H 7 #define _MEC5_I3C_HOST_V2_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 /** 13 * @brief I3C Primary Controller (MEC_I3C_HOST0) 14 */ 15 16 typedef struct mec_i3c_host_regs { /*!< (@ 0x40010800) MEC_I3C_HOST0 Structure */ 17 __IOM uint32_t DEV_CTRL; /*!< (@ 0x00000000) Target device control register */ 18 __IOM uint32_t DEV_ADDR; /*!< (@ 0x00000004) Target device address register */ 19 __IM uint32_t HW_CAP; /*!< (@ 0x00000008) I3C Host controller hardware capabilities */ 20 __IOM uint32_t CMD; /*!< (@ 0x0000000C) Command register */ 21 __IOM uint32_t RESP; /*!< (@ 0x00000010) Response register */ 22 23 union { 24 __OM uint32_t TX_DATA; /*!< (@ 0x00000014) Transmit data register */ 25 __IM uint32_t RX_DATA; /*!< (@ 0x00000014) Receive data register */ 26 }; 27 __IOM uint32_t IBI_QUE_STS; /*!< (@ 0x00000018) IBI Queue status register */ 28 __IOM uint32_t QUE_THLD_CTRL; /*!< (@ 0x0000001C) Queue threshold control register */ 29 __IOM uint32_t DB_THLD_CTRL; /*!< (@ 0x00000020) Data buffer threshold control register */ 30 __IOM uint32_t IBI_QUE_CTRL; /*!< (@ 0x00000024) IBI Queue control register */ 31 __IM uint32_t RESERVED[3]; 32 __IOM uint32_t RST_CTRL; /*!< (@ 0x00000034) Reset control register */ 33 __IM uint32_t RESERVED1; 34 __IOM uint32_t INTR_STS; /*!< (@ 0x0000003C) Interrupt status register */ 35 __IOM uint32_t INTR_EN; /*!< (@ 0x00000040) Interrupt enable register */ 36 __IOM uint32_t INTR_SIG_EN; /*!< (@ 0x00000044) Interrupt signal enable register */ 37 __IOM uint32_t INTR_FORCE_EN; /*!< (@ 0x00000048) Interrupt force enable register */ 38 __IOM uint32_t QUE_STS_LVL; /*!< (@ 0x0000004C) Queue status level register */ 39 __IOM uint32_t DB_STS_LVL; /*!< (@ 0x00000050) Data buffer status level register */ 40 __IOM uint32_t PRES_STATE; /*!< (@ 0x00000054) Present state register */ 41 __IM uint32_t RESERVED2; 42 __IOM uint32_t DAT_PTR; /*!< (@ 0x0000005C) Device address table(DAT) pointer register */ 43 __IOM uint32_t DCT_PTR; /*!< (@ 0x00000060) Device characteristic table(DCT) pointer register */ 44 __IM uint32_t RESERVED3[2]; 45 __IOM uint32_t VENR_PTR; /*!< (@ 0x0000006C) Vendor specific registers pointer */ 46 __IM uint32_t RESERVED4[16]; 47 __IOM uint32_t DEV_EXT_CTRL; /*!< (@ 0x000000B0) Device extended control register */ 48 __IOM uint32_t SCL_OD_TM; /*!< (@ 0x000000B4) Open drain timing register */ 49 __IOM uint32_t SCL_PP_TM; /*!< (@ 0x000000B8) Push-pull timing register */ 50 __IOM uint32_t SCL_I2C_FM_TM; /*!< (@ 0x000000BC) Fast mode timing register */ 51 __IOM uint32_t SCL_I2C_FMP_TM; /*!< (@ 0x000000C0) Fast mode plus timing register */ 52 __IM uint32_t RESERVED5; 53 __IOM uint32_t SCL_ELC_TM; /*!< (@ 0x000000C8) SCL Extended low count timing register */ 54 __IOM uint32_t SCL_TBLC_TM; /*!< (@ 0x000000CC) SCL termination bit low count timing register */ 55 __IOM uint32_t SDA_HMSD_TM; /*!< (@ 0x000000D0) SDA hold mode switch delay timing register */ 56 __IOM uint32_t BUS_FREE_TM; /*!< (@ 0x000000D4) Bus free timing register */ 57 __IOM uint32_t BUS_IDLE_TM; /*!< (@ 0x000000D8) Bus idle timing register */ 58 __IOM uint32_t SCL_LMST_TM; /*!< (@ 0x000000DC) SCL low MST timeout register */ 59 __IM uint32_t VER_ID; /*!< (@ 0x000000E0) I3C version ID register */ 60 __IM uint32_t VER_TYPE; /*!< (@ 0x000000E4) I3C version type register */ 61 __IM uint32_t QUE_SIZE_CAP; /*!< (@ 0x000000E8) I3C Queue size capability register */ 62 __IM uint32_t RESERVED6[69]; 63 __IOM uint32_t DCT_LOC[44]; /*!< (@ 0x00000200) I3C Device characteristic table location register */ 64 __IM uint32_t RESERVED7[4]; 65 __IOM uint32_t DAT_LOC[11]; /*!< (@ 0x000002C0) I3C Device address table location registers */ 66 __IM uint32_t RESERVED8[5]; 67 __IOM uint32_t HOST_CFG; /*!< (@ 0x00000300) I3C Host config register */ 68 __IOM uint32_t HOST_RST_CTRL; /*!< (@ 0x00000304) I3C Host reset control register */ 69 __IOM uint32_t HOST_DMA_TX_TMOUT; /*!< (@ 0x00000308) I3C Host TX DMA timerout register */ 70 __IOM uint32_t HOST_DMA_RX_TMOUT; /*!< (@ 0x0000030C) I3C Host RX DMA timerout register */ 71 __IOM uint32_t STK_SDA_TMOUT; /*!< (@ 0x00000310) I3C stuck SDA timeout register */ 72 __IOM uint32_t HWRAP_STS; /*!< (@ 0x00000314) I3C Host wrapper status register */ 73 __IOM uint32_t HWRP_INTR_EN; /*!< (@ 0x00000318) I3C Host wrapper interrupt enable register */ 74 __IM uint32_t RESERVED9[45]; 75 __IOM uint32_t PAD_TST; /*!< (@ 0x000003D0) I3C pad test register */ 76 __IOM uint32_t I3C_DBG0; /*!< (@ 0x000003D4) I3C debug 0 register */ 77 __IOM uint32_t I3C_DBG1; /*!< (@ 0x000003D8) I3C debug 1 register */ 78 } MEC_I3C_HOST_Type; /*!< Size = 988 (0x3dc) */ 79 80 /** @} */ /* End of group Device_Peripheral_peripherals */ 81 82 /** @addtogroup PosMask_peripherals 83 * @{ 84 */ 85 86 /** @} */ /* End of group PosMask_peripherals */ 87 88 /** @addtogroup EnumValue_peripherals 89 * @{ 90 */ 91 /* ================================================= MEC_I3C_HOST DCT_LOC ================================================= */ 92 typedef enum { /*!< MEC_I3C_HOST_DCT_LOC */ 93 MEC_I3C_DCT_DEV1_T1_L1 = 0, /*!< T1_L1 : Device 1: Table 1 Location 1 */ 94 MEC_I3C_DCT_DEV1_T1_L2 = 1, /*!< T1_L2 : Device 1: Table 1 Location 2 */ 95 MEC_I3C_DCT_DEV1_T1_L3 = 2, /*!< T1_L3 : Device 1: Table 1 Location 3 */ 96 MEC_I3C_DCT_DEV1_T1_L4 = 3, /*!< T1_L4 : Device 1: Table 1 Location 4 */ 97 MEC_I3C_DCT_DEV1_T2_L1 = 4, /*!< T2_L1 : Device 1: Table 2 Location 1 */ 98 MEC_I3C_DCT_DEV1_T2_L2 = 5, /*!< T2_L2 : Device 1: Table 2 Location 2 */ 99 MEC_I3C_DCT_DEV1_T2_L3 = 6, /*!< T2_L3 : Device 1: Table 2 Location 3 */ 100 MEC_I3C_DCT_DEV1_T2_L4 = 7, /*!< T2_L4 : Device 1: Table 2 Location 4 */ 101 MEC_I3C_DCT_DEV1_T3_L1 = 8, /*!< T3_L1 : Device 1: Table 3 Location 1 */ 102 MEC_I3C_DCT_DEV1_T3_L2 = 8, /*!< T3_L2 : Device 1: Table 3 Location 2 */ 103 MEC_I3C_DCT_DEV1_T3_L3 = 10, /*!< T3_L3 : Device 1: Table 3 Location 3 */ 104 MEC_I3C_DCT_DEV1_T3_L4 = 11, /*!< T3_L4 : Device 1: Table 3 Location 4 */ 105 MEC_I3C_DCT_DEV1_T4_L1 = 12, /*!< T4_L1 : Device 1: Table 4 Location 1 */ 106 MEC_I3C_DCT_DEV1_T4_L2 = 13, /*!< T4_L2 : Device 1: Table 4 Location 2 */ 107 MEC_I3C_DCT_DEV1_T4_L3 = 14, /*!< T4_L3 : Device 1: Table 4 Location 3 */ 108 MEC_I3C_DCT_DEV1_T4_L4 = 15, /*!< T4_L4 : Device 1: Table 4 Location 4 */ 109 MEC_I3C_DCT_DEV1_T5_L1 = 16, /*!< T5_L1 : Device 1: Table 5 Location 1 */ 110 MEC_I3C_DCT_DEV1_T5_L2 = 17, /*!< T5_L2 : Device 1: Table 5 Location 2 */ 111 MEC_I3C_DCT_DEV1_T5_L3 = 18, /*!< T5_L3 : Device 1: Table 5 Location 3 */ 112 MEC_I3C_DCT_DEV1_T5_L4 = 19, /*!< T5_L4 : Device 1: Table 5 Location 4 */ 113 MEC_I3C_DCT_DEV1_T6_L1 = 20, /*!< T6_L1 : Device 1: Table 6 Location 1 */ 114 MEC_I3C_DCT_DEV1_T6_L2 = 21, /*!< T6_L2 : Device 1: Table 6 Location 2 */ 115 MEC_I3C_DCT_DEV1_T6_L3 = 22, /*!< T6_L3 : Device 1: Table 6 Location 3 */ 116 MEC_I3C_DCT_DEV1_T6_L4 = 23, /*!< T6_L4 : Device 1: Table 6 Location 4 */ 117 MEC_I3C_DCT_DEV1_T7_L1 = 24, /*!< T7_L1 : Device 1: Table 7 Location 1 */ 118 MEC_I3C_DCT_DEV1_T7_L2 = 25, /*!< T7_L2 : Device 1: Table 7 Location 2 */ 119 MEC_I3C_DCT_DEV1_T7_L3 = 26, /*!< T7_L3 : Device 1: Table 7 Location 3 */ 120 MEC_I3C_DCT_DEV1_T7_L4 = 27, /*!< T7_L4 : Device 1: Table 7 Location 4 */ 121 MEC_I3C_DCT_DEV1_T8_L1 = 28, /*!< T8_L1 : Device 1: Table 8 Location 1 */ 122 MEC_I3C_DCT_DEV1_T8_L2 = 29, /*!< T8_L2 : Device 1: Table 8 Location 2 */ 123 MEC_I3C_DCT_DEV1_T8_L3 = 30, /*!< T8_L3 : Device 1: Table 8 Location 3 */ 124 MEC_I3C_DCT_DEV1_T8_L4 = 31, /*!< T8_L4 : Device 1: Table 8 Location 4 */ 125 MEC_I3C_DCT_DEV1_T9_L1 = 32, /*!< T9_L1 : Device 1: Table 9 Location 1 */ 126 MEC_I3C_DCT_DEV1_T9_L2 = 33, /*!< T9_L2 : Device 1: Table 9 Location 2 */ 127 MEC_I3C_DCT_DEV1_T9_L3 = 34, /*!< T9_L3 : Device 1: Table 9 Location 3 */ 128 MEC_I3C_DCT_DEV1_T9_L4 = 35, /*!< T9_L4 : Device 1: Table 9 Location 4 */ 129 MEC_I3C_DCT_DEV1_T10_L1 = 36, /*!< T10_L1 : Device 1: Table 10 Location 1 */ 130 MEC_I3C_DCT_DEV1_T10_L2 = 37, /*!< T10_L2 : Device 1: Table 10 Location 2 */ 131 MEC_I3C_DCT_DEV1_T10_L3 = 38, /*!< T10_L3 : Device 1: Table 10 Location 3 */ 132 MEC_I3C_DCT_DEV1_T10_L4 = 39, /*!< T10_L4 : Device 1: Table 10 Location 4 */ 133 MEC_I3C_DCT_DEV1_T11_L1 = 40, /*!< T11_L1 : Device 1: Table 11 Location 1 */ 134 MEC_I3C_DCT_DEV1_T11_L2 = 41, /*!< T11_L2 : Device 1: Table 11 Location 2 */ 135 MEC_I3C_DCT_DEV1_T11_L3 = 42, /*!< T11_L3 : Device 1: Table 11 Location 3 */ 136 MEC_I3C_DCT_DEV1_T11_L4 = 43, /*!< T11_L4 : Device 1: Table 11 Location 4 */ 137 } MEC_I3C_DCT_DEV1_Enum; 138 139 /* ======================================================== DAT_LOC ======================================================== */ 140 /* ================================================= MEC_I3C_HOST DAT_LOC ================================================= */ 141 typedef enum { /*!< MEC_I3C_HOST_DAT_LOC */ 142 MEC_I3C_DAT_DEV1_T1_L1 = 0, /*!< T1_L1 : Device 1: Table 1 Location 1 */ 143 MEC_I3C_DAT_DEV1_T2_L1 = 1, /*!< T2_L1 : Device 1: Table 1 Location 2 */ 144 MEC_I3C_DAT_DEV1_T3_L1 = 2, /*!< T3_L1 : Device 1: Table 1 Location 3 */ 145 MEC_I3C_DAT_DEV1_T4_L1 = 3, /*!< T4_L1 : Device 1: Table 1 Location 4 */ 146 MEC_I3C_DAT_DEV1_T5_L1 = 4, /*!< T5_L1 : Device 1: Table 2 Location 1 */ 147 MEC_I3C_DAT_DEV1_T6_L1 = 5, /*!< T6_L1 : Device 1: Table 2 Location 2 */ 148 MEC_I3C_DAT_DEV1_T7_L1 = 6, /*!< T7_L1 : Device 1: Table 2 Location 3 */ 149 MEC_I3C_DAT_DEV1_T8_L1 = 7, /*!< T8_L1 : Device 1: Table 2 Location 4 */ 150 MEC_I3C_DAT_DEV1_T9_L1 = 8, /*!< T9_L1 : Device 1: Table 3 Location 1 */ 151 MEC_I3C_DAT_DEV1_T10_L1 = 8, /*!< T10_L1 : Device 1: Table 3 Location 2 */ 152 MEC_I3C_DAT_DEV1_T11_L1 = 10, /*!< T11_L1 : Device 1: Table 3 Location 3 */ 153 } MEC_I3C_DAT_DEV1_Enum; 154 155 /** @} */ /* End of group EnumValue_peripherals */ 156 157 #endif /* _MEC5_I3C_HOST_V2_H */ 158