1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_ECIA_V1_5_H 7 #define _MEC5_ECIA_V1_5_H 8 9 /** @addtogroup Device_Peripheral_clusters 10 * @{ 11 */ 12 13 /** 14 * @brief MEC_GIRQS [GIRQ] (ECIA GIRQ) 15 */ 16 typedef struct mec_girqs_regs { 17 __IOM uint32_t SOURCE; /*!< (@ 0x00000000) Individual latched interrupt source bits(R/W1C) */ 18 __IOM uint32_t EN_SET; /*!< (@ 0x00000004) Individual interrupt enable set bits(R/W1S) */ 19 __IM uint32_t RESULT; /*!< (@ 0x00000008) Individual interrupt result(RO) = Source AND 20 EN_SET */ 21 __IOM uint32_t EN_CLR; /*!< (@ 0x0000000C) Individual interrupt enable clear bits(R/W1C) */ 22 __IM uint32_t RSVD; /*!< (@ 0x00000010) Not implemented */ 23 } MEC_GIRQS_Type; /*!< Size = 20 (0x14) */ 24 25 /** @} */ /* End of group Device_Peripheral_clusters */ 26 27 /** @addtogroup Device_Peripheral_peripherals 28 * @{ 29 */ 30 31 /** 32 * @brief EC Interrupt Aggregator(ECIA) (MEC_ECIA0) 33 */ 34 35 typedef struct mec_ecia_regs { /*!< (@ 0x4000E000) MEC_ECIA0 Structure */ 36 __IOM MEC_GIRQS_Type GIRQ[19]; /*!< (@ 0x00000000) ECIA GIRQ */ 37 __IM uint32_t RESERVED[33]; 38 __IOM uint32_t BLK_EN_SET; /*!< (@ 0x00000200) Bit map to enable aggregated GIRQ outputs */ 39 __IOM uint32_t BLK_EN_CLR; /*!< (@ 0x00000204) Bit map to disable aggregated GIRQ outputs */ 40 __IM uint32_t BLK_ACTIVE; /*!< (@ 0x00000208) Read only bit map of active aggregated GIRQ outputs */ 41 } MEC_ECIA_Type; /*!< Size = 524 (0x20c) */ 42 /** @} */ /* End of group Device_Peripheral_peripherals */ 43 44 /** @addtogroup EnumValue_clusters 45 * @{ 46 */ 47 /* ========================================================= GIRQ ========================================================= */ 48 typedef enum { /*!< MEC_ECIA0_GIRQ */ 49 MEC_GIRQ_IDX_GIRQ8 = 0, /*!< GIRQ8 : GIRQ08 array index */ 50 MEC_GIRQ_IDX_GIRQ9 = 1, /*!< GIRQ9 : GIRQ09 array index */ 51 MEC_GIRQ_IDX_GIRQ10 = 2, /*!< GIRQ10 : GIRQ10 array index */ 52 MEC_GIRQ_IDX_GIRQ11 = 3, /*!< GIRQ11 : GIRQ11 array index */ 53 MEC_GIRQ_IDX_GIRQ12 = 4, /*!< GIRQ12 : GIRQ12 array index */ 54 MEC_GIRQ_IDX_GIRQ13 = 5, /*!< GIRQ13 : GIRQ13 array index */ 55 MEC_GIRQ_IDX_GIRQ14 = 6, /*!< GIRQ14 : GIRQ14 array index */ 56 MEC_GIRQ_IDX_GIRQ15 = 7, /*!< GIRQ15 : GIRQ15 array index */ 57 MEC_GIRQ_IDX_GIRQ16 = 8, /*!< GIRQ16 : GIRQ16 array index */ 58 MEC_GIRQ_IDX_GIRQ17 = 9, /*!< GIRQ17 : GIRQ17 array index */ 59 MEC_GIRQ_IDX_GIRQ18 = 10, /*!< GIRQ18 : GIRQ18 array index */ 60 MEC_GIRQ_IDX_GIRQ19 = 11, /*!< GIRQ19 : GIRQ19 array index */ 61 MEC_GIRQ_IDX_GIRQ20 = 12, /*!< GIRQ20 : GIRQ20 array index */ 62 MEC_GIRQ_IDX_GIRQ21 = 13, /*!< GIRQ21 : GIRQ21 array index */ 63 MEC_GIRQ_IDX_GIRQ22 = 14, /*!< GIRQ22 : GIRQ22 array index */ 64 MEC_GIRQ_IDX_GIRQ23 = 15, /*!< GIRQ23 : GIRQ23 array index */ 65 MEC_GIRQ_IDX_GIRQ24 = 16, /*!< GIRQ24 : GIRQ24 array index */ 66 MEC_GIRQ_IDX_GIRQ25 = 17, /*!< GIRQ25 : GIRQ25 array index */ 67 MEC_GIRQ_IDX_GIRQ26 = 18, /*!< GIRQ26 : GIRQ26 array index */ 68 } MEC_GIRQ_IDX_Enum; 69 70 /* GIRQ8 - GIRQ26 numerical value */ 71 typedef enum { /*!< MEC_GIRQ */ 72 MEC_GIRQ08_ID = 8, /*!< GIRQ8 ID data sheet number */ 73 MEC_GIRQ09_ID = 9, /*!< GIRQ9 */ 74 MEC_GIRQ10_ID = 10, /*!< GIRQ10 */ 75 MEC_GIRQ11_ID = 11, /*!< GIRQ11 */ 76 MEC_GIRQ12_ID = 12, /*!< GIRQ12 */ 77 MEC_GIRQ13_ID = 13, /*!< GIRQ13 */ 78 MEC_GIRQ14_ID = 14, /*!< GIRQ14 */ 79 MEC_GIRQ15_ID = 15, /*!< GIRQ15 */ 80 MEC_GIRQ16_ID = 16, /*!< GIRQ16 */ 81 MEC_GIRQ17_ID = 17, /*!< GIRQ17 */ 82 MEC_GIRQ18_ID = 18, /*!< GIRQ18 */ 83 MEC_GIRQ19_ID = 19, /*!< GIRQ19 */ 84 MEC_GIRQ20_ID = 20, /*!< GIRQ20 */ 85 MEC_GIRQ21_ID = 21, /*!< GIRQ21 */ 86 MEC_GIRQ22_ID = 22, /*!< GIRQ22 */ 87 MEC_GIRQ23_ID = 23, /*!< GIRQ23 */ 88 MEC_GIRQ24_ID = 24, /*!< GIRQ24 */ 89 MEC_GIRQ25_ID = 25, /*!< GIRQ25 */ 90 MEC_GIRQ26_ID = 26, /*!< GIRQ26 */ 91 } MEC_GIRQ_Enum; 92 93 /** @} */ /* End of group EnumValue_clusters */ 94 95 #endif /* _MEC5_ECIA_V1_5_H */ 96
