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Searched refs:MEC_GENMASK (Results 1 – 5 of 5) sorted by relevance

/hal_microchip-latest/mec5/drivers/
Dmec_i3c_pvt.c907 ((sda_tout_val & (uint32_t)MEC_GENMASK(9 , 0)) << SEC_HOST_CFG_STUCK_SDA_TOUT_BITPOS); in _i3c_sec_host_stuck_sda_scl_config()
909 ((scl_tout_val & (uint32_t)MEC_GENMASK(9 , 0)) << SEC_HOST_CFG_STUCK_SCL_TOUT_BITPOS); in _i3c_sec_host_stuck_sda_scl_config()
1301 …return (uint8_t)((FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(3, 0)) >> Q_CAP_TX_FI… in _i3c_tx_fifo_depth_get()
1310 …return (uint8_t)((FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(7, 4)) >> Q_CAP_RX_FI… in _i3c_rx_fifo_depth_get()
1319 …return (uint8_t)(FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(11, 8)) >> Q_CAP_CMD_F… in _i3c_cmd_fifo_depth_get()
1328 …return (uint8_t)(FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(15, 12)) >> Q_CAP_RESP… in _i3c_resp_fifo_depth_get()
1337 …return (uint8_t)(FIFO_DEPTH_MIN_DWORD << ((regs->QUE_SIZE_CAP & MEC_GENMASK(19, 16)) >> Q_CAP_IBI_… in _i3c_ibi_fifo_depth_get()
1374 return (uint8_t)((regs->DEV_ADDR & MEC_GENMASK(22, 16)) >> DEVICE_ADDR_DYNAMIC_ADDR_BITPOS); in _i3c_tgt_dyn_addr_get()
1382 regs->MAX_RW_LEN = (regs->MAX_RW_LEN & ~(MEC_GENMASK(31, 16))) | (mrl << MRL_BITPOS); in _i3c_tgt_mrl_set()
1390 regs->MAX_RW_LEN = (regs->MAX_RW_LEN & ~(MEC_GENMASK(15, 0))) | (mwl << MWL_BITPOS); in _i3c_tgt_mwl_set()
Dmec_defs.h139 #ifndef MEC_GENMASK
140 #define MEC_GENMASK(h, l) \ macro
Dmec_btimer_api.h34 #define MEC5_BTIMER_INST_MASK MEC_GENMASK(MEC5_BASIC_TIMER_INSTANCES - 1, 0)
Dmec_ps2.c17 #define MEC_PS2_CTRL_BITMAP MEC_GENMASK(MEC5_PS2_INSTANCES, 0)
Dmec_i3c_pvt.h501 #define MXDS_MAX_RD_TURN_MASK(x) (x & MEC_GENMASK(23, 0))