1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_ESPI_PC_H 7 #define _MEC_ESPI_PC_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 13 /* Interfaces to any C modules */ 14 #ifdef __cplusplus 15 extern "C" 16 { 17 #endif 18 19 /* forward declarations */ 20 struct mec_espi_io_regs; 21 struct mec_espi_mem_regs; 22 struct mec_espi_vw_regs; 23 24 /* ---- eSPI Peripheral Channel ---- */ 25 26 /* eSPI Host Logical Device numbers */ 27 enum mec_espi_ldn { 28 MEC_ESPI_LDN_MBOX = 0, 29 MEC_ESPI_LDN_KBC, 30 MEC_ESPI_LDN_ACPI_EC0, 31 MEC_ESPI_LDN_ACPI_EC1, 32 MEC_ESPI_LDN_ACPI_EC2, 33 MEC_ESPI_LDN_ACPI_EC3, 34 MEC_ESPI_LDN_ACPI_EC4, 35 MEC_ESPI_LDN_ACPI_PM1, 36 MEC_ESPI_LDN_KB_PORT92, 37 MEC_ESPI_LDN_UART0, 38 MEC_ESPI_LDN_UART1, 39 MEC_ESPI_LDN_UART2, 40 MEC_ESPI_LDN_UART3, 41 MEC_ESPI_LDN_IOC, 42 MEC_ESPI_LDN_IOMC, 43 MEC_ESPI_LDN_GLUE, 44 MEC_ESPI_LDN_EMI0, 45 MEC_ESPI_LDN_EMI1, 46 MEC_ESPI_LDN_EMI2, 47 MEC_ESPI_LDN_RTC = 20, 48 MEC_ESPI_LDN_PP0, 49 MEC_ESPI_LDN_BDBG0 = 32, 50 MEC_ESPI_LDN_BDBG0_ALIAS, 51 MEC_ESPI_LDN_TB32 = 47, 52 MEC_ESPI_LDN_EC = 66, 53 MEC_ESPI_LDN_MAX, 54 }; 55 56 /* Logical devices using Serial IRQ implement one SIRQ except: 57 * Mailbox, KBC, and EMI implement two Serial IRQs each. 58 * Use these enumerated types for the instance parameter of 59 * sirq get/set. 60 */ 61 enum mec_espi_ld_sirq_mbox { 62 MEC_ESPI_LD_MBOX_HOST_SIRQ = 0, 63 MEC_ESPI_LD_MBOX_HOST_SMI, 64 }; 65 66 enum mec_espi_ld_sirq_kbc { 67 MEC_ESPI_LD_KBC_KIRQ = 0, 68 MEC_ESPI_LD_KBC_MIRQ, 69 }; 70 71 enum mec_espi_ld_sirq_emi { 72 MEC_ESPI_LD_EMI_HOST_EVENT = 0, 73 MEC_ESPI_LD_EMI_E2H, 74 }; 75 76 /* ---- Peripheral channel (PC) ---- */ 77 #define MEC_ESPI_PC_BM_EN_CHG 0x1 78 #define MEC_ESPI_PC_BM_EN_STATE_HI 0x2 79 #define MEC_ESPI_PC_EN_CHG 0x1 80 #define MEC_ESPI_PC_EN_STATE_HI 0x2 81 82 enum mec_espi_pc_intr_pos { 83 MEC_ESPI_PC_INTR_CHEN_CHG_POS = 0, 84 MEC_ESPI_PC_INTR_BMEN_CHG_POS, 85 MEC_ESPI_PC_INTR_BERR_POS, 86 MEC_ESPI_PC_INTR_POS_MAX 87 }; 88 89 enum mec_espi_pc_sts_pos { 90 MEC_ESPI_PC_ISTS_CHEN_STATE_POS = 0, 91 MEC_ESPI_PC_ISTS_CHEN_CHG_POS, 92 MEC_ESPI_PC_ISTS_BMEN_STATE_POS, 93 MEC_ESPI_PC_ISTS_BMEN_CHG_POS, 94 MEC_ESPI_PC_ISTS_BERR_POS, 95 MEC_ESPI_PC_ISTS_POS_MAX, 96 }; 97 98 struct mec_espi_pc_last_cycle { 99 uint32_t host_pc_addr_lsw; 100 uint32_t host_pc_addr_msw; 101 uint16_t len; 102 uint8_t cycle_type; 103 uint8_t tag; 104 }; 105 106 void mec_hal_espi_pc_ready_set(struct mec_espi_io_regs *iobase); 107 /* return 1 is ready else 0 */ 108 int mec_hal_espi_pc_is_ready(struct mec_espi_io_regs *iobase); 109 110 /* return bits indicating eSPI peripheral channel enable has changed and the 111 * channel enable's current state. 112 */ 113 uint32_t mec_hal_espi_pc_en_status(struct mec_espi_io_regs *iobase); 114 uint32_t mec_hal_espi_pc_bm_status(struct mec_espi_io_regs *iobase); 115 116 /* return status bit map interpreted using mec_espi_pc_status_pos bit positions */ 117 uint32_t mec_hal_espi_pc_status(struct mec_espi_io_regs *iobase); 118 void mec_hal_espi_pc_status_clr(struct mec_espi_io_regs *iobase, uint32_t bitmap); 119 void mec_hal_espi_pc_status_clr_all(struct mec_espi_io_regs *iobase); 120 121 void mec_hal_espi_pc_intr_en(struct mec_espi_io_regs *iobase, uint32_t bitmap); 122 void mec_hal_espi_pc_intr_dis(struct mec_espi_io_regs *iobase, uint32_t bitmap); 123 124 /* Get 64-bit address sent by Host which caused an error */ 125 uint64_t mec_hal_espi_pc_error_addr(struct mec_espi_io_regs *iobase); 126 127 void mec_hal_espi_pc_last_cycle(struct mec_espi_io_regs *iobase, 128 struct mec_espi_pc_last_cycle *lc); 129 130 void mec_hal_espi_pc_girq_ctrl(uint8_t enable); 131 void mec_hal_espi_pc_girq_status_clr(void); 132 uint32_t mec_hal_espi_pc_girq_status(void); 133 uint32_t mec_hal_espi_pc_girq_result(void); 134 135 /* PC LTR */ 136 enum mec_espi_pc_ltr_intr_pos { 137 MEC_ESPI_PC_LTR_INTR_TX_DONE_POS = 0, 138 MEC_ESPI_PC_LTR_INTR_START_OVR_POS = 3, 139 MEC_ESPI_PC_LTR_INTR_DIS_BY_HOST_POS, 140 MEC_ESPI_PC_LTR_INTR_TX_BUSY_POS = 8 141 }; 142 143 uint32_t mec_hal_espi_pc_ltr_status(struct mec_espi_io_regs *iobase); 144 void mec_hal_espi_pc_ltr_intr_en(struct mec_espi_io_regs *iobase, uint32_t enmask); 145 void mec_hal_espi_pc_ltr_ctrl(struct mec_espi_io_regs *iobase, uint8_t tag, uint8_t start); 146 void mec_hal_espi_pc_ltr_msg(struct mec_espi_io_regs *iobase, uint16_t nunits, uint8_t time_unit, 147 uint8_t rsvd_bits, uint8_t max_lat); 148 void mec_hal_espi_pc_ltr_girq_ctrl(uint8_t enable); 149 void mec_hal_espi_pc_ltr_girq_status_clr(void); 150 uint32_t mec_hal_espi_pc_ltr_girq_status(void); 151 uint32_t mec_hal_espi_pc_ltr_girq_result(void); 152 153 /* ---- Peripheral Channel Logical Device I/O and Memory BARs ---- */ 154 155 /* NOTE: refer to chip documentation. Most I/O and memory BARs are held 156 * in reset by the SoC's VCC Power Good signal and the state of the nPLTRST signal. 157 * nPLTRST can be a virtual wire or an external signal (legacy systems). 158 */ 159 int mec_hal_espi_iobar_cfg(struct mec_espi_io_regs *base, uint8_t ldn, uint16_t io_base, 160 uint8_t enable); 161 int mec_hal_espi_iobar_enable(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t enable); 162 int mec_hal_espi_iobar_is_enabled(struct mec_espi_io_regs *base, uint8_t ldn); 163 uint32_t mec_hal_espi_iobar_mask(struct mec_espi_io_regs *base, uint8_t ldn); 164 int mec_hal_espi_iobar_mask_set(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t mask); 165 166 /* Inhibit both I/O and Memory BAR for a logical device or a bit map of LDNs */ 167 int mec_hal_espi_bar_inhibit(struct mec_espi_io_regs *base, uint8_t ldn, uint8_t inhibit); 168 int mec_hal_espi_bar_inhibit_msk(struct mec_espi_io_regs *base, uint8_t inhibit, 169 uint32_t msklo, uint32_t mskhi); 170 171 int mec_hal_espi_mbar_enable(struct mec_espi_mem_regs *base, uint8_t ldn, uint8_t enable); 172 int mec_hal_espi_mbar_is_enabled(struct mec_espi_mem_regs *base, uint8_t ldn); 173 int mec_hal_espi_mbar_cfg(struct mec_espi_mem_regs *base, uint8_t ldn, uint32_t mem_base, 174 uint8_t enable); 175 int mec_hal_espi_mbar_extended_addr_set(struct mec_espi_mem_regs *base, uint32_t extended_addr); 176 177 enum espi_mec5_sram_bar_id { 178 MEC_ESPI_SRAM_BAR_0 = 0, 179 MEC_ESPI_SRAM_BAR_1, 180 MEC_ESPI_SRAM_BAR_MAX, 181 }; 182 183 enum espi_mec5_sram_host_access { 184 MEC_ESPI_SRAM_HOST_ACCESS_NONE = 0, 185 MEC_ESPI_SRAM_HOST_ACCESS_RO, 186 MEC_ESPI_SRAM_HOST_ACCESS_WO, 187 MEC_ESPI_SRAM_HOST_ACCESS_RW, 188 }; 189 190 enum espi_mec5_sram_bar_size { 191 MEC_ESPI_SRAM_BAR_SIZE_1B = 0, 192 MEC_ESPI_SRAM_BAR_SIZE_2B, 193 MEC_ESPI_SRAM_BAR_SIZE_4B, 194 MEC_ESPI_SRAM_BAR_SIZE_8B, 195 MEC_ESPI_SRAM_BAR_SIZE_16B, 196 MEC_ESPI_SRAM_BAR_SIZE_32B, 197 MEC_ESPI_SRAM_BAR_SIZE_64B, 198 MEC_ESPI_SRAM_BAR_SIZE_128B, 199 MEC_ESPI_SRAM_BAR_SIZE_256B, 200 MEC_ESPI_SRAM_BAR_SIZE_512B, 201 MEC_ESPI_SRAM_BAR_SIZE_1KB, 202 MEC_ESPI_SRAM_BAR_SIZE_2KB, 203 MEC_ESPI_SRAM_BAR_SIZE_4KB, 204 MEC_ESPI_SRAM_BAR_SIZE_8KB, 205 MEC_ESPI_SRAM_BAR_SIZE_16KB, 206 MEC_ESPI_SRAM_BAR_SIZE_32KB, 207 MEC_ESPI_SRAM_BAR_SIZE_MAX, 208 }; 209 210 struct espi_mec5_sram_bar_cfg { 211 uint32_t haddr; 212 uint32_t maddr; 213 uint8_t size; 214 uint8_t access; 215 }; 216 217 int mec_hal_espi_sram_bar_cfg(struct mec_espi_mem_regs *base, 218 const struct espi_mec5_sram_bar_cfg *barcfg, 219 uint8_t sram_bar_id, uint8_t enable); 220 int mec_hal_espi_sram_bar_extended_addr_set(struct mec_espi_mem_regs *base, 221 uint32_t extended_addr); 222 223 /* Return the number of Serial IRQ's a logical device implements */ 224 uint8_t mec_hal_espi_ld_sirq_num(struct mec_espi_io_regs *iobase, uint8_t ldn); 225 226 /* Get/set Serial IRQ slot(interrupt) number for a logical device. 227 * Some logical devices implement more than one SIRQ selected by ldn_sirq_id (zero based) 228 */ 229 uint8_t mec_hal_espi_ld_sirq_get(struct mec_espi_io_regs *iobase, uint8_t ldn, 230 uint8_t ldn_sirq_id); 231 void mec_hal_espi_ld_sirq_set(struct mec_espi_io_regs *iobase, uint8_t ldn, 232 uint8_t ldn_sirq_id, uint8_t slot); 233 234 /* Generate EC_IRQ Serial IRQ to the Host using the Serial IRQ slot 235 * number previously programmed by mec_espi_ld_sirq_set(). 236 */ 237 int mec_hal_espi_gen_ec_sirq(struct mec_espi_io_regs *iobase); 238 239 #ifdef __cplusplus 240 } 241 #endif 242 243 #endif /* #ifndef _MEC_ESPI_PC_H */ 244
