1 /* 2 * Copyright 2024 Microchip Technology Inc. and its subsidiaries. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC_ESPI_FC_H 7 #define _MEC_ESPI_FC_H 8 9 #include <stdbool.h> 10 #include <stddef.h> 11 #include <stdint.h> 12 13 /* Interfaces to any C modules */ 14 #ifdef __cplusplus 15 extern "C" 16 { 17 #endif 18 19 /* forward declarations */ 20 struct mec_espi_io_regs; 21 struct mec_espi_mem_regs; 22 struct mec_espi_vw_regs; 23 24 /* ---- Flash Channel (FC) ---- */ 25 enum mec_espi_fc_op { 26 MEC_ESPI_FC_OP_READ = 0, 27 MEC_ESPI_FC_OP_WRITE, 28 MEC_ESPI_FC_OP_ERASE_S, 29 MEC_ESPI_FC_OP_ERASE_L, 30 MEC_ESPI_FC_OP_MAX, 31 }; 32 33 enum mec_espi_fc_intr { 34 MEC_ESPI_FC_INTR_CHEN_POS = 0, 35 MEC_ESPI_FC_INTR_CHEN_CHG_POS, 36 MEC_ESPI_FC_INTR_DONE_POS, 37 MEC_ESPI_FC_INTR_DIS_BY_HOST_POS, 38 MEC_ESPI_FC_INTR_EC_BERR_POS, 39 MEC_ESPI_FC_INTR_ABORT_BY_EC_POS, 40 MEC_ESPI_FC_INTR_DATA_OVRUN_POS, 41 MEC_ESPI_FC_INTR_INCOMPL_POS, 42 MEC_ESPI_FC_INTR_FAIL_POS, 43 MEC_ESPI_FC_INTR_START_OVFL_POS, 44 MEC_ESPI_FC_INTR_BAD_REQ_POS = 11, 45 }; 46 47 struct mec_espi_fc_xfr { 48 uint32_t buf_addr; 49 uint32_t flash_addr; 50 uint32_t byte_len; 51 uint8_t operation; 52 uint8_t tag; 53 }; 54 55 #define MEC_ESPI_FC_XFR_FLAG_START_IEN_POS 0 56 57 void mec_hal_espi_fc_ready_set(struct mec_espi_io_regs *iobase); 58 int mec_hal_espi_fc_is_ready(struct mec_espi_io_regs *iobase); 59 60 /* return bits indicating channel enable state and enable change status */ 61 uint32_t mec_hal_espi_fc_en_status(struct mec_espi_io_regs *iobase); 62 63 void mec_hal_espi_fc_girq_ctrl(uint8_t enable); 64 void mec_hal_espi_fc_girq_status_clr(void); 65 uint32_t mec_hal_espi_fc_girq_status(void); 66 uint32_t mec_hal_espi_fc_girq_result(void); 67 68 uint32_t mec_hal_espi_fc_max_read_req_sz(struct mec_espi_io_regs *iobase); 69 uint32_t mec_hal_espi_fc_max_pld_sz(struct mec_espi_io_regs *iobase); 70 71 int mec_hal_espi_fc_is_busy(struct mec_espi_io_regs *iobase); 72 void mec_hal_espi_fc_op_start(struct mec_espi_io_regs *iobase, uint32_t flags); 73 void mec_hal_espi_fc_op_abort(struct mec_espi_io_regs *iobase); 74 void mec_hal_espi_fc_intr_ctrl(struct mec_espi_io_regs *iobase, uint32_t msk, uint8_t en); 75 uint32_t mec_hal_espi_fc_status(struct mec_espi_io_regs *iobase); 76 void mec_hal_espi_fc_status_clr(struct mec_espi_io_regs *iobase, uint32_t msk); 77 int mec_hal_espi_fc_is_error(uint32_t fc_status); 78 79 /* Return the two allowed erase block sizes in b[15:0] and b[31:16] in units 80 * of KB. If only one erase size allowed both fields will be identical. 81 * A return value of 0 indicates the flash channel has not been properly 82 * configured during eSPI link negoitation. 83 */ 84 uint32_t mec_hal_espi_fc_get_erase_sz(struct mec_espi_io_regs *iobase); 85 int mec_hal_espi_fc_check_erase_sz(struct mec_espi_io_regs *iobase, uint32_t ersz_bytes); 86 87 int mec_hal_espi_fc_xfr_start(struct mec_espi_io_regs *iobase, struct mec_espi_fc_xfr *pxfr, 88 uint32_t flags); 89 90 #ifdef __cplusplus 91 } 92 #endif 93 94 #endif /* #ifndef _MEC_ESPI_FC_H */ 95
