1 /*
2  * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC_DMAC_H
7 #define _MEC_DMAC_H
8 
9 #include <stdbool.h>
10 #include <stddef.h>
11 #include <stdint.h>
12 
13 #include "mec_retval.h"
14 
15 /* Interfaces to any C modules */
16 #ifdef __cplusplus
17 extern "C"
18 {
19 #endif
20 
21 #define MEC_DMAC_ALL_CHAN_MASK 0xffffu
22 
23 enum mec_dmac_channel {
24     MEC_DMAC_CHAN_0 = 0,
25     MEC_DMAC_CHAN_1,
26     MEC_DMAC_CHAN_2,
27     MEC_DMAC_CHAN_3,
28     MEC_DMAC_CHAN_4,
29     MEC_DMAC_CHAN_5,
30     MEC_DMAC_CHAN_6,
31     MEC_DMAC_CHAN_7,
32     MEC_DMAC_CHAN_8,
33     MEC_DMAC_CHAN_9,
34     MEC_DMAC_CHAN_10,
35     MEC_DMAC_CHAN_11,
36     MEC_DMAC_CHAN_12,
37     MEC_DMAC_CHAN_13,
38     MEC_DMAC_CHAN_14,
39     MEC_DMAC_CHAN_15,
40     MEC_DMAC_CHAN_MAX,
41 };
42 
43 enum mec_dmac_dir {
44     MEC_DMAC_DIR_DEV_TO_MEM = 0,
45     MEC_DMAC_DIR_MEM_TO_DEV,
46     MEC_DMAC_DIR_MAX,
47 };
48 
49 enum mec_dmac_hwfc_dev_id {
50     MEC_DMAC_DEV_ID_SMB_0_T2C = 0,
51     MEC_DMAC_DEV_ID_SMB_0_C2T,
52     MEC_DMAC_DEV_ID_SMB_1_T2C,
53     MEC_DMAC_DEV_ID_SMB_1_C2T,
54     MEC_DMAC_DEV_ID_SMB_2_T2C,
55     MEC_DMAC_DEV_ID_SMB_2_C2T,
56     MEC_DMAC_DEV_ID_SMB_3_T2C,
57     MEC_DMAC_DEV_ID_SMB_3_C2T,
58     MEC_DMAC_DEV_ID_SMB_4_T2C,
59     MEC_DMAC_DEV_ID_SMB_4_C2T,
60     MEC_DMAC_DEV_ID_QSPI_0_TX,
61     MEC_DMAC_DEV_ID_QSPI_0_RX,
62     MEC_DMAC_DEV_ID_GPSPI_0_TX,
63     MEC_DMAC_DEV_ID_GPSPI_0_RX,
64     MEC_DMAC_DEV_ID_GPSPI_1_TX,
65     MEC_DMAC_DEV_ID_GPSPI_1_RX,
66     MEC_DMAC_DEV_ID_NONE, /* software flow control */
67     MEC_DMAC_DEV_ID_MAX,
68 };
69 
70 enum mec_dmac_unit_size {
71     MEC_DMAC_UNIT_SIZE_1 = 0,
72     MEC_DMAC_UNIT_SIZE_2 = 1,
73     MEC_DMAC_UNIT_SIZE_4 = 2,
74     MEC_DMAC_UNIT_SIZE_MAX,
75 };
76 
77 enum mec_dma_chan_status_pos {
78     MEC_DMA_CHAN_STS_BUS_ERR_POS = 0,
79     MEC_DMA_CHAN_STS_HFC_OVF_POS,
80     MEC_DMA_CHAN_STS_DONE_POS,
81     MEC_DMA_CHAN_STS_HFC_TERM_POS,
82     MEC_DMA_CHAN_STS_MAX_POS,
83 };
84 
85 #define MEC_DMA_CFG_FLAG_INCR_SRC_ADDR 0x01
86 #define MEC_DMA_CFG_FLAG_INCR_DST_ADDR 0x02
87 
88 struct mec_dma_cfg {
89     uintptr_t src_addr;
90     uintptr_t dst_addr;
91     size_t nbytes;
92     uint8_t flags;
93     enum mec_dmac_unit_size unitsz;
94     enum mec_dmac_dir dir;
95     enum mec_dmac_hwfc_dev_id hwfc_dev;
96 };
97 
98 /* forward declaration */
99 struct mec_dmac_regs;
100 
101 /* ---- channel oriented API ----
102  * MEC5 family has one instance of the central DMA controller.
103  * The number of channels varies by part.
104  * No need for register base address parameter.
105  */
106 
107 /* ---- Reset and Enable Controller ---- */
108 
109 int mec_hal_dmac_reset(void);
110 
111 int mec_hal_dmac_enable(uint8_t enable);
112 bool mec_hal_dmac_is_enabled(void);
113 
114 int mec_hal_dmac_init(uint32_t chan_mask);
115 
116 uint32_t mec_hal_dmac_girq_result(void);
117 void mec_hal_dmac_girq_aggr(uint8_t enable);
118 
119 /* ---- channel API ---- */
120 int mec_hal_dma_chan_init(enum mec_dmac_channel);
121 
122 int mec_hal_dma_chan_intr_status(enum mec_dmac_channel chan, uint32_t *status);
123 int mec_hal_dma_chan_intr_status_clr(enum mec_dmac_channel chan);
124 int mec_hal_dma_chan_intr_en(enum mec_dmac_channel chan, uint8_t ien);
125 
126 int mec_hal_dma_chan_ia_status_clr(enum mec_dmac_channel channel);
127 int mec_hal_dma_chan_ia_status_clr_mask(uint32_t chanmsk);
128 int mec_hal_dma_chan_ia_enable(enum mec_dmac_channel channel);
129 int mec_hal_dma_chan_ia_enable_mask(uint32_t chan_mask);
130 int mec_hal_dma_chan_ia_disable_mask(uint32_t chan_mask);
131 int mec_hal_dma_chan_ia_disable(enum mec_dmac_channel channel);
132 
133 bool mec_hal_dma_chan_is_busy(enum mec_dmac_channel chan);
134 
135 int mec_hal_dma_chan_start(enum mec_dmac_channel chan);
136 
137 int mec_hal_dma_chan_halt(enum mec_dmac_channel chan);
138 
139 int mec_hal_dma_chan_stop(enum mec_dmac_channel chan);
140 
141 int mec_hal_dma_chan_hwfc_set(enum mec_dmac_channel chan, enum mec_dmac_hwfc_dev_id hwfc_dev,
142                               uintptr_t dev_addr);
143 
144 int mec_hal_dma_chan_dir_set(enum mec_dmac_channel chan, enum mec_dmac_dir dir);
145 int mec_hal_dma_chan_dir_get(enum mec_dmac_channel chan, enum mec_dmac_dir *dir);
146 
147 int mec_hal_dma_chan_mem_set(enum mec_dmac_channel chan, uintptr_t maddr, size_t nbytes);
148 
149 int mec_hal_dma_chan_mem_units_set(enum mec_dmac_channel chan, enum mec_dmac_unit_size unitsz);
150 
151 int mec_hal_dma_chan_rem_bytes(enum mec_dmac_channel chan, uint32_t *remsz);
152 
153 int mec_hal_dma_chan_reload(enum mec_dmac_channel chan, uintptr_t src, uintptr_t dest,
154                             size_t nbytes);
155 
156 int mec_hal_dma_chan_cfg(enum mec_dmac_channel chan, struct mec_dma_cfg *cfg);
157 
158 int mec_hal_dma_chan_cfg_get(enum mec_dmac_channel chan, struct mec_dma_cfg *cfg);
159 
160 #ifdef __cplusplus
161 }
162 #endif
163 
164 #endif /* #ifndef _MEC_DMAC_H */
165