1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_CCT_V1_1_H 7 #define _MEC5_CCT_V1_1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief Capture and Compare Timer (MEC_CCT) 15 */ 16 17 typedef struct mec_cct_regs { /*!< (@ 0x40001000) MEC_CCT Structure */ 18 __IOM uint32_t TCTRL; /*!< (@ 0x00000000) CCT capture and compare timer control */ 19 __IOM uint32_t CAP_CTRL0; /*!< (@ 0x00000004) CCT capture 0 control */ 20 __IOM uint32_t CAP_CTRL1; /*!< (@ 0x00000008) CCT capture 1 control */ 21 __IOM uint32_t FR_COUNT; /*!< (@ 0x0000000C) CCT free run counter */ 22 __IM uint32_t CAP0_CNT; /*!< (@ 0x00000010) CCT capture 0 count(RO) */ 23 __IM uint32_t CAP1_CNT; /*!< (@ 0x00000014) CCT capture 1 count(RO) */ 24 __IM uint32_t CAP2_CNT; /*!< (@ 0x00000018) CCT capture 2 count(RO) */ 25 __IM uint32_t CAP3_CNT; /*!< (@ 0x0000001C) CCT capture 3 count(RO) */ 26 __IM uint32_t CAP4_CNT; /*!< (@ 0x00000020) CCT capture 4 count(RO) */ 27 __IM uint32_t CAP5_CNT; /*!< (@ 0x00000024) CCT capture 5 count(RO) */ 28 __IOM uint32_t CMP0_CNT; /*!< (@ 0x00000028) CCT compare 0 match count */ 29 __IOM uint32_t CMP1_CNT; /*!< (@ 0x0000002C) CCT compare 1 match count */ 30 __IOM uint32_t MUX_SEL; /*!< (@ 0x00000030) CCT MUX Select */ 31 } MEC_CCT_Type; /*!< Size = 52 (0x34) */ 32 33 /** @} */ /* End of group Device_Peripheral_peripherals */ 34 35 /** @addtogroup PosMask_peripherals 36 * @{ 37 */ 38 /* ========================================================= TCTRL ========================================================= */ 39 #define MEC_CCT_TCTRL_ACTV_Pos (0UL) /*!< ACTV (Bit 0) */ 40 #define MEC_CCT_TCTRL_ACTV_Msk (0x1UL) /*!< ACTV (Bitfield-Mask: 0x01) */ 41 #define MEC_CCT_TCTRL_FREN_Pos (1UL) /*!< FREN (Bit 1) */ 42 #define MEC_CCT_TCTRL_FREN_Msk (0x2UL) /*!< FREN (Bitfield-Mask: 0x01) */ 43 #define MEC_CCT_TCTRL_FRRST_Pos (2UL) /*!< FRRST (Bit 2) */ 44 #define MEC_CCT_TCTRL_FRRST_Msk (0x4UL) /*!< FRRST (Bitfield-Mask: 0x01) */ 45 #define MEC_CCT_TCTRL_TCLK_FREQ_Pos (4UL) /*!< TCLK_FREQ (Bit 4) */ 46 #define MEC_CCT_TCTRL_TCLK_FREQ_Msk (0x70UL) /*!< TCLK_FREQ (Bitfield-Mask: 0x07) */ 47 #define MEC_CCT_TCTRL_COMP0_EN_Pos (8UL) /*!< COMP0_EN (Bit 8) */ 48 #define MEC_CCT_TCTRL_COMP0_EN_Msk (0x100UL) /*!< COMP0_EN (Bitfield-Mask: 0x01) */ 49 #define MEC_CCT_TCTRL_COMP1_EN_Pos (9UL) /*!< COMP1_EN (Bit 9) */ 50 #define MEC_CCT_TCTRL_COMP1_EN_Msk (0x200UL) /*!< COMP1_EN (Bitfield-Mask: 0x01) */ 51 #define MEC_CCT_TCTRL_COMP1_SET_Pos (16UL) /*!< COMP1_SET (Bit 16) */ 52 #define MEC_CCT_TCTRL_COMP1_SET_Msk (0x10000UL) /*!< COMP1_SET (Bitfield-Mask: 0x01) */ 53 #define MEC_CCT_TCTRL_COMP0_SET_Pos (17UL) /*!< COMP0_SET (Bit 17) */ 54 #define MEC_CCT_TCTRL_COMP0_SET_Msk (0x20000UL) /*!< COMP0_SET (Bitfield-Mask: 0x01) */ 55 #define MEC_CCT_TCTRL_COMP1_CLR_Pos (24UL) /*!< COMP1_CLR (Bit 24) */ 56 #define MEC_CCT_TCTRL_COMP1_CLR_Msk (0x1000000UL) /*!< COMP1_CLR (Bitfield-Mask: 0x01) */ 57 #define MEC_CCT_TCTRL_COMP0_CLR_Pos (25UL) /*!< COMP0_CLR (Bit 25) */ 58 #define MEC_CCT_TCTRL_COMP0_CLR_Msk (0x2000000UL) /*!< COMP0_CLR (Bitfield-Mask: 0x01) */ 59 /* ======================================================= CAP_CTRL0 ======================================================= */ 60 #define MEC_CCT_CAP_CTRL0_CAP0_EDGE_Pos (0UL) /*!< CAP0_EDGE (Bit 0) */ 61 #define MEC_CCT_CAP_CTRL0_CAP0_EDGE_Msk (0x3UL) /*!< CAP0_EDGE (Bitfield-Mask: 0x03) */ 62 #define MEC_CCT_CAP_CTRL0_FILT0_BYP_Pos (2UL) /*!< FILT0_BYP (Bit 2) */ 63 #define MEC_CCT_CAP_CTRL0_FILT0_BYP_Msk (0x4UL) /*!< FILT0_BYP (Bitfield-Mask: 0x01) */ 64 #define MEC_CCT_CAP_CTRL0_FCLK0_SEL_Pos (5UL) /*!< FCLK0_SEL (Bit 5) */ 65 #define MEC_CCT_CAP_CTRL0_FCLK0_SEL_Msk (0xe0UL) /*!< FCLK0_SEL (Bitfield-Mask: 0x07) */ 66 #define MEC_CCT_CAP_CTRL0_CAP1_EDGE_Pos (8UL) /*!< CAP1_EDGE (Bit 8) */ 67 #define MEC_CCT_CAP_CTRL0_CAP1_EDGE_Msk (0x300UL) /*!< CAP1_EDGE (Bitfield-Mask: 0x03) */ 68 #define MEC_CCT_CAP_CTRL0_FILT1_BYP_Pos (10UL) /*!< FILT1_BYP (Bit 10) */ 69 #define MEC_CCT_CAP_CTRL0_FILT1_BYP_Msk (0x400UL) /*!< FILT1_BYP (Bitfield-Mask: 0x01) */ 70 #define MEC_CCT_CAP_CTRL0_FCLK1_SEL_Pos (13UL) /*!< FCLK1_SEL (Bit 13) */ 71 #define MEC_CCT_CAP_CTRL0_FCLK1_SEL_Msk (0xe000UL) /*!< FCLK1_SEL (Bitfield-Mask: 0x07) */ 72 #define MEC_CCT_CAP_CTRL0_CAP2_EDGE_Pos (16UL) /*!< CAP2_EDGE (Bit 16) */ 73 #define MEC_CCT_CAP_CTRL0_CAP2_EDGE_Msk (0x30000UL) /*!< CAP2_EDGE (Bitfield-Mask: 0x03) */ 74 #define MEC_CCT_CAP_CTRL0_FILT2_BYP_Pos (18UL) /*!< FILT2_BYP (Bit 18) */ 75 #define MEC_CCT_CAP_CTRL0_FILT2_BYP_Msk (0x40000UL) /*!< FILT2_BYP (Bitfield-Mask: 0x01) */ 76 #define MEC_CCT_CAP_CTRL0_FCLK2_SEL_Pos (21UL) /*!< FCLK2_SEL (Bit 21) */ 77 #define MEC_CCT_CAP_CTRL0_FCLK2_SEL_Msk (0xe00000UL) /*!< FCLK2_SEL (Bitfield-Mask: 0x07) */ 78 #define MEC_CCT_CAP_CTRL0_CAP3_EDGE_Pos (24UL) /*!< CAP3_EDGE (Bit 24) */ 79 #define MEC_CCT_CAP_CTRL0_CAP3_EDGE_Msk (0x3000000UL) /*!< CAP3_EDGE (Bitfield-Mask: 0x03) */ 80 #define MEC_CCT_CAP_CTRL0_FILT3_BYP_Pos (26UL) /*!< FILT3_BYP (Bit 26) */ 81 #define MEC_CCT_CAP_CTRL0_FILT3_BYP_Msk (0x4000000UL) /*!< FILT3_BYP (Bitfield-Mask: 0x01) */ 82 #define MEC_CCT_CAP_CTRL0_FCLK3_SEL_Pos (29UL) /*!< FCLK3_SEL (Bit 29) */ 83 #define MEC_CCT_CAP_CTRL0_FCLK3_SEL_Msk (0xe0000000UL) /*!< FCLK3_SEL (Bitfield-Mask: 0x07) */ 84 /* ======================================================= CAP_CTRL1 ======================================================= */ 85 #define MEC_CCT_CAP_CTRL1_CAP4_EDGE_Pos (0UL) /*!< CAP4_EDGE (Bit 0) */ 86 #define MEC_CCT_CAP_CTRL1_CAP4_EDGE_Msk (0x3UL) /*!< CAP4_EDGE (Bitfield-Mask: 0x03) */ 87 #define MEC_CCT_CAP_CTRL1_FILT4_BYP_Pos (2UL) /*!< FILT4_BYP (Bit 2) */ 88 #define MEC_CCT_CAP_CTRL1_FILT4_BYP_Msk (0x4UL) /*!< FILT4_BYP (Bitfield-Mask: 0x01) */ 89 #define MEC_CCT_CAP_CTRL1_FCLK4_SEL_Pos (5UL) /*!< FCLK4_SEL (Bit 5) */ 90 #define MEC_CCT_CAP_CTRL1_FCLK4_SEL_Msk (0xe0UL) /*!< FCLK4_SEL (Bitfield-Mask: 0x07) */ 91 #define MEC_CCT_CAP_CTRL1_CAP5_EDGE_Pos (8UL) /*!< CAP5_EDGE (Bit 8) */ 92 #define MEC_CCT_CAP_CTRL1_CAP5_EDGE_Msk (0x300UL) /*!< CAP5_EDGE (Bitfield-Mask: 0x03) */ 93 #define MEC_CCT_CAP_CTRL1_FILT5_BYP_Pos (10UL) /*!< FILT5_BYP (Bit 10) */ 94 #define MEC_CCT_CAP_CTRL1_FILT5_BYP_Msk (0x400UL) /*!< FILT5_BYP (Bitfield-Mask: 0x01) */ 95 #define MEC_CCT_CAP_CTRL1_FCLK5_SEL_Pos (13UL) /*!< FCLK5_SEL (Bit 13) */ 96 #define MEC_CCT_CAP_CTRL1_FCLK5_SEL_Msk (0xe000UL) /*!< FCLK5_SEL (Bitfield-Mask: 0x07) */ 97 /* ======================================================= FR_COUNT ======================================================== */ 98 /* ======================================================= CAP0_CNT ======================================================== */ 99 /* ======================================================= CAP1_CNT ======================================================== */ 100 /* ======================================================= CAP2_CNT ======================================================== */ 101 /* ======================================================= CAP3_CNT ======================================================== */ 102 /* ======================================================= CAP4_CNT ======================================================== */ 103 /* ======================================================= CAP5_CNT ======================================================== */ 104 /* ======================================================= CMP0_CNT ======================================================== */ 105 /* ======================================================= CMP1_CNT ======================================================== */ 106 /* ======================================================== MUX_SEL ======================================================== */ 107 #define MEC_CCT_MUX_SEL_CAP0_SEL_Pos (0UL) /*!< CAP0_SEL (Bit 0) */ 108 #define MEC_CCT_MUX_SEL_CAP0_SEL_Msk (0xfUL) /*!< CAP0_SEL (Bitfield-Mask: 0x0f) */ 109 #define MEC_CCT_MUX_SEL_CAP1_SEL_Pos (4UL) /*!< CAP1_SEL (Bit 4) */ 110 #define MEC_CCT_MUX_SEL_CAP1_SEL_Msk (0xf0UL) /*!< CAP1_SEL (Bitfield-Mask: 0x0f) */ 111 #define MEC_CCT_MUX_SEL_CAP2_SEL_Pos (8UL) /*!< CAP2_SEL (Bit 8) */ 112 #define MEC_CCT_MUX_SEL_CAP2_SEL_Msk (0xf00UL) /*!< CAP2_SEL (Bitfield-Mask: 0x0f) */ 113 #define MEC_CCT_MUX_SEL_CAP3_SEL_Pos (12UL) /*!< CAP3_SEL (Bit 12) */ 114 #define MEC_CCT_MUX_SEL_CAP3_SEL_Msk (0xf000UL) /*!< CAP3_SEL (Bitfield-Mask: 0x0f) */ 115 #define MEC_CCT_MUX_SEL_CAP4_SEL_Pos (16UL) /*!< CAP4_SEL (Bit 16) */ 116 #define MEC_CCT_MUX_SEL_CAP4_SEL_Msk (0xf0000UL) /*!< CAP4_SEL (Bitfield-Mask: 0x0f) */ 117 #define MEC_CCT_MUX_SEL_CAP5_SEL_Pos (20UL) /*!< CAP5_SEL (Bit 20) */ 118 #define MEC_CCT_MUX_SEL_CAP5_SEL_Msk (0xf00000UL) /*!< CAP5_SEL (Bitfield-Mask: 0x0f) */ 119 120 /** @} */ /* End of group PosMask_peripherals */ 121 122 /** @addtogroup EnumValue_peripherals 123 * @{ 124 */ 125 /* ========================================================= TCTRL ========================================================= */ 126 /* ============================================== MEC_CCT TCTRL ACTV [0..0] =============================================== */ 127 typedef enum { /*!< MEC_CCT_TCTRL_ACTV */ 128 MEC_CCT_TCTRL_ACTV_OFF = 0, /*!< OFF : CCT off and clocks gated */ 129 MEC_CCT_TCTRL_ACTV_ON = 1, /*!< ON : CCT on and clocks ungated */ 130 } MEC_CCT_TCTRL_ACTV_Enum; 131 132 /* ============================================== MEC_CCT TCTRL FREN [1..1] =============================================== */ 133 typedef enum { /*!< MEC_CCT_TCTRL_FREN */ 134 MEC_CCT_TCTRL_FREN_OFF = 0, /*!< OFF : Free run counter off */ 135 MEC_CCT_TCTRL_FREN_ON = 1, /*!< ON : Free run counter on and counting */ 136 } MEC_CCT_TCTRL_FREN_Enum; 137 138 /* ============================================== MEC_CCT TCTRL FRRST [2..2] ============================================== */ 139 typedef enum { /*!< MEC_CCT_TCTRL_FRRST */ 140 MEC_CCT_TCTRL_FRRST_EN = 1, /*!< EN : Self-clearing Free run counter reset */ 141 } MEC_CCT_TCTRL_FRRST_Enum; 142 143 /* ============================================ MEC_CCT TCTRL TCLK_FREQ [4..6] ============================================ */ 144 typedef enum { /*!< MEC_CCT_TCTRL_TCLK_FREQ */ 145 MEC_CCT_TCTRL_TCLK_FREQ_48M = 0, /*!< 48M : 48MHz CCT frequency */ 146 MEC_CCT_TCTRL_TCLK_FREQ_24M = 1, /*!< 24M : 24MHz CCT frequency */ 147 MEC_CCT_TCTRL_TCLK_FREQ_12M = 2, /*!< 12M : 12MHz CCT frequency */ 148 MEC_CCT_TCTRL_TCLK_FREQ_6M = 3, /*!< 6M : 6MHz CCT frequency */ 149 MEC_CCT_TCTRL_TCLK_FREQ_3M = 4, /*!< 3M : 3MHz CCT frequency */ 150 MEC_CCT_TCTRL_TCLK_FREQ_1500K = 5, /*!< 1500K : 1500KHz CCT frequency */ 151 MEC_CCT_TCTRL_TCLK_FREQ_750K = 6, /*!< 750K : 750KHz CCT frequency */ 152 MEC_CCT_TCTRL_TCLK_FREQ_375K = 7, /*!< 375K : 357KHz CCT frequency */ 153 } MEC_CCT_TCTRL_TCLK_FREQ_Enum; 154 155 /* ============================================ MEC_CCT TCTRL COMP0_EN [8..8] ============================================= */ 156 typedef enum { /*!< MEC_CCT_TCTRL_COMP0_EN */ 157 MEC_CCT_TCTRL_COMP0_EN_ON = 1, /*!< ON : Enable free run count comparator 0 */ 158 } MEC_CCT_TCTRL_COMP0_EN_Enum; 159 160 /* ============================================ MEC_CCT TCTRL COMP1_EN [9..9] ============================================= */ 161 typedef enum { /*!< MEC_CCT_TCTRL_COMP1_EN */ 162 MEC_CCT_TCTRL_COMP1_EN_ON = 1, /*!< ON : Enable free run count comparator 1 */ 163 } MEC_CCT_TCTRL_COMP1_EN_Enum; 164 165 /* =========================================== MEC_CCT TCTRL COMP1_SET [16..16] =========================================== */ 166 typedef enum { /*!< MEC_CCT_TCTRL_COMP1_SET */ 167 MEC_CCT_TCTRL_COMP1_SET_STS = 1, /*!< STS : Set Comparator 1 match status */ 168 } MEC_CCT_TCTRL_COMP1_SET_Enum; 169 170 /* =========================================== MEC_CCT TCTRL COMP0_SET [17..17] =========================================== */ 171 typedef enum { /*!< MEC_CCT_TCTRL_COMP0_SET */ 172 MEC_CCT_TCTRL_COMP0_SET_STS = 1, /*!< STS : Set Comparator 0 match status */ 173 } MEC_CCT_TCTRL_COMP0_SET_Enum; 174 175 /* =========================================== MEC_CCT TCTRL COMP1_CLR [24..24] =========================================== */ 176 typedef enum { /*!< MEC_CCT_TCTRL_COMP1_CLR */ 177 MEC_CCT_TCTRL_COMP1_CLR_STS = 1, /*!< STS : Clear Comparator 1 match status */ 178 } MEC_CCT_TCTRL_COMP1_CLR_Enum; 179 180 /* =========================================== MEC_CCT TCTRL COMP0_CLR [25..25] =========================================== */ 181 typedef enum { /*!< MEC_CCT_TCTRL_COMP0_CLR */ 182 MEC_CCT_TCTRL_COMP0_CLR_STS = 1, /*!< STS : Clear Comparator 0 match status */ 183 } MEC_CCT_TCTRL_COMP0_CLR_Enum; 184 185 /* ======================================================= CAP_CTRL0 ======================================================= */ 186 /* ========================================== MEC_CCT CAP_CTRL0 CAP0_EDGE [0..1] ========================================== */ 187 typedef enum { /*!< MEC_CCT_CAP_CTRL0_CAP0_EDGE */ 188 MEC_CCT_CAP_CTRL0_CAP0_EDGE_FALLING = 0, /*!< FALLING : Capture on falling edges */ 189 MEC_CCT_CAP_CTRL0_CAP0_EDGE_RISING = 1, /*!< RISING : Capture on rising edges */ 190 MEC_CCT_CAP_CTRL0_CAP0_EDGE_BOTH = 2, /*!< BOTH : Capture on both edges */ 191 MEC_CCT_CAP_CTRL0_CAP0_EDGE_DIS = 3, /*!< DIS : Capture event disabled */ 192 } MEC_CCT_CAP_CTRL0_CAP0_EDGE_Enum; 193 194 /* ========================================== MEC_CCT CAP_CTRL0 FILT0_BYP [2..2] ========================================== */ 195 typedef enum { /*!< MEC_CCT_CAP_CTRL0_FILT0_BYP */ 196 MEC_CCT_CAP_CTRL0_FILT0_BYP_EN = 1, /*!< EN : Enable bypass of input filter to capture 0 logic */ 197 } MEC_CCT_CAP_CTRL0_FILT0_BYP_Enum; 198 199 /* ========================================== MEC_CCT CAP_CTRL0 FCLK0_SEL [5..7] ========================================== */ 200 typedef enum { /*!< MEC_CCT_CAP_CTRL0_FCLK0_SEL */ 201 MEC_CCT_CAP_CTRL0_FCLK0_SEL_48M = 0, /*!< 48M : 48MHz CCT frequency */ 202 MEC_CCT_CAP_CTRL0_FCLK0_SEL_24M = 1, /*!< 24M : 24MHz CCT frequency */ 203 MEC_CCT_CAP_CTRL0_FCLK0_SEL_12M = 2, /*!< 12M : 12MHz CCT frequency */ 204 MEC_CCT_CAP_CTRL0_FCLK0_SEL_6M = 3, /*!< 6M : 6MHz CCT frequency */ 205 MEC_CCT_CAP_CTRL0_FCLK0_SEL_3M = 4, /*!< 3M : 3MHz CCT frequency */ 206 MEC_CCT_CAP_CTRL0_FCLK0_SEL_1500K = 5, /*!< 1500K : 1500KHz CCT frequency */ 207 MEC_CCT_CAP_CTRL0_FCLK0_SEL_750K = 6, /*!< 750K : 750KHz CCT frequency */ 208 MEC_CCT_CAP_CTRL0_FCLK0_SEL_375K = 7, /*!< 375K : 357KHz CCT frequency */ 209 } MEC_CCT_CAP_CTRL0_FCLK0_SEL_Enum; 210 211 /* ========================================== MEC_CCT CAP_CTRL0 CAP1_EDGE [8..9] ========================================== */ 212 typedef enum { /*!< MEC_CCT_CAP_CTRL0_CAP1_EDGE */ 213 MEC_CCT_CAP_CTRL0_CAP1_EDGE_FALLING = 0, /*!< FALLING : Capture on falling edges */ 214 MEC_CCT_CAP_CTRL0_CAP1_EDGE_RISING = 1, /*!< RISING : Capture on rising edges */ 215 MEC_CCT_CAP_CTRL0_CAP1_EDGE_BOTH = 2, /*!< BOTH : Capture on both edges */ 216 MEC_CCT_CAP_CTRL0_CAP1_EDGE_DIS = 3, /*!< DIS : Capture event disabled */ 217 } MEC_CCT_CAP_CTRL0_CAP1_EDGE_Enum; 218 219 /* ========================================= MEC_CCT CAP_CTRL0 FILT1_BYP [10..10] ========================================= */ 220 typedef enum { /*!< MEC_CCT_CAP_CTRL0_FILT1_BYP */ 221 MEC_CCT_CAP_CTRL0_FILT1_BYP_EN = 1, /*!< EN : Enable bypass of input filter to capture 1 logic */ 222 } MEC_CCT_CAP_CTRL0_FILT1_BYP_Enum; 223 224 /* ========================================= MEC_CCT CAP_CTRL0 FCLK1_SEL [13..15] ========================================= */ 225 typedef enum { /*!< MEC_CCT_CAP_CTRL0_FCLK1_SEL */ 226 MEC_CCT_CAP_CTRL0_FCLK1_SEL_48M = 0, /*!< 48M : 48MHz CCT frequency */ 227 MEC_CCT_CAP_CTRL0_FCLK1_SEL_24M = 1, /*!< 24M : 24MHz CCT frequency */ 228 MEC_CCT_CAP_CTRL0_FCLK1_SEL_12M = 2, /*!< 12M : 12MHz CCT frequency */ 229 MEC_CCT_CAP_CTRL0_FCLK1_SEL_6M = 3, /*!< 6M : 6MHz CCT frequency */ 230 MEC_CCT_CAP_CTRL0_FCLK1_SEL_3M = 4, /*!< 3M : 3MHz CCT frequency */ 231 MEC_CCT_CAP_CTRL0_FCLK1_SEL_1500K = 5, /*!< 1500K : 1500KHz CCT frequency */ 232 MEC_CCT_CAP_CTRL0_FCLK1_SEL_750K = 6, /*!< 750K : 750KHz CCT frequency */ 233 MEC_CCT_CAP_CTRL0_FCLK1_SEL_375K = 7, /*!< 375K : 357KHz CCT frequency */ 234 } MEC_CCT_CAP_CTRL0_FCLK1_SEL_Enum; 235 236 /* ========================================= MEC_CCT CAP_CTRL0 CAP2_EDGE [16..17] ========================================= */ 237 typedef enum { /*!< MEC_CCT_CAP_CTRL0_CAP2_EDGE */ 238 MEC_CCT_CAP_CTRL0_CAP2_EDGE_FALLING = 0, /*!< FALLING : Capture on falling edges */ 239 MEC_CCT_CAP_CTRL0_CAP2_EDGE_RISING = 1, /*!< RISING : Capture on rising edges */ 240 MEC_CCT_CAP_CTRL0_CAP2_EDGE_BOTH = 2, /*!< BOTH : Capture on both edges */ 241 MEC_CCT_CAP_CTRL0_CAP2_EDGE_DIS = 3, /*!< DIS : Capture event disabled */ 242 } MEC_CCT_CAP_CTRL0_CAP2_EDGE_Enum; 243 244 /* ========================================= MEC_CCT CAP_CTRL0 FILT2_BYP [18..18] ========================================= */ 245 typedef enum { /*!< MEC_CCT_CAP_CTRL0_FILT2_BYP */ 246 MEC_CCT_CAP_CTRL0_FILT2_BYP_EN = 1, /*!< EN : Enable bypass of input filter to capture 2 logic */ 247 } MEC_CCT_CAP_CTRL0_FILT2_BYP_Enum; 248 249 /* ========================================= MEC_CCT CAP_CTRL0 FCLK2_SEL [21..23] ========================================= */ 250 typedef enum { /*!< MEC_CCT_CAP_CTRL0_FCLK2_SEL */ 251 MEC_CCT_CAP_CTRL0_FCLK2_SEL_48M = 0, /*!< 48M : 48MHz CCT frequency */ 252 MEC_CCT_CAP_CTRL0_FCLK2_SEL_24M = 1, /*!< 24M : 24MHz CCT frequency */ 253 MEC_CCT_CAP_CTRL0_FCLK2_SEL_12M = 2, /*!< 12M : 12MHz CCT frequency */ 254 MEC_CCT_CAP_CTRL0_FCLK2_SEL_6M = 3, /*!< 6M : 6MHz CCT frequency */ 255 MEC_CCT_CAP_CTRL0_FCLK2_SEL_3M = 4, /*!< 3M : 3MHz CCT frequency */ 256 MEC_CCT_CAP_CTRL0_FCLK2_SEL_1500K = 5, /*!< 1500K : 1500KHz CCT frequency */ 257 MEC_CCT_CAP_CTRL0_FCLK2_SEL_750K = 6, /*!< 750K : 750KHz CCT frequency */ 258 MEC_CCT_CAP_CTRL0_FCLK2_SEL_375K = 7, /*!< 375K : 357KHz CCT frequency */ 259 } MEC_CCT_CAP_CTRL0_FCLK2_SEL_Enum; 260 261 /* ========================================= MEC_CCT CAP_CTRL0 CAP3_EDGE [24..25] ========================================= */ 262 typedef enum { /*!< MEC_CCT_CAP_CTRL0_CAP3_EDGE */ 263 MEC_CCT_CAP_CTRL0_CAP3_EDGE_FALLING = 0, /*!< FALLING : Capture on falling edges */ 264 MEC_CCT_CAP_CTRL0_CAP3_EDGE_RISING = 1, /*!< RISING : Capture on rising edges */ 265 MEC_CCT_CAP_CTRL0_CAP3_EDGE_BOTH = 2, /*!< BOTH : Capture on both edges */ 266 MEC_CCT_CAP_CTRL0_CAP3_EDGE_DIS = 3, /*!< DIS : Capture event disabled */ 267 } MEC_CCT_CAP_CTRL0_CAP3_EDGE_Enum; 268 269 /* ========================================= MEC_CCT CAP_CTRL0 FILT3_BYP [26..26] ========================================= */ 270 typedef enum { /*!< MEC_CCT_CAP_CTRL0_FILT3_BYP */ 271 MEC_CCT_CAP_CTRL0_FILT3_BYP_EN = 1, /*!< EN : Enable bypass of input filter to capture 3 logic */ 272 } MEC_CCT_CAP_CTRL0_FILT3_BYP_Enum; 273 274 /* ========================================= MEC_CCT CAP_CTRL0 FCLK3_SEL [29..31] ========================================= */ 275 typedef enum { /*!< MEC_CCT_CAP_CTRL0_FCLK3_SEL */ 276 MEC_CCT_CAP_CTRL0_FCLK3_SEL_48M = 0, /*!< 48M : 48MHz CCT frequency */ 277 MEC_CCT_CAP_CTRL0_FCLK3_SEL_24M = 1, /*!< 24M : 24MHz CCT frequency */ 278 MEC_CCT_CAP_CTRL0_FCLK3_SEL_12M = 2, /*!< 12M : 12MHz CCT frequency */ 279 MEC_CCT_CAP_CTRL0_FCLK3_SEL_6M = 3, /*!< 6M : 6MHz CCT frequency */ 280 MEC_CCT_CAP_CTRL0_FCLK3_SEL_3M = 4, /*!< 3M : 3MHz CCT frequency */ 281 MEC_CCT_CAP_CTRL0_FCLK3_SEL_1500K = 5, /*!< 1500K : 1500KHz CCT frequency */ 282 MEC_CCT_CAP_CTRL0_FCLK3_SEL_750K = 6, /*!< 750K : 750KHz CCT frequency */ 283 MEC_CCT_CAP_CTRL0_FCLK3_SEL_375K = 7, /*!< 375K : 357KHz CCT frequency */ 284 } MEC_CCT_CAP_CTRL0_FCLK3_SEL_Enum; 285 286 /* ======================================================= CAP_CTRL1 ======================================================= */ 287 /* ========================================== MEC_CCT CAP_CTRL1 CAP4_EDGE [0..1] ========================================== */ 288 typedef enum { /*!< MEC_CCT_CAP_CTRL1_CAP4_EDGE */ 289 MEC_CCT_CAP_CTRL1_CAP4_EDGE_FALLING = 0, /*!< FALLING : Capture on falling edges */ 290 MEC_CCT_CAP_CTRL1_CAP4_EDGE_RISING = 1, /*!< RISING : Capture on rising edges */ 291 MEC_CCT_CAP_CTRL1_CAP4_EDGE_BOTH = 2, /*!< BOTH : Capture on both edges */ 292 MEC_CCT_CAP_CTRL1_CAP4_EDGE_DIS = 3, /*!< DIS : Capture event disabled */ 293 } MEC_CCT_CAP_CTRL1_CAP4_EDGE_Enum; 294 295 /* ========================================== MEC_CCT CAP_CTRL1 FILT4_BYP [2..2] ========================================== */ 296 typedef enum { /*!< MEC_CCT_CAP_CTRL1_FILT4_BYP */ 297 MEC_CCT_CAP_CTRL1_FILT4_BYP_EN = 1, /*!< EN : Enable bypass of input filter to capture 4 logic */ 298 } MEC_CCT_CAP_CTRL1_FILT4_BYP_Enum; 299 300 /* ========================================== MEC_CCT CAP_CTRL1 FCLK4_SEL [5..7] ========================================== */ 301 typedef enum { /*!< MEC_CCT_CAP_CTRL1_FCLK4_SEL */ 302 MEC_CCT_CAP_CTRL1_FCLK4_SEL_48M = 0, /*!< 48M : 48MHz CCT frequency */ 303 MEC_CCT_CAP_CTRL1_FCLK4_SEL_24M = 1, /*!< 24M : 24MHz CCT frequency */ 304 MEC_CCT_CAP_CTRL1_FCLK4_SEL_12M = 2, /*!< 12M : 12MHz CCT frequency */ 305 MEC_CCT_CAP_CTRL1_FCLK4_SEL_6M = 3, /*!< 6M : 6MHz CCT frequency */ 306 MEC_CCT_CAP_CTRL1_FCLK4_SEL_3M = 4, /*!< 3M : 3MHz CCT frequency */ 307 MEC_CCT_CAP_CTRL1_FCLK4_SEL_1500K = 5, /*!< 1500K : 1500KHz CCT frequency */ 308 MEC_CCT_CAP_CTRL1_FCLK4_SEL_750K = 6, /*!< 750K : 750KHz CCT frequency */ 309 MEC_CCT_CAP_CTRL1_FCLK4_SEL_375K = 7, /*!< 375K : 357KHz CCT frequency */ 310 } MEC_CCT_CAP_CTRL1_FCLK4_SEL_Enum; 311 312 /* ========================================== MEC_CCT CAP_CTRL1 CAP5_EDGE [8..9] ========================================== */ 313 typedef enum { /*!< MEC_CCT_CAP_CTRL1_CAP5_EDGE */ 314 MEC_CCT_CAP_CTRL1_CAP5_EDGE_FALLING = 0, /*!< FALLING : Capture on falling edges */ 315 MEC_CCT_CAP_CTRL1_CAP5_EDGE_RISING = 1, /*!< RISING : Capture on rising edges */ 316 MEC_CCT_CAP_CTRL1_CAP5_EDGE_BOTH = 2, /*!< BOTH : Capture on both edges */ 317 MEC_CCT_CAP_CTRL1_CAP5_EDGE_DIS = 3, /*!< DIS : Capture event disabled */ 318 } MEC_CCT_CAP_CTRL1_CAP5_EDGE_Enum; 319 320 /* ========================================= MEC_CCT CAP_CTRL1 FILT5_BYP [10..10] ========================================= */ 321 typedef enum { /*!< MEC_CCT_CAP_CTRL1_FILT5_BYP */ 322 MEC_CCT_CAP_CTRL1_FILT5_BYP_EN = 1, /*!< EN : Enable bypass of input filter to capture 5 logic */ 323 } MEC_CCT_CAP_CTRL1_FILT5_BYP_Enum; 324 325 /* ========================================= MEC_CCT CAP_CTRL1 FCLK5_SEL [13..15] ========================================= */ 326 typedef enum { /*!< MEC_CCT_CAP_CTRL1_FCLK5_SEL */ 327 MEC_CCT_CAP_CTRL1_FCLK5_SEL_48M = 0, /*!< 48M : 48MHz CCT frequency */ 328 MEC_CCT_CAP_CTRL1_FCLK5_SEL_24M = 1, /*!< 24M : 24MHz CCT frequency */ 329 MEC_CCT_CAP_CTRL1_FCLK5_SEL_12M = 2, /*!< 12M : 12MHz CCT frequency */ 330 MEC_CCT_CAP_CTRL1_FCLK5_SEL_6M = 3, /*!< 6M : 6MHz CCT frequency */ 331 MEC_CCT_CAP_CTRL1_FCLK5_SEL_3M = 4, /*!< 3M : 3MHz CCT frequency */ 332 MEC_CCT_CAP_CTRL1_FCLK5_SEL_1500K = 5, /*!< 1500K : 1500KHz CCT frequency */ 333 MEC_CCT_CAP_CTRL1_FCLK5_SEL_750K = 6, /*!< 750K : 750KHz CCT frequency */ 334 MEC_CCT_CAP_CTRL1_FCLK5_SEL_375K = 7, /*!< 375K : 357KHz CCT frequency */ 335 } MEC_CCT_CAP_CTRL1_FCLK5_SEL_Enum; 336 337 /* ======================================================= FR_COUNT ======================================================== */ 338 /* ======================================================= CAP0_CNT ======================================================== */ 339 /* ======================================================= CAP1_CNT ======================================================== */ 340 /* ======================================================= CAP2_CNT ======================================================== */ 341 /* ======================================================= CAP3_CNT ======================================================== */ 342 /* ======================================================= CAP4_CNT ======================================================== */ 343 /* ======================================================= CAP5_CNT ======================================================== */ 344 /* ======================================================= CMP0_CNT ======================================================== */ 345 /* ======================================================= CMP1_CNT ======================================================== */ 346 /* ======================================================== MUX_SEL ======================================================== */ 347 /* =========================================== MEC_CCT MUX_SEL CAP0_SEL [0..3] ============================================ */ 348 typedef enum { /*!< MEC_CCT_MUX_SEL_CAP0_SEL */ 349 MEC_CCT_MUX_SEL_CAP0_SEL_ICT00 = 0, /*!< ICT00 : Select ICT00 pin as input to Capture 0 */ 350 MEC_CCT_MUX_SEL_CAP0_SEL_ICT01 = 1, /*!< ICT01 : Select ICT01 pin as input to Capture 0 */ 351 MEC_CCT_MUX_SEL_CAP0_SEL_ICT02 = 2, /*!< ICT02 : Select ICT02 pin as input to Capture 0 */ 352 MEC_CCT_MUX_SEL_CAP0_SEL_ICT03 = 3, /*!< ICT03 : Select ICT03 pin as input to Capture 0 */ 353 MEC_CCT_MUX_SEL_CAP0_SEL_ICT04 = 4, /*!< ICT04 : Select ICT04 pin as input to Capture 0 */ 354 MEC_CCT_MUX_SEL_CAP0_SEL_ICT05 = 5, /*!< ICT05 : Select ICT05 pin as input to Capture 0 */ 355 MEC_CCT_MUX_SEL_CAP0_SEL_ICT06 = 6, /*!< ICT06 : Select ICT06 pin as input to Capture 0 */ 356 MEC_CCT_MUX_SEL_CAP0_SEL_ICT07 = 7, /*!< ICT07 : Select ICT07 pin as input to Capture 0 */ 357 MEC_CCT_MUX_SEL_CAP0_SEL_ICT08 = 8, /*!< ICT08 : Select ICT08 pin as input to Capture 0 */ 358 MEC_CCT_MUX_SEL_CAP0_SEL_ICT09 = 9, /*!< ICT09 : Select ICT09 pin as input to Capture 0 */ 359 MEC_CCT_MUX_SEL_CAP0_SEL_ICT10 = 10, /*!< ICT10 : Select ICT10 pin as input to Capture 0 */ 360 MEC_CCT_MUX_SEL_CAP0_SEL_ICT11 = 11, /*!< ICT11 : Select ICT11 pin as input to Capture 0 */ 361 MEC_CCT_MUX_SEL_CAP0_SEL_ICT12 = 12, /*!< ICT12 : Select ICT12 pin as input to Capture 0 */ 362 MEC_CCT_MUX_SEL_CAP0_SEL_ICT13 = 13, /*!< ICT13 : Select ICT13 pin as input to Capture 0 */ 363 MEC_CCT_MUX_SEL_CAP0_SEL_ICT14 = 14, /*!< ICT14 : Select ICT14 pin as input to Capture 0 */ 364 MEC_CCT_MUX_SEL_CAP0_SEL_ICT15 = 15, /*!< ICT15 : Select ICT15 pin as input to Capture 0 */ 365 } MEC_CCT_MUX_SEL_CAP0_SEL_Enum; 366 367 /* =========================================== MEC_CCT MUX_SEL CAP1_SEL [4..7] ============================================ */ 368 typedef enum { /*!< MEC_CCT_MUX_SEL_CAP1_SEL */ 369 MEC_CCT_MUX_SEL_CAP1_SEL_ICT00 = 0, /*!< ICT00 : Select ICT00 pin as input to Capture 1 */ 370 MEC_CCT_MUX_SEL_CAP1_SEL_ICT01 = 1, /*!< ICT01 : Select ICT01 pin as input to Capture 1 */ 371 MEC_CCT_MUX_SEL_CAP1_SEL_ICT02 = 2, /*!< ICT02 : Select ICT02 pin as input to Capture 1 */ 372 MEC_CCT_MUX_SEL_CAP1_SEL_ICT03 = 3, /*!< ICT03 : Select ICT03 pin as input to Capture 1 */ 373 MEC_CCT_MUX_SEL_CAP1_SEL_ICT04 = 4, /*!< ICT04 : Select ICT04 pin as input to Capture 1 */ 374 MEC_CCT_MUX_SEL_CAP1_SEL_ICT05 = 5, /*!< ICT05 : Select ICT05 pin as input to Capture 1 */ 375 MEC_CCT_MUX_SEL_CAP1_SEL_ICT06 = 6, /*!< ICT06 : Select ICT06 pin as input to Capture 1 */ 376 MEC_CCT_MUX_SEL_CAP1_SEL_ICT07 = 7, /*!< ICT07 : Select ICT07 pin as input to Capture 1 */ 377 MEC_CCT_MUX_SEL_CAP1_SEL_ICT08 = 8, /*!< ICT08 : Select ICT08 pin as input to Capture 1 */ 378 MEC_CCT_MUX_SEL_CAP1_SEL_ICT09 = 9, /*!< ICT09 : Select ICT09 pin as input to Capture 1 */ 379 MEC_CCT_MUX_SEL_CAP1_SEL_ICT10 = 10, /*!< ICT10 : Select ICT10 pin as input to Capture 1 */ 380 MEC_CCT_MUX_SEL_CAP1_SEL_ICT11 = 11, /*!< ICT11 : Select ICT11 pin as input to Capture 1 */ 381 MEC_CCT_MUX_SEL_CAP1_SEL_ICT12 = 12, /*!< ICT12 : Select ICT12 pin as input to Capture 1 */ 382 MEC_CCT_MUX_SEL_CAP1_SEL_ICT13 = 13, /*!< ICT13 : Select ICT13 pin as input to Capture 1 */ 383 MEC_CCT_MUX_SEL_CAP1_SEL_ICT14 = 14, /*!< ICT14 : Select ICT14 pin as input to Capture 1 */ 384 MEC_CCT_MUX_SEL_CAP1_SEL_ICT15 = 15, /*!< ICT15 : Select ICT15 pin as input to Capture 1 */ 385 } MEC_CCT_MUX_SEL_CAP1_SEL_Enum; 386 387 /* =========================================== MEC_CCT MUX_SEL CAP2_SEL [8..11] =========================================== */ 388 typedef enum { /*!< MEC_CCT_MUX_SEL_CAP2_SEL */ 389 MEC_CCT_MUX_SEL_CAP2_SEL_ICT00 = 0, /*!< ICT00 : Select ICT00 pin as input to Capture 2 */ 390 MEC_CCT_MUX_SEL_CAP2_SEL_ICT01 = 1, /*!< ICT01 : Select ICT01 pin as input to Capture 2 */ 391 MEC_CCT_MUX_SEL_CAP2_SEL_ICT02 = 2, /*!< ICT02 : Select ICT02 pin as input to Capture 2 */ 392 MEC_CCT_MUX_SEL_CAP2_SEL_ICT03 = 3, /*!< ICT03 : Select ICT03 pin as input to Capture 2 */ 393 MEC_CCT_MUX_SEL_CAP2_SEL_ICT04 = 4, /*!< ICT04 : Select ICT04 pin as input to Capture 2 */ 394 MEC_CCT_MUX_SEL_CAP2_SEL_ICT05 = 5, /*!< ICT05 : Select ICT05 pin as input to Capture 2 */ 395 MEC_CCT_MUX_SEL_CAP2_SEL_ICT06 = 6, /*!< ICT06 : Select ICT06 pin as input to Capture 2 */ 396 MEC_CCT_MUX_SEL_CAP2_SEL_ICT07 = 7, /*!< ICT07 : Select ICT07 pin as input to Capture 2 */ 397 MEC_CCT_MUX_SEL_CAP2_SEL_ICT08 = 8, /*!< ICT08 : Select ICT08 pin as input to Capture 2 */ 398 MEC_CCT_MUX_SEL_CAP2_SEL_ICT09 = 9, /*!< ICT09 : Select ICT09 pin as input to Capture 2 */ 399 MEC_CCT_MUX_SEL_CAP2_SEL_ICT10 = 10, /*!< ICT10 : Select ICT10 pin as input to Capture 2 */ 400 MEC_CCT_MUX_SEL_CAP2_SEL_ICT11 = 11, /*!< ICT11 : Select ICT11 pin as input to Capture 2 */ 401 MEC_CCT_MUX_SEL_CAP2_SEL_ICT12 = 12, /*!< ICT12 : Select ICT12 pin as input to Capture 2 */ 402 MEC_CCT_MUX_SEL_CAP2_SEL_ICT13 = 13, /*!< ICT13 : Select ICT13 pin as input to Capture 2 */ 403 MEC_CCT_MUX_SEL_CAP2_SEL_ICT14 = 14, /*!< ICT14 : Select ICT14 pin as input to Capture 2 */ 404 MEC_CCT_MUX_SEL_CAP2_SEL_ICT15 = 15, /*!< ICT15 : Select ICT15 pin as input to Capture 2 */ 405 } MEC_CCT_MUX_SEL_CAP2_SEL_Enum; 406 407 /* ========================================== MEC_CCT MUX_SEL CAP3_SEL [12..15] =========================================== */ 408 typedef enum { /*!< MEC_CCT_MUX_SEL_CAP3_SEL */ 409 MEC_CCT_MUX_SEL_CAP3_SEL_ICT00 = 0, /*!< ICT00 : Select ICT00 pin as input to Capture 3 */ 410 MEC_CCT_MUX_SEL_CAP3_SEL_ICT01 = 1, /*!< ICT01 : Select ICT01 pin as input to Capture 3 */ 411 MEC_CCT_MUX_SEL_CAP3_SEL_ICT02 = 2, /*!< ICT02 : Select ICT02 pin as input to Capture 3 */ 412 MEC_CCT_MUX_SEL_CAP3_SEL_ICT03 = 3, /*!< ICT03 : Select ICT03 pin as input to Capture 3 */ 413 MEC_CCT_MUX_SEL_CAP3_SEL_ICT04 = 4, /*!< ICT04 : Select ICT04 pin as input to Capture 3 */ 414 MEC_CCT_MUX_SEL_CAP3_SEL_ICT05 = 5, /*!< ICT05 : Select ICT05 pin as input to Capture 3 */ 415 MEC_CCT_MUX_SEL_CAP3_SEL_ICT06 = 6, /*!< ICT06 : Select ICT06 pin as input to Capture 3 */ 416 MEC_CCT_MUX_SEL_CAP3_SEL_ICT07 = 7, /*!< ICT07 : Select ICT07 pin as input to Capture 3 */ 417 MEC_CCT_MUX_SEL_CAP3_SEL_ICT08 = 8, /*!< ICT08 : Select ICT08 pin as input to Capture 3 */ 418 MEC_CCT_MUX_SEL_CAP3_SEL_ICT09 = 9, /*!< ICT09 : Select ICT09 pin as input to Capture 3 */ 419 MEC_CCT_MUX_SEL_CAP3_SEL_ICT10 = 10, /*!< ICT10 : Select ICT10 pin as input to Capture 3 */ 420 MEC_CCT_MUX_SEL_CAP3_SEL_ICT11 = 11, /*!< ICT11 : Select ICT11 pin as input to Capture 3 */ 421 MEC_CCT_MUX_SEL_CAP3_SEL_ICT12 = 12, /*!< ICT12 : Select ICT12 pin as input to Capture 3 */ 422 MEC_CCT_MUX_SEL_CAP3_SEL_ICT13 = 13, /*!< ICT13 : Select ICT13 pin as input to Capture 3 */ 423 MEC_CCT_MUX_SEL_CAP3_SEL_ICT14 = 14, /*!< ICT14 : Select ICT14 pin as input to Capture 3 */ 424 MEC_CCT_MUX_SEL_CAP3_SEL_ICT15 = 15, /*!< ICT15 : Select ICT15 pin as input to Capture 3 */ 425 } MEC_CCT_MUX_SEL_CAP3_SEL_Enum; 426 427 /* ========================================== MEC_CCT MUX_SEL CAP4_SEL [16..19] =========================================== */ 428 typedef enum { /*!< MEC_CCT_MUX_SEL_CAP4_SEL */ 429 MEC_CCT_MUX_SEL_CAP4_SEL_ICT00 = 0, /*!< ICT00 : Select ICT00 pin as input to Capture 4 */ 430 MEC_CCT_MUX_SEL_CAP4_SEL_ICT01 = 1, /*!< ICT01 : Select ICT01 pin as input to Capture 4 */ 431 MEC_CCT_MUX_SEL_CAP4_SEL_ICT02 = 2, /*!< ICT02 : Select ICT02 pin as input to Capture 4 */ 432 MEC_CCT_MUX_SEL_CAP4_SEL_ICT03 = 3, /*!< ICT03 : Select ICT03 pin as input to Capture 4 */ 433 MEC_CCT_MUX_SEL_CAP4_SEL_ICT04 = 4, /*!< ICT04 : Select ICT04 pin as input to Capture 4 */ 434 MEC_CCT_MUX_SEL_CAP4_SEL_ICT05 = 5, /*!< ICT05 : Select ICT05 pin as input to Capture 4 */ 435 MEC_CCT_MUX_SEL_CAP4_SEL_ICT06 = 6, /*!< ICT06 : Select ICT06 pin as input to Capture 4 */ 436 MEC_CCT_MUX_SEL_CAP4_SEL_ICT07 = 7, /*!< ICT07 : Select ICT07 pin as input to Capture 4 */ 437 MEC_CCT_MUX_SEL_CAP4_SEL_ICT08 = 8, /*!< ICT08 : Select ICT08 pin as input to Capture 4 */ 438 MEC_CCT_MUX_SEL_CAP4_SEL_ICT09 = 9, /*!< ICT09 : Select ICT09 pin as input to Capture 4 */ 439 MEC_CCT_MUX_SEL_CAP4_SEL_ICT10 = 10, /*!< ICT10 : Select ICT10 pin as input to Capture 4 */ 440 MEC_CCT_MUX_SEL_CAP4_SEL_ICT11 = 11, /*!< ICT11 : Select ICT11 pin as input to Capture 4 */ 441 MEC_CCT_MUX_SEL_CAP4_SEL_ICT12 = 12, /*!< ICT12 : Select ICT12 pin as input to Capture 4 */ 442 MEC_CCT_MUX_SEL_CAP4_SEL_ICT13 = 13, /*!< ICT13 : Select ICT13 pin as input to Capture 4 */ 443 MEC_CCT_MUX_SEL_CAP4_SEL_ICT14 = 14, /*!< ICT14 : Select ICT14 pin as input to Capture 4 */ 444 MEC_CCT_MUX_SEL_CAP4_SEL_ICT15 = 15, /*!< ICT15 : Select ICT15 pin as input to Capture 4 */ 445 } MEC_CCT_MUX_SEL_CAP4_SEL_Enum; 446 447 /* ========================================== MEC_CCT MUX_SEL CAP5_SEL [20..23] =========================================== */ 448 typedef enum { /*!< MEC_CCT_MUX_SEL_CAP5_SEL */ 449 MEC_CCT_MUX_SEL_CAP5_SEL_ICT00 = 0, /*!< ICT00 : Select ICT00 pin as input to Capture 5 */ 450 MEC_CCT_MUX_SEL_CAP5_SEL_ICT01 = 1, /*!< ICT01 : Select ICT01 pin as input to Capture 5 */ 451 MEC_CCT_MUX_SEL_CAP5_SEL_ICT02 = 2, /*!< ICT02 : Select ICT02 pin as input to Capture 5 */ 452 MEC_CCT_MUX_SEL_CAP5_SEL_ICT03 = 3, /*!< ICT03 : Select ICT03 pin as input to Capture 5 */ 453 MEC_CCT_MUX_SEL_CAP5_SEL_ICT04 = 4, /*!< ICT04 : Select ICT04 pin as input to Capture 5 */ 454 MEC_CCT_MUX_SEL_CAP5_SEL_ICT05 = 5, /*!< ICT05 : Select ICT05 pin as input to Capture 5 */ 455 MEC_CCT_MUX_SEL_CAP5_SEL_ICT06 = 6, /*!< ICT06 : Select ICT06 pin as input to Capture 5 */ 456 MEC_CCT_MUX_SEL_CAP5_SEL_ICT07 = 7, /*!< ICT07 : Select ICT07 pin as input to Capture 5 */ 457 MEC_CCT_MUX_SEL_CAP5_SEL_ICT08 = 8, /*!< ICT08 : Select ICT08 pin as input to Capture 5 */ 458 MEC_CCT_MUX_SEL_CAP5_SEL_ICT09 = 9, /*!< ICT09 : Select ICT09 pin as input to Capture 5 */ 459 MEC_CCT_MUX_SEL_CAP5_SEL_ICT10 = 10, /*!< ICT10 : Select ICT10 pin as input to Capture 5 */ 460 MEC_CCT_MUX_SEL_CAP5_SEL_ICT11 = 11, /*!< ICT11 : Select ICT11 pin as input to Capture 5 */ 461 MEC_CCT_MUX_SEL_CAP5_SEL_ICT12 = 12, /*!< ICT12 : Select ICT12 pin as input to Capture 5 */ 462 MEC_CCT_MUX_SEL_CAP5_SEL_ICT13 = 13, /*!< ICT13 : Select ICT13 pin as input to Capture 5 */ 463 MEC_CCT_MUX_SEL_CAP5_SEL_ICT14 = 14, /*!< ICT14 : Select ICT14 pin as input to Capture 5 */ 464 MEC_CCT_MUX_SEL_CAP5_SEL_ICT15 = 15, /*!< ICT15 : Select ICT15 pin as input to Capture 5 */ 465 } MEC_CCT_MUX_SEL_CAP5_SEL_Enum; 466 467 /** @} */ /* End of group EnumValue_peripherals */ 468 469 #endif /* _MEC5_CCT_V1_1_H */ 470
