1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_BDP_V1_H 7 #define _MEC5_BDP_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief BDP BIOS Debug Port: Host I/O Ports 80/90 (MEC_BDP0) 15 */ 16 17 typedef struct mec_bdp_regs { /*!< (@ 0x400F8000) MEC_BDP0 Structure */ 18 __OM uint32_t HP80D; /*!< (@ 0x00000000) BDP Runtime: Host Port80 data */ 19 __IM uint32_t RESERVED[63]; 20 __IM uint32_t DATRB; /*!< (@ 0x00000100) BDP EC-only: data with attributes */ 21 __IOM uint32_t CONFIG; /*!< (@ 0x00000104) BDP EC-only: configuration */ 22 __IM uint8_t STATUS; /*!< (@ 0x00000108) BDP EC-only: status(RO) */ 23 __IOM uint8_t IEN; /*!< (@ 0x00000109) BDP EC-only: interrupt enable */ 24 __IM uint16_t RESERVED1; 25 __IM uint32_t SNAP; /*!< (@ 0x0000010C) BDP EC-only: snapshot register */ 26 __IOM uint32_t CAPT; /*!< (@ 0x00000110) BDP EC-only: capture register */ 27 __IM uint32_t RESERVED2[135]; 28 __IOM uint8_t ACTV80; /*!< (@ 0x00000330) BDP EC-only: Port80 logical device activate */ 29 __IM uint8_t RESERVED3; 30 __IM uint16_t RESERVED4; 31 __IM uint32_t RESERVED5[51]; 32 __OM uint32_t HP80AD; /*!< (@ 0x00000400) BDP Runtime: Host Port80 alias data */ 33 __IM uint32_t RESERVED6[203]; 34 __IOM uint8_t ACTV80A; /*!< (@ 0x00000730) BDP EC-only: Port80 alias logical device activate */ 35 __IM uint8_t RESERVED7; 36 __IM uint16_t RESERVED8; 37 __IM uint32_t RESERVED9[47]; 38 __IOM uint8_t BL80A; /*!< (@ 0x000007F0) BDP EC-only: Port80 alias byte lane */ 39 __IM uint8_t RESERVED10; 40 __IM uint16_t RESERVED11; 41 } MEC_BDP_Type; /*!< Size = 2036 (0x7f4) */ 42 43 /** @} */ /* End of group Device_Peripheral_peripherals */ 44 45 /** @addtogroup PosMask_peripherals 46 * @{ 47 */ 48 /* ========================================================= HP80D ========================================================= */ 49 /* ========================================================= DATRB ========================================================= */ 50 #define MEC_BDP_DATRB_DATA_Pos (0UL) /*!< DATA (Bit 0) */ 51 #define MEC_BDP_DATRB_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ 52 #define MEC_BDP_DATRB_LANE_Pos (8UL) /*!< LANE (Bit 8) */ 53 #define MEC_BDP_DATRB_LANE_Msk (0x300UL) /*!< LANE (Bitfield-Mask: 0x03) */ 54 #define MEC_BDP_DATRB_LEN_Pos (10UL) /*!< LEN (Bit 10) */ 55 #define MEC_BDP_DATRB_LEN_Msk (0xc00UL) /*!< LEN (Bitfield-Mask: 0x03) */ 56 #define MEC_BDP_DATRB_NOT_EMPTY_Pos (12UL) /*!< NOT_EMPTY (Bit 12) */ 57 #define MEC_BDP_DATRB_NOT_EMPTY_Msk (0x1000UL) /*!< NOT_EMPTY (Bitfield-Mask: 0x01) */ 58 #define MEC_BDP_DATRB_OVERRUN_Pos (13UL) /*!< OVERRUN (Bit 13) */ 59 #define MEC_BDP_DATRB_OVERRUN_Msk (0x2000UL) /*!< OVERRUN (Bitfield-Mask: 0x01) */ 60 #define MEC_BDP_DATRB_THRES_Pos (14UL) /*!< THRES (Bit 14) */ 61 #define MEC_BDP_DATRB_THRES_Msk (0x4000UL) /*!< THRES (Bitfield-Mask: 0x01) */ 62 /* ======================================================== CONFIG ========================================================= */ 63 #define MEC_BDP_CONFIG_FLUSH_FIFO_Pos (0UL) /*!< FLUSH_FIFO (Bit 0) */ 64 #define MEC_BDP_CONFIG_FLUSH_FIFO_Msk (0x1UL) /*!< FLUSH_FIFO (Bitfield-Mask: 0x01) */ 65 #define MEC_BDP_CONFIG_CLR_SNAPSHOT_Pos (1UL) /*!< CLR_SNAPSHOT (Bit 1) */ 66 #define MEC_BDP_CONFIG_CLR_SNAPSHOT_Msk (0x2UL) /*!< CLR_SNAPSHOT (Bitfield-Mask: 0x01) */ 67 #define MEC_BDP_CONFIG_FIFO_THRES_Pos (8UL) /*!< FIFO_THRES (Bit 8) */ 68 #define MEC_BDP_CONFIG_FIFO_THRES_Msk (0x700UL) /*!< FIFO_THRES (Bitfield-Mask: 0x07) */ 69 #define MEC_BDP_CONFIG_SRST_Pos (31UL) /*!< SRST (Bit 31) */ 70 #define MEC_BDP_CONFIG_SRST_Msk (0x80000000UL) /*!< SRST (Bitfield-Mask: 0x01) */ 71 /* ======================================================== STATUS ========================================================= */ 72 #define MEC_BDP_STATUS_NOT_EMPTY_Pos (0UL) /*!< NOT_EMPTY (Bit 0) */ 73 #define MEC_BDP_STATUS_NOT_EMPTY_Msk (0x1UL) /*!< NOT_EMPTY (Bitfield-Mask: 0x01) */ 74 #define MEC_BDP_STATUS_OVERRUN_Pos (1UL) /*!< OVERRUN (Bit 1) */ 75 #define MEC_BDP_STATUS_OVERRUN_Msk (0x2UL) /*!< OVERRUN (Bitfield-Mask: 0x01) */ 76 #define MEC_BDP_STATUS_THRES_Pos (2UL) /*!< THRES (Bit 2) */ 77 #define MEC_BDP_STATUS_THRES_Msk (0x4UL) /*!< THRES (Bitfield-Mask: 0x01) */ 78 /* ========================================================== IEN ========================================================== */ 79 #define MEC_BDP_IEN_THRES_Pos (0UL) /*!< THRES (Bit 0) */ 80 #define MEC_BDP_IEN_THRES_Msk (0x1UL) /*!< THRES (Bitfield-Mask: 0x01) */ 81 /* ========================================================= SNAP ========================================================== */ 82 /* ========================================================= CAPT ========================================================== */ 83 /* ======================================================== ACTV80 ========================================================= */ 84 #define MEC_BDP_ACTV80_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ 85 #define MEC_BDP_ACTV80_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 86 /* ======================================================== HP80AD ========================================================= */ 87 /* ======================================================== ACTV80A ======================================================== */ 88 #define MEC_BDP_ACTV80A_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ 89 #define MEC_BDP_ACTV80A_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 90 /* ========================================================= BL80A ========================================================= */ 91 #define MEC_BDP_BL80A_ASBL_Pos (0UL) /*!< ASBL (Bit 0) */ 92 #define MEC_BDP_BL80A_ASBL_Msk (0x3UL) /*!< ASBL (Bitfield-Mask: 0x03) */ 93 94 /** @} */ /* End of group PosMask_peripherals */ 95 96 /** @addtogroup EnumValue_peripherals 97 * @{ 98 */ 99 /* ========================================================= HP80D ========================================================= */ 100 /* ========================================================= DATRB ========================================================= */ 101 /* ============================================== MEC_BDP DATRB LANE [8..9] =============================================== */ 102 typedef enum { /*!< MEC_BDP_DATRB_LANE */ 103 MEC_BDP_DATRB_LANE_B0 = 0, /*!< B0 : Byte lane 0 */ 104 MEC_BDP_DATRB_LANE_B1 = 1, /*!< B1 : Byte lane 1 */ 105 MEC_BDP_DATRB_LANE_B2 = 2, /*!< B2 : Byte lane 2 */ 106 MEC_BDP_DATRB_LANE_B3 = 3, /*!< B3 : Byte lane 3 */ 107 } MEC_BDP_DATRB_LANE_Enum; 108 109 /* ============================================== MEC_BDP DATRB LEN [10..11] ============================================== */ 110 typedef enum { /*!< MEC_BDP_DATRB_LEN */ 111 MEC_BDP_DATRB_LEN_IO8 = 0, /*!< IO8 : One byte or continuation of a mutli-byte value */ 112 MEC_BDP_DATRB_LEN_IO16B0 = 1, /*!< IO16B0 : First byte of a 16-bit I/O write */ 113 MEC_BDP_DATRB_LEN_IO32B0 = 2, /*!< IO32B0 : First byte of a 32-bit I/O write */ 114 MEC_BDP_DATRB_LEN_IO_INVAL = 3, /*!< IO_INVAL : Lost byte of a previous overrun. Should be discarded */ 115 } MEC_BDP_DATRB_LEN_Enum; 116 117 /* ======================================================== CONFIG ========================================================= */ 118 /* ========================================== MEC_BDP CONFIG FIFO_THRES [8..10] =========================================== */ 119 typedef enum { /*!< MEC_BDP_CONFIG_FIFO_THRES */ 120 MEC_BDP_CONFIG_FIFO_THRES_ENTRIES_1 = 0, /*!< ENTRIES_1 : FIFO Threshold status set if number of entries >= 1 */ 121 MEC_BDP_CONFIG_FIFO_THRES_ENTRIES_4 = 1, /*!< ENTRIES_4 : FIFO Threshold status set if number of entries >= 4 */ 122 MEC_BDP_CONFIG_FIFO_THRES_ENTRIES_8 = 2, /*!< ENTRIES_8 : FIFO Threshold status set if number of entries >= 8 */ 123 MEC_BDP_CONFIG_FIFO_THRES_ENTRIES_16 = 3, /*!< ENTRIES_16 : FIFO Threshold status set if number of entries >= 16 */ 124 MEC_BDP_CONFIG_FIFO_THRES_ENTRIES_20 = 4, /*!< ENTRIES_20 : FIFO Threshold status set if number of entries >= 20 */ 125 MEC_BDP_CONFIG_FIFO_THRES_ENTRIES_24 = 5, /*!< ENTRIES_24 : FIFO Threshold status set if number of entries >= 24 */ 126 MEC_BDP_CONFIG_FIFO_THRES_ENTRIES_28 = 6, /*!< ENTRIES_28 : FIFO Threshold status set if number of entries >= 28 */ 127 MEC_BDP_CONFIG_FIFO_THRES_ENTRIES_30 = 7, /*!< ENTRIES_30 : FIFO Threshold status set if number of entries >= 30 */ 128 } MEC_BDP_CONFIG_FIFO_THRES_Enum; 129 130 /* ======================================================== STATUS ========================================================= */ 131 /* ========================================================== IEN ========================================================== */ 132 /* ========================================================= SNAP ========================================================== */ 133 /* ========================================================= CAPT ========================================================== */ 134 /* ======================================================== ACTV80 ========================================================= */ 135 /* ======================================================== HP80AD ========================================================= */ 136 /* ======================================================== ACTV80A ======================================================== */ 137 /* ========================================================= BL80A ========================================================= */ 138 /* ============================================== MEC_BDP BL80A ASBL [0..1] =============================================== */ 139 typedef enum { /*!< MEC_BDP_BL80A_ASBL */ 140 MEC_BDP_BL80A_ASBL_BL0 = 0, /*!< BL0 : Host write to 8-bit Alias I/O port is stored in byte lane 141 0 of primary 4-byte range */ 142 MEC_BDP_BL80A_ASBL_BL1 = 1, /*!< BL1 : Host write to 8-bit Alias I/O port is stored in byte lane 143 1 of primary 4-byte range */ 144 MEC_BDP_BL80A_ASBL_BL2 = 2, /*!< BL2 : Host write to 8-bit Alias I/O port is stored in byte lane 145 2 of primary 4-byte range */ 146 MEC_BDP_BL80A_ASBL_BL3 = 3, /*!< BL3 : Host write to 8-bit Alias I/O port is stored in byte lane 147 3 of primary 4-byte range */ 148 } MEC_BDP_BL80A_ASBL_Enum; 149 150 /** @} */ /* End of group EnumValue_peripherals */ 151 152 #endif /* _MEC5_BDP_V1_H */ 153
