1 /*
2  * Copyright 2024 Microchip Technology Inc. and its subsidiaries.
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 #ifndef _MEC_ADC_API_H
7 #define _MEC_ADC_API_H
8 
9 #include <stdbool.h>
10 #include <stddef.h>
11 #include <stdint.h>
12 
13 #include "device_mec5.h"
14 #include "mec_defs.h"
15 #include "mec_retval.h"
16 
17 /* Microchip MEC5 ADC */
18 
19 /* Interfaces to any C modules */
20 #ifdef __cplusplus
21 extern "C"
22 {
23 #endif
24 
25 #define MEC_ADC_MAIN_CLK_FREQ 48000000u
26 
27 /* Default values of ADC sample clock generator.
28  * Sample clock low and high times are 8-bit values
29  * in units of MEC_ADC_MAIN_CLK_FREQ ticks.
30  * Default values produce 50% duty cycle at frequency
31  * of (MEC_ADC_SAMPLE_CLK_LIT_DFLT / 2)
32  */
33 #define MEC_ADC_SAMPLE_CLK_LIT_DFLT 1u
34 #define MEC_ADC_SAMPLE_CLK_HIT_DFLT 1u
35 
36 /* ADC warm up delay defaults to 514 ADC Sample clocks
37  * Hardware applies warm up delay when either start single
38  * or start repeat is set when the ADC is fully idle.
39  */
40 #define MEC_ADC_WARM_UP_DLY_CLKS_DFLT 514u
41 
42 /* Additional delay before the channels selected for repeat
43  * conversions are processed for the first time after the
44  * start repeat bit is set. Delay is in units of 40 us.
45  */
46 #define MEC_ADC_RPT_CYCLE_START_DLY_DFLT 0
47 
48 /* Additional delay before the channels selected for repeat
49  * conversions are processed for the second and subsequent
50  * times after the start repeat bit is set. Delay is in units of 40 us.
51  */
52 #define MEC_ADC_RPT_CYCLE_DLY_DFLT 0
53 
54 /* Internal voltage reference from the ADC voltage rail */
55 #define MEC_ADC_INTERNAL_VREF_MV 3300u
56 
57 enum mec_adc_cfg_flags {
58     MEC_ADC_CFG_SOFT_RESET_POS = 0,
59     MEC_ADC_CFG_PWR_SAVE_DIS_POS,
60     MEC_ADC_CFG_SAMPLE_TIME_POS,
61     MEC_ADC_CFG_WARM_UP_POS,
62     MEC_ADC_CFG_RPT_DELAY_POS,
63     MEC_ADC_CFG_SAR_CFG_OVR_POS,
64 };
65 
66 enum mec_adc_intr_flags {
67     MEC_ADC_SINGLE_INTR_POS = 0,
68     MEC_ADC_REPEAT_INTR_POS,
69 };
70 
71 enum mec_adc_chan_vref {
72     MEC_ADC_CHAN_VREF_PAD = 0,
73     MEC_ADC_CHAN_VREF_GPIO,
74 };
75 
76 struct mec_adc_config {
77     uint8_t flags;
78     uint8_t sample_clk_lo_time;
79     uint8_t sample_clk_hi_time;
80     uint16_t warm_up_delay;
81     uint16_t rpt_start_delay;
82     uint16_t rpt_cycle_delay;
83     uint32_t sar_config;
84 };
85 
86 int mec_hal_adc_init(struct mec_adc_regs *regs, struct mec_adc_config *cfg);
87 int mec_hal_adc_activate(struct mec_adc_regs *regs, uint8_t enable);
88 
89 int mec_hal_adc_girq_ctrl(struct mec_adc_regs *regs, uint32_t flags, uint8_t enable);
90 int mec_hal_adc_girq_status_clr(struct mec_adc_regs *regs, uint32_t flags);
91 
92 int mec_hal_adc_repeat_delay_set(struct mec_adc_regs *regs, uint16_t start_delay,
93                                  uint16_t repeat_delay);
94 int mec_hal_adc_repeat_mode_chan_set(struct mec_adc_regs *regs, uint32_t rpt_chan_bm);
95 
96 int mec_hal_adc_chan_vref_select(struct mec_adc_regs *regs, uint8_t chan_id,
97                                  enum mec_adc_chan_vref vref);
98 
99 /* Enable/disable differential input mode for ALL channels */
100 int mec_hal_adc_differential_input_enable(struct mec_adc_regs *regs, uint8_t enable);
101 
102 int mec_hal_adc_resolution_set(struct mec_adc_regs *regs, uint8_t resolution_bits);
103 
104 int mec_hal_adc_start(struct mec_adc_regs *regs, uint16_t single_chan_bm, uint16_t rpt_chan_bm);
105 
106 uint32_t mec_hal_adc_channels_done(struct mec_adc_regs *regs);
107 
108 int mec_hal_adc_status_clear(struct mec_adc_regs *regs, uint32_t flags);
109 
110 uint32_t mec_hal_adc_channel_reading(struct mec_adc_regs *regs, uint8_t channel);
111 
112 void mec_hal_adc_pm_save_disable(void);
113 void mec_hal_adc_pm_restore(void);
114 
115 #ifdef __cplusplus
116 }
117 #endif
118 
119 #endif /* #ifndef _MEC_ADC_API_H */
120