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Searched refs:MC_BASE2 (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_ddr.c496 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; in ddr_setup()
505 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x0U; in ddr_setup()
580 DDRCFG->MC_BASE2.CTRLR_INIT.CTRLR_INIT = 0x00000000U; in ddr_setup()
883 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ in ddr_setup()
885 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ in ddr_setup()
890 DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x1; in ddr_setup()
893 DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x1; in ddr_setup()
896 DDRCFG->MC_BASE2.INIT_FORCE_RESET.INIT_FORCE_RESET = 0x0; in ddr_setup()
900 DDRCFG->MC_BASE2.INIT_DISABLE_CKE.INIT_DISABLE_CKE = 0x0; in ddr_setup()
1022 DDRCFG->MC_BASE2.CTRLR_SOFT_RESET_N.CTRLR_SOFT_RESET_N =\ in ddr_setup()
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Dmss_ddr_sgmii_regs.h4365 __IO DDR_CSR_APB_MC_BASE2_TypeDef MC_BASE2; /*!< Offset: 0x4000 */ member