LIBERO_SETTING_PHY_GATE_TRAIN_DELAY (reference) in projects: hal_microchip-latest

Searched refs:LIBERO_SETTING_PHY_GATE_TRAIN_DELAY (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-latest/mpfs/boards/icicle-kit-es/fpga_design_config/ddr/
D	hw_ddrc.h	`1830 #if !defined (LIBERO_SETTING_PHY_GATE_TRAIN_DELAY) 1832 #define LIBERO_SETTING_PHY_GATE_TRAIN_DELAY 0x0000003FUL macro`
/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
D	mss_ddr.c	`4749 LIBERO_SETTING_PHY_GATE_TRAIN_DELAY; in init_ddrc()`