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Searched refs:LIBERO_SETTING_DDR_SSCG_REG_3 (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-latest/mpfs/boards/icicle-kit-es/fpga_design_config/clocks/
Dhw_clk_ddr_pll.h178 #if !defined (LIBERO_SETTING_DDR_SSCG_REG_3)
180 #define LIBERO_SETTING_DDR_SSCG_REG_3 0x00000001UL macro
/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_pll.c539 MSS_SCB_DDR_PLL->SSCG_REG_3 = LIBERO_SETTING_DDR_SSCG_REG_3; in ddr_pll_config()