Home
last modified time | relevance | path

Searched refs:LIBERO_SETTING_DDR_SSCG_REG_0 (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-latest/mpfs/boards/icicle-kit-es/fpga_design_config/clocks/
Dhw_clk_ddr_pll.h156 #if !defined (LIBERO_SETTING_DDR_SSCG_REG_0)
158 #define LIBERO_SETTING_DDR_SSCG_REG_0 0x00000000UL macro
/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_pll.c535 MSS_SCB_DDR_PLL->SSCG_REG_0 = LIBERO_SETTING_DDR_SSCG_REG_0; in ddr_pll_config()