1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_CMCC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_CMCC_COMPONENT_FIXUP_H_ 9 10 /* -------- CMCC_TYPE : (CMCC Offset: 0x00) ( R/ 32) Cache Type Register -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t :1; /*!< bit: 0 Reserved */ 15 uint32_t DCGCLK:1; /*!< bit: 1 dynamic Clock Gating supported */ /* MDS */ 16 uint32_t :2; /*!< bit: 2.. 3 Reserved */ 17 uint32_t RRP:1; /*!< bit: 4 Round Robin Policy supported */ 18 uint32_t WAYNUM:2; /*!< bit: 5.. 6 Number of Way */ 19 uint32_t LCKDOWN:1; /*!< bit: 7 Lock Down supported */ 20 uint32_t CSIZE:3; /*!< bit: 8..10 Cache Size */ 21 uint32_t CLSIZE:3; /*!< bit: 11..13 Cache Line Size */ 22 uint32_t :18; /*!< bit: 14..31 Reserved */ 23 } bit; /*!< Structure used for bit access */ 24 uint32_t reg; /*!< Type used for register access */ 25 } CMCC_TYPE_Type; 26 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 27 28 /* -------- CMCC_CFG : (CMCC Offset: 0x04) (R/W 32) Cache Configuration Register -------- */ 29 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 30 typedef union { 31 struct { 32 uint32_t :1; /*!< bit: 0 Reserved */ 33 uint32_t ICDIS:1; /*!< bit: 1 Instruction Cache Disable */ 34 uint32_t DCDIS:1; /*!< bit: 2 Data Cache Disable */ 35 uint32_t :1; /*!< bit: 3 Reserved */ 36 uint32_t CSIZESW:3; /*!< bit: 4.. 6 Cache size configured by software */ 37 uint32_t :25; /*!< bit: 7..31 Reserved */ 38 } bit; /*!< Structure used for bit access */ 39 uint32_t reg; /*!< Type used for register access */ 40 } CMCC_CFG_Type; 41 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 42 43 /* -------- CMCC_CTRL : (CMCC Offset: 0x08) ( /W 32) Cache Control Register -------- */ 44 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 45 typedef union { 46 struct { 47 uint32_t CEN:1; /*!< bit: 0 Cache Controller Enable */ 48 uint32_t :31; /*!< bit: 1..31 Reserved */ 49 } bit; /*!< Structure used for bit access */ 50 uint32_t reg; /*!< Type used for register access */ 51 } CMCC_CTRL_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 /* -------- CMCC_SR : (CMCC Offset: 0x0C) ( R/ 32) Cache Status Register -------- */ 55 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 56 typedef union { 57 struct { 58 uint32_t CSTS:1; /*!< bit: 0 Cache Controller Status */ 59 uint32_t :31; /*!< bit: 1..31 Reserved */ 60 } bit; /*!< Structure used for bit access */ 61 uint32_t reg; /*!< Type used for register access */ 62 } CMCC_SR_Type; 63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 64 65 /* -------- CMCC_LCKWAY : (CMCC Offset: 0x10) (R/W 32) Cache Lock per Way Register -------- */ 66 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 67 typedef union { 68 struct { 69 uint32_t LCKWAY:4; /*!< bit: 0.. 3 Lockdown way Register */ 70 uint32_t :28; /*!< bit: 4..31 Reserved */ 71 } bit; /*!< Structure used for bit access */ 72 uint32_t reg; /*!< Type used for register access */ 73 } CMCC_LCKWAY_Type; 74 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 75 76 /* -------- CMCC_MAINT0 : (CMCC Offset: 0x20) ( /W 32) Cache Maintenance Register 0 -------- */ 77 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 78 typedef union { 79 struct { 80 uint32_t INVALL:1; /*!< bit: 0 Cache Controller invalidate All */ 81 uint32_t :31; /*!< bit: 1..31 Reserved */ 82 } bit; /*!< Structure used for bit access */ 83 uint32_t reg; /*!< Type used for register access */ 84 } CMCC_MAINT0_Type; 85 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 86 /* -------- CMCC_MAINT1 : (CMCC Offset: 0x24) ( /W 32) Cache Maintenance Register 1 -------- */ 87 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 88 typedef union { 89 struct { 90 uint32_t :4; /*!< bit: 0.. 3 Reserved */ 91 uint32_t INDEX:8; /*!< bit: 4..11 Invalidate Index */ 92 uint32_t :16; /*!< bit: 12..27 Reserved */ 93 uint32_t WAY:4; /*!< bit: 28..31 Invalidate Way */ 94 } bit; /*!< Structure used for bit access */ 95 uint32_t reg; /*!< Type used for register access */ 96 } CMCC_MAINT1_Type; 97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 /* -------- CMCC_MCFG : (CMCC Offset: 0x28) (R/W 32) Cache Monitor Configuration Register -------- */ 100 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 101 typedef union { 102 struct { 103 uint32_t MODE:2; /*!< bit: 0.. 1 Cache Controller Monitor Counter Mode */ 104 uint32_t :30; /*!< bit: 2..31 Reserved */ 105 } bit; /*!< Structure used for bit access */ 106 uint32_t reg; /*!< Type used for register access */ 107 } CMCC_MCFG_Type; 108 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 109 110 /* -------- CMCC_MEN : (CMCC Offset: 0x2C) (R/W 32) Cache Monitor Enable Register -------- */ 111 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 112 typedef union { 113 struct { 114 uint32_t MENABLE:1; /*!< bit: 0 Cache Controller Monitor Enable */ 115 uint32_t :31; /*!< bit: 1..31 Reserved */ 116 } bit; /*!< Structure used for bit access */ 117 uint32_t reg; /*!< Type used for register access */ 118 } CMCC_MEN_Type; 119 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 120 121 /* -------- CMCC_MCTRL : (CMCC Offset: 0x30) ( /W 32) Cache Monitor Control Register -------- */ 122 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 123 typedef union { 124 struct { 125 uint32_t SWRST:1; /*!< bit: 0 Cache Controller Software Reset */ 126 uint32_t :31; /*!< bit: 1..31 Reserved */ 127 } bit; /*!< Structure used for bit access */ 128 uint32_t reg; /*!< Type used for register access */ 129 } CMCC_MCTRL_Type; 130 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 131 132 /* -------- CMCC_MSR : (CMCC Offset: 0x34) ( R/ 32) Cache Monitor Status Register -------- */ 133 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 134 typedef union { 135 struct { 136 uint32_t EVENT_CNT:32; /*!< bit: 0..31 Monitor Event Counter */ 137 } bit; /*!< Structure used for bit access */ 138 uint32_t reg; /*!< Type used for register access */ 139 } CMCC_MSR_Type; 140 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 141 142 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 143 typedef struct { 144 __I CMCC_TYPE_Type TYPE; /**< \brief Offset: 0x00 (R/ 32) Cache Type Register */ 145 __IO CMCC_CFG_Type CFG; /**< \brief Offset: 0x04 (R/W 32) Cache Configuration Register */ 146 __O CMCC_CTRL_Type CTRL; /**< \brief Offset: 0x08 ( /W 32) Cache Control Register */ 147 __I CMCC_SR_Type SR; /**< \brief Offset: 0x0C (R/ 32) Cache Status Register */ 148 __IO CMCC_LCKWAY_Type LCKWAY; /**< \brief Offset: 0x10 (R/W 32) Cache Lock per Way Register */ 149 RoReg8 Reserved1[0xC]; 150 __O CMCC_MAINT0_Type MAINT0; /**< \brief Offset: 0x20 ( /W 32) Cache Maintenance Register 0 */ 151 __O CMCC_MAINT1_Type MAINT1; /**< \brief Offset: 0x24 ( /W 32) Cache Maintenance Register 1 */ 152 __IO CMCC_MCFG_Type MCFG; /**< \brief Offset: 0x28 (R/W 32) Cache Monitor Configuration Register */ 153 __IO CMCC_MEN_Type MEN; /**< \brief Offset: 0x2C (R/W 32) Cache Monitor Enable Register */ 154 __O CMCC_MCTRL_Type MCTRL; /**< \brief Offset: 0x30 ( /W 32) Cache Monitor Control Register */ 155 __I CMCC_MSR_Type MSR; /**< \brief Offset: 0x34 (R/ 32) Cache Monitor Status Register */ 156 } Cmcc; 157 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 158 159 #endif /* _MICROCHIP_PIC32CXSG_CMCC_COMPONENT_FIXUP_H_ */ 160
