Home
last modified time | relevance | path

Searched refs:INTR_EN (Results 1 – 5 of 5) sorted by relevance

/hal_microchip-latest/mec5/drivers/
Dmec_eeprom.c43 regs->INTR_EN = 0; in mec_hal_eeprom_init()
60 regs->INTR_EN |= MEC_BIT(MEC_EEPROM_CTRL_INTR_EN_XFR_DONE_Pos); in mec_hal_eeprom_init()
63 regs->INTR_EN |= MEC_BIT(MEC_EEPROM_CTRL_INTR_EN_ERROR_Pos); in mec_hal_eeprom_init()
165 regs->INTR_EN = (regs->INTR_EN & (uint32_t)~msk) | rval; in mec_hal_eeprom_intr_en()
Dmec_i3c_pvt.c45 regs->INTR_EN = mask; in _i3c_intr_sts_enable()
55 regs->INTR_EN |= sbit_IBI_THLD_STS; in _i3c_intr_IBI_enable()
67 regs->INTR_EN &= (uint32_t)~sbit_IBI_THLD_STS; in _i3c_intr_IBI_disable()
79 regs->INTR_EN |= sbit_TX_THLD_STS; in _i3c_intr_thresholds_tx_enable()
91 regs->INTR_EN &= (uint32_t)~sbit_TX_THLD_STS; in _i3c_intr_thresholds_tx_disable()
103 regs->INTR_EN |= sbit_RX_THLD_STS; in _i3c_intr_thresholds_rx_enable()
115 regs->INTR_EN &= (uint32_t)~sbit_RX_THLD_STS; in _i3c_intr_thresholds_rx_disable()
/hal_microchip-latest/mec5/devices/common/
Dmec5_eeprom_ctrl_v1.h21 …__IOM uint32_t INTR_EN; /*!< (@ 0x0000000C) Interrupt enable register … member
Dmec5_i3c_host_v2.h35 …__IOM uint32_t INTR_EN; /*!< (@ 0x00000040) Interrupt enable register … member
Dmec5_i3c_sec_v2.h35 …__IOM uint32_t INTR_EN; /*!< (@ 0x00000040) Interrupt enable register … member