1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_PDEC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_PDEC_COMPONENT_FIXUP_H_ 9 10 /* -------- PDEC_CTRLA : (PDEC Offset: 0x00) (R/W 32) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint32_t MODE:2; /*!< bit: 2.. 3 Operation Mode */ 17 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 18 uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 19 uint32_t :1; /*!< bit: 7 Reserved */ 20 uint32_t CONF:3; /*!< bit: 8..10 PDEC Configuration */ 21 uint32_t ALOCK:1; /*!< bit: 11 Auto Lock */ 22 uint32_t :2; /*!< bit: 12..13 Reserved */ 23 uint32_t SWAP:1; /*!< bit: 14 PDEC Phase A and B Swap */ 24 uint32_t PEREN:1; /*!< bit: 15 Period Enable */ 25 uint32_t PINEN0:1; /*!< bit: 16 PDEC Input From Pin 0 Enable */ 26 uint32_t PINEN1:1; /*!< bit: 17 PDEC Input From Pin 1 Enable */ 27 uint32_t PINEN2:1; /*!< bit: 18 PDEC Input From Pin 2 Enable */ 28 uint32_t :1; /*!< bit: 19 Reserved */ 29 uint32_t PINVEN0:1; /*!< bit: 20 IO Pin 0 Invert Enable */ 30 uint32_t PINVEN1:1; /*!< bit: 21 IO Pin 1 Invert Enable */ 31 uint32_t PINVEN2:1; /*!< bit: 22 IO Pin 2 Invert Enable */ 32 uint32_t :1; /*!< bit: 23 Reserved */ 33 uint32_t ANGULAR:3; /*!< bit: 24..26 Angular Counter Length */ 34 uint32_t :1; /*!< bit: 27 Reserved */ 35 uint32_t MAXCMP:4; /*!< bit: 28..31 Maximum Consecutive Missing Pulses */ 36 } bit; /*!< Structure used for bit access */ 37 struct { 38 uint32_t :16; /*!< bit: 0..15 Reserved */ 39 uint32_t PINEN:3; /*!< bit: 16..18 PDEC Input From Pin x Enable */ 40 uint32_t :1; /*!< bit: 19 Reserved */ 41 uint32_t PINVEN:3; /*!< bit: 20..22 IO Pin x Invert Enable */ 42 uint32_t :9; /*!< bit: 23..31 Reserved */ 43 } vec; /*!< Structure used for vec access */ 44 uint32_t reg; /*!< Type used for register access */ 45 } PDEC_CTRLA_Type; 46 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 47 48 /* -------- PDEC_CTRLBCLR : (PDEC Offset: 0x04) (R/W 8) Control B Clear -------- */ 49 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 50 typedef union { 51 struct { 52 uint8_t :1; /*!< bit: 0 Reserved */ 53 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 54 uint8_t :3; /*!< bit: 2.. 4 Reserved */ 55 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ 56 } bit; /*!< Structure used for bit access */ 57 uint8_t reg; /*!< Type used for register access */ 58 } PDEC_CTRLBCLR_Type; 59 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 60 61 /* -------- PDEC_CTRLBSET : (PDEC Offset: 0x05) (R/W 8) Control B Set -------- */ 62 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 63 typedef union { 64 struct { 65 uint8_t :1; /*!< bit: 0 Reserved */ 66 uint8_t LUPD:1; /*!< bit: 1 Lock Update */ 67 uint8_t :3; /*!< bit: 2.. 4 Reserved */ 68 uint8_t CMD:3; /*!< bit: 5.. 7 Command */ 69 } bit; /*!< Structure used for bit access */ 70 uint8_t reg; /*!< Type used for register access */ 71 } PDEC_CTRLBSET_Type; 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 73 74 /* -------- PDEC_EVCTRL : (PDEC Offset: 0x06) (R/W 16) Event Control -------- */ 75 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 76 typedef union { 77 struct { 78 uint16_t EVACT:2; /*!< bit: 0.. 1 Event Action */ 79 uint16_t EVINV:3; /*!< bit: 2.. 4 Inverted Event Input Enable */ 80 uint16_t EVEI:3; /*!< bit: 5.. 7 Event Input Enable */ 81 uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Output Event Enable */ 82 uint16_t ERREO:1; /*!< bit: 9 Error Output Event Enable */ 83 uint16_t DIREO:1; /*!< bit: 10 Direction Output Event Enable */ 84 uint16_t VLCEO:1; /*!< bit: 11 Velocity Output Event Enable */ 85 uint16_t MCEO0:1; /*!< bit: 12 Match Channel 0 Event Output Enable */ 86 uint16_t MCEO1:1; /*!< bit: 13 Match Channel 1 Event Output Enable */ 87 uint16_t :2; /*!< bit: 14..15 Reserved */ 88 } bit; /*!< Structure used for bit access */ 89 struct { 90 uint16_t :12; /*!< bit: 0..11 Reserved */ 91 uint16_t MCEO:2; /*!< bit: 12..13 Match Channel x Event Output Enable */ 92 uint16_t :2; /*!< bit: 14..15 Reserved */ 93 } vec; /*!< Structure used for vec access */ 94 uint16_t reg; /*!< Type used for register access */ 95 } PDEC_EVCTRL_Type; 96 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 97 98 /* -------- PDEC_INTENCLR : (PDEC Offset: 0x08) (R/W 8) Interrupt Enable Clear -------- */ 99 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 100 typedef union { 101 struct { 102 uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Disable */ 103 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Disable */ 104 uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Disable */ 105 uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Disable */ 106 uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Disable */ 107 uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Disable */ 108 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 109 } bit; /*!< Structure used for bit access */ 110 struct { 111 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 112 uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Disable */ 113 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 114 } vec; /*!< Structure used for vec access */ 115 uint8_t reg; /*!< Type used for register access */ 116 } PDEC_INTENCLR_Type; 117 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 118 119 /* -------- PDEC_INTENSET : (PDEC Offset: 0x09) (R/W 8) Interrupt Enable Set -------- */ 120 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 121 typedef union { 122 struct { 123 uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow Interrupt Enable */ 124 uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */ 125 uint8_t DIR:1; /*!< bit: 2 Direction Interrupt Enable */ 126 uint8_t VLC:1; /*!< bit: 3 Velocity Interrupt Enable */ 127 uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match Enable */ 128 uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match Enable */ 129 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 130 } bit; /*!< Structure used for bit access */ 131 struct { 132 uint8_t :4; /*!< bit: 0.. 3 Reserved */ 133 uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match Enable */ 134 uint8_t :2; /*!< bit: 6.. 7 Reserved */ 135 } vec; /*!< Structure used for vec access */ 136 uint8_t reg; /*!< Type used for register access */ 137 } PDEC_INTENSET_Type; 138 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 139 140 /* -------- PDEC_INTFLAG : (PDEC Offset: 0x0A) (R/W 8) Interrupt Flag Status and Clear -------- */ 141 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 142 typedef union { // __I to avoid read-modify-write on write-to-clear register 143 struct { 144 __I uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow */ 145 __I uint8_t ERR:1; /*!< bit: 1 Error */ 146 __I uint8_t DIR:1; /*!< bit: 2 Direction Change */ 147 __I uint8_t VLC:1; /*!< bit: 3 Velocity */ 148 __I uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match */ 149 __I uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match */ 150 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 151 } bit; /*!< Structure used for bit access */ 152 struct { 153 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */ 154 __I uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match */ 155 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */ 156 } vec; /*!< Structure used for vec access */ 157 uint8_t reg; /*!< Type used for register access */ 158 } PDEC_INTFLAG_Type; 159 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 160 161 /* -------- PDEC_STATUS : (PDEC Offset: 0x0C) (R/W 16) Status -------- */ 162 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 163 typedef union { 164 struct { 165 uint16_t QERR:1; /*!< bit: 0 Quadrature Error Flag */ 166 uint16_t IDXERR:1; /*!< bit: 1 Index Error Flag */ 167 uint16_t MPERR:1; /*!< bit: 2 Missing Pulse Error flag */ 168 uint16_t :1; /*!< bit: 3 Reserved */ 169 uint16_t WINERR:1; /*!< bit: 4 Window Error Flag */ 170 uint16_t HERR:1; /*!< bit: 5 Hall Error Flag */ 171 uint16_t STOP:1; /*!< bit: 6 Stop */ 172 uint16_t DIR:1; /*!< bit: 7 Direction Status Flag */ 173 uint16_t PRESCBUFV:1; /*!< bit: 8 Prescaler Buffer Valid */ 174 uint16_t FILTERBUFV:1; /*!< bit: 9 Filter Buffer Valid */ 175 uint16_t :2; /*!< bit: 10..11 Reserved */ 176 uint16_t CCBUFV0:1; /*!< bit: 12 Compare Channel 0 Buffer Valid */ 177 uint16_t CCBUFV1:1; /*!< bit: 13 Compare Channel 1 Buffer Valid */ 178 uint16_t :2; /*!< bit: 14..15 Reserved */ 179 } bit; /*!< Structure used for bit access */ 180 struct { 181 uint16_t :12; /*!< bit: 0..11 Reserved */ 182 uint16_t CCBUFV:2; /*!< bit: 12..13 Compare Channel x Buffer Valid */ 183 uint16_t :2; /*!< bit: 14..15 Reserved */ 184 } vec; /*!< Structure used for vec access */ 185 uint16_t reg; /*!< Type used for register access */ 186 } PDEC_STATUS_Type; 187 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 188 189 /* -------- PDEC_DBGCTRL : (PDEC Offset: 0x0F) (R/W 8) Debug Control -------- */ 190 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 191 typedef union { 192 struct { 193 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */ 194 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 195 } bit; /*!< Structure used for bit access */ 196 uint8_t reg; /*!< Type used for register access */ 197 } PDEC_DBGCTRL_Type; 198 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 199 200 /* -------- PDEC_SYNCBUSY : (PDEC Offset: 0x10) ( R/ 32) Synchronization Status -------- */ 201 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 202 typedef union { 203 struct { 204 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy */ 205 uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy */ 206 uint32_t CTRLB:1; /*!< bit: 2 Control B Synchronization Busy */ 207 uint32_t STATUS:1; /*!< bit: 3 Status Synchronization Busy */ 208 uint32_t PRESC:1; /*!< bit: 4 Prescaler Synchronization Busy */ 209 uint32_t FILTER:1; /*!< bit: 5 Filter Synchronization Busy */ 210 uint32_t COUNT:1; /*!< bit: 6 Count Synchronization Busy */ 211 uint32_t CC0:1; /*!< bit: 7 Compare Channel 0 Synchronization Busy */ 212 uint32_t CC1:1; /*!< bit: 8 Compare Channel 1 Synchronization Busy */ 213 uint32_t :23; /*!< bit: 9..31 Reserved */ 214 } bit; /*!< Structure used for bit access */ 215 struct { 216 uint32_t :7; /*!< bit: 0.. 6 Reserved */ 217 uint32_t CC:2; /*!< bit: 7.. 8 Compare Channel x Synchronization Busy */ 218 uint32_t :23; /*!< bit: 9..31 Reserved */ 219 } vec; /*!< Structure used for vec access */ 220 uint32_t reg; /*!< Type used for register access */ 221 } PDEC_SYNCBUSY_Type; 222 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 223 /* -------- PDEC_PRESC : (PDEC Offset: 0x14) (R/W 8) Prescaler Value -------- */ 224 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 225 typedef union { 226 struct { 227 uint8_t PRESC:4; /*!< bit: 0.. 3 Prescaler Value */ 228 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 229 } bit; /*!< Structure used for bit access */ 230 uint8_t reg; /*!< Type used for register access */ 231 } PDEC_PRESC_Type; 232 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 233 234 /* -------- PDEC_FILTER : (PDEC Offset: 0x15) (R/W 8) Filter Value -------- */ 235 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 236 typedef union { 237 struct { 238 uint8_t FILTER:8; /*!< bit: 0.. 7 Filter Value */ 239 } bit; /*!< Structure used for bit access */ 240 uint8_t reg; /*!< Type used for register access */ 241 } PDEC_FILTER_Type; 242 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 243 244 /* -------- PDEC_PRESCBUF : (PDEC Offset: 0x18) (R/W 8) Prescaler Buffer Value -------- */ 245 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 246 typedef union { 247 struct { 248 uint8_t PRESCBUF:4; /*!< bit: 0.. 3 Prescaler Buffer Value */ 249 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 250 } bit; /*!< Structure used for bit access */ 251 uint8_t reg; /*!< Type used for register access */ 252 } PDEC_PRESCBUF_Type; 253 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 254 255 /* -------- PDEC_FILTERBUF : (PDEC Offset: 0x19) (R/W 8) Filter Buffer Value -------- */ 256 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 257 typedef union { 258 struct { 259 uint8_t FILTERBUF:8; /*!< bit: 0.. 7 Filter Buffer Value */ 260 } bit; /*!< Structure used for bit access */ 261 uint8_t reg; /*!< Type used for register access */ 262 } PDEC_FILTERBUF_Type; 263 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 264 265 /* -------- PDEC_COUNT : (PDEC Offset: 0x1C) (R/W 32) Counter Value -------- */ 266 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 267 typedef union { 268 struct { 269 uint32_t COUNT:16; /*!< bit: 0..15 Counter Value */ 270 uint32_t :16; /*!< bit: 16..31 Reserved */ 271 } bit; /*!< Structure used for bit access */ 272 uint32_t reg; /*!< Type used for register access */ 273 } PDEC_COUNT_Type; 274 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 275 276 /* -------- PDEC_CC : (PDEC Offset: 0x20) (R/W 32) Channel n Compare Value -------- */ 277 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 278 typedef union { 279 struct { 280 uint32_t CC:16; /*!< bit: 0..15 Channel Compare Value */ 281 uint32_t :16; /*!< bit: 16..31 Reserved */ 282 } bit; /*!< Structure used for bit access */ 283 uint32_t reg; /*!< Type used for register access */ 284 } PDEC_CC_Type; 285 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 286 287 /* -------- PDEC_CCBUF : (PDEC Offset: 0x30) (R/W 32) Channel Compare Buffer Value -------- */ 288 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 289 typedef union { 290 struct { 291 uint32_t CCBUF:16; /*!< bit: 0..15 Channel Compare Buffer Value */ 292 uint32_t :16; /*!< bit: 16..31 Reserved */ 293 } bit; /*!< Structure used for bit access */ 294 uint32_t reg; /*!< Type used for register access */ 295 } PDEC_CCBUF_Type; 296 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 297 298 /** \brief PDEC hardware registers */ 299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 300 typedef struct { 301 __IO PDEC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 32) Control A */ 302 __IO PDEC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */ 303 __IO PDEC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */ 304 __IO PDEC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x06 (R/W 16) Event Control */ 305 __IO PDEC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear */ 306 __IO PDEC_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set */ 307 __IO PDEC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Status and Clear */ 308 RoReg8 Reserved1[0x1]; 309 __IO PDEC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/W 16) Status */ 310 RoReg8 Reserved2[0x1]; 311 __IO PDEC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0F (R/W 8) Debug Control */ 312 __I PDEC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x10 (R/ 32) Synchronization Status */ 313 __IO PDEC_PRESC_Type PRESC; /**< \brief Offset: 0x14 (R/W 8) Prescaler Value */ 314 __IO PDEC_FILTER_Type FILTER; /**< \brief Offset: 0x15 (R/W 8) Filter Value */ 315 RoReg8 Reserved3[0x2]; 316 __IO PDEC_PRESCBUF_Type PRESCBUF; /**< \brief Offset: 0x18 (R/W 8) Prescaler Buffer Value */ 317 __IO PDEC_FILTERBUF_Type FILTERBUF; /**< \brief Offset: 0x19 (R/W 8) Filter Buffer Value */ 318 RoReg8 Reserved4[0x2]; 319 __IO PDEC_COUNT_Type COUNT; /**< \brief Offset: 0x1C (R/W 32) Counter Value */ 320 __IO PDEC_CC_Type CC[2]; /**< \brief Offset: 0x20 (R/W 32) Channel n Compare Value */ 321 RoReg8 Reserved5[0x8]; 322 __IO PDEC_CCBUF_Type CCBUF[2]; /**< \brief Offset: 0x30 (R/W 32) Channel Compare Buffer Value */ 323 } Pdec; 324 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 325 326 #endif /* _MICROCHIP_PIC32CXSG_PDEC_COMPONENT_FIXUP_H_ */ 327
