Searched refs:GIRQ (Results 1 – 8 of 8) sorted by relevance
80 ensts |= ((MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].SOURCE >> 7) & 0x2u); in mec_hal_espi_vw_en_status()87 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].SOURCE = MEC_BIT(MEC_ESPI_VW_CHEN_CHG_GIRQ19_POS); in mec_hal_espi_vw_en_status_clr()93 return (MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].RESULT in mec_hal_espi_vw_en_result()100 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].EN_SET = MEC_BIT(MEC_ESPI_VW_CHEN_CHG_GIRQ19_POS); in mec_hal_espi_vw_en_ien()102 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].EN_CLR = MEC_BIT(MEC_ESPI_VW_CHEN_CHG_GIRQ19_POS); in mec_hal_espi_vw_en_ien()177 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_SET = MEC_BIT(bitpos); in mec_hal_espi_vw_ct_girq_ctrl()179 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_CLR = MEC_BIT(bitpos); in mec_hal_espi_vw_ct_girq_ctrl()184 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_SET = MEC_BIT(bitpos); in mec_hal_espi_vw_ct_girq_ctrl()186 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_CLR = MEC_BIT(bitpos); in mec_hal_espi_vw_ct_girq_ctrl()196 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_SET = UINT32_MAX; in mec_hal_espi_vw_ct_girq_ctrl_all()[all …]
322 MEC_ECIA0->GIRQ[0].EN_SET = UINT32_MAX; in enable_girq_direct_bitmap()403 MEC_ECIA0->GIRQ[i].EN_CLR = UINT32_MAX; in mec_hal_ecia_init()404 MEC_ECIA0->GIRQ[i].SOURCE = UINT32_MAX; in mec_hal_ecia_init()453 MEC_ECIA0->GIRQ[gidx].EN_SET = bitmap; in mec_hal_girq_bm_en()455 MEC_ECIA0->GIRQ[gidx].EN_CLR = bitmap; in mec_hal_girq_bm_en()474 MEC_ECIA0->GIRQ[gidx].SOURCE = bitmap; in mec_hal_girq_bm_clr_src()487 return MEC_ECIA0->GIRQ[gidx].SOURCE; in mec_hal_girq_source_get()498 return MEC_ECIA0->GIRQ[gidx].RESULT; in mec_hal_girq_result_get()519 MEC_ECIA0->GIRQ[gidx].EN_SET = MEC_BIT(gpos); in mec_hal_girq_ctrl()521 MEC_ECIA0->GIRQ[gidx].EN_CLR = MEC_BIT(gpos); in mec_hal_girq_ctrl()[all …]
1078 MEC_ECIA0->GIRQ[girq_idx].EN_SET = MEC_BIT(port_pin_pos); in mec_hal_gpio_port_pin_ia_enable()1080 MEC_ECIA0->GIRQ[girq_idx].EN_CLR = MEC_BIT(port_pin_pos); in mec_hal_gpio_port_pin_ia_enable()1107 MEC_ECIA0->GIRQ[girq_idx].SOURCE = MEC_BIT(port_pin_pos & 0x1fu); in mec_hal_gpio_port_pin_ia_status_clear()1133 MEC_ECIA0->GIRQ[girq_idx].SOURCE = mask; in mec_hal_gpio_port_ia_status_clr_mask()1146 *result = MEC_ECIA0->GIRQ[girq_idx].RESULT; in mec_hal_gpio_port_ia_result()
347 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_SET = 0x0fffffffu; in mec_hal_espi_init()348 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_SET = 0x0000ffffu; in mec_hal_espi_init()387 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].EN_SET = girq_en; in mec_hal_espi_init()
184 MEC_ECIA0->GIRQ[MEC_DMAC_GIRQ_IDX].SOURCE = chanmsk; in mec_hal_dma_chan_ia_status_clr_mask()314 MEC_ECIA0->GIRQ[MEC_DMAC_GIRQ_IDX].SOURCE = MEC_BIT(chan); in mec_hal_dma_chan_intr_status_clr()
36 …__IOM MEC_GIRQS_Type GIRQ[19]; /*!< (@ 0x00000000) ECIA GIRQ … member
17 Add missing eSPI Virtual Wires groups 8 - 10 GIRQ definitions.
795 GIRQ_Type GIRQ[19]; member
