1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_GCLK_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_GCLK_COMPONENT_FIXUP_H_ 9 10 /* -------- GCLK_CTRLA : (GCLK Offset: 0x00) (R/W 8) Control -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 16 } bit; /*!< Structure used for bit access */ 17 uint8_t reg; /*!< Type used for register access */ 18 } GCLK_CTRLA_Type; 19 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 20 21 /* -------- GCLK_SYNCBUSY : (GCLK Offset: 0x04) ( R/ 32) Synchronization Busy -------- */ 22 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 23 typedef union { 24 struct { 25 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchroniation Busy bit */ 26 uint32_t :1; /*!< bit: 1 Reserved */ 27 uint32_t GENCTRL0:1; /*!< bit: 2 Generic Clock Generator Control 0 Synchronization Busy bits */ 28 uint32_t GENCTRL1:1; /*!< bit: 3 Generic Clock Generator Control 1 Synchronization Busy bits */ 29 uint32_t GENCTRL2:1; /*!< bit: 4 Generic Clock Generator Control 2 Synchronization Busy bits */ 30 uint32_t GENCTRL3:1; /*!< bit: 5 Generic Clock Generator Control 3 Synchronization Busy bits */ 31 uint32_t GENCTRL4:1; /*!< bit: 6 Generic Clock Generator Control 4 Synchronization Busy bits */ 32 uint32_t GENCTRL5:1; /*!< bit: 7 Generic Clock Generator Control 5 Synchronization Busy bits */ 33 uint32_t GENCTRL6:1; /*!< bit: 8 Generic Clock Generator Control 6 Synchronization Busy bits */ 34 uint32_t GENCTRL7:1; /*!< bit: 9 Generic Clock Generator Control 7 Synchronization Busy bits */ 35 uint32_t GENCTRL8:1; /*!< bit: 10 Generic Clock Generator Control 8 Synchronization Busy bits */ 36 uint32_t GENCTRL9:1; /*!< bit: 11 Generic Clock Generator Control 9 Synchronization Busy bits */ 37 uint32_t GENCTRL10:1; /*!< bit: 12 Generic Clock Generator Control 10 Synchronization Busy bits */ 38 uint32_t GENCTRL11:1; /*!< bit: 13 Generic Clock Generator Control 11 Synchronization Busy bits */ 39 uint32_t :18; /*!< bit: 14..31 Reserved */ 40 } bit; /*!< Structure used for bit access */ 41 struct { 42 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 43 uint32_t GENCTRL:12; /*!< bit: 2..13 Generic Clock Generator Control x Synchronization Busy bits */ 44 uint32_t :18; /*!< bit: 14..31 Reserved */ 45 } vec; /*!< Structure used for vec access */ 46 uint32_t reg; /*!< Type used for register access */ 47 } GCLK_SYNCBUSY_Type; 48 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 49 50 #define GCLK_SYNCBUSY_OFFSET 0x04 /**< \brief (GCLK_SYNCBUSY offset) Synchronization Busy */ 51 52 /* -------- GCLK_GENCTRL : (GCLK Offset: 0x20) (R/W 32) Generic Clock Generator Control -------- */ 53 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 54 typedef union { 55 struct { 56 uint32_t SRC:4; /*!< bit: 0.. 3 Source Select */ 57 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 58 uint32_t GENEN:1; /*!< bit: 8 Generic Clock Generator Enable */ 59 uint32_t IDC:1; /*!< bit: 9 Improve Duty Cycle */ 60 uint32_t OOV:1; /*!< bit: 10 Output Off Value */ 61 uint32_t OE:1; /*!< bit: 11 Output Enable */ 62 uint32_t DIVSEL:1; /*!< bit: 12 Divide Selection */ 63 uint32_t RUNSTDBY:1; /*!< bit: 13 Run in Standby */ 64 uint32_t :2; /*!< bit: 14..15 Reserved */ 65 uint32_t DIV:16; /*!< bit: 16..31 Division Factor */ 66 } bit; /*!< Structure used for bit access */ 67 uint32_t reg; /*!< Type used for register access */ 68 } GCLK_GENCTRL_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 /* -------- GCLK_PCHCTRL : (GCLK Offset: 0x80) (R/W 32) Peripheral Clock Control -------- */ 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 typedef union { 74 struct { 75 uint32_t GEN:4; /*!< bit: 0.. 3 Generic Clock Generator */ 76 uint32_t :2; /*!< bit: 4.. 5 Reserved */ 77 uint32_t CHEN:1; /*!< bit: 6 Channel Enable */ 78 uint32_t WRTLOCK:1; /*!< bit: 7 Write Lock */ 79 uint32_t :24; /*!< bit: 8..31 Reserved */ 80 } bit; /*!< Structure used for bit access */ 81 uint32_t reg; /*!< Type used for register access */ 82 } GCLK_PCHCTRL_Type; 83 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 84 85 #define GCLK_PCHCTRL_CHEN_BIT_MASK ((uint32_t)(0x1) << GCLK_PCHCTRL_CHEN_Pos) 86 87 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 88 typedef struct { 89 __IO GCLK_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control */ 90 RoReg8 Reserved1[0x03]; 91 __I GCLK_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */ 92 RoReg8 Reserved2[0x18]; 93 __IO GCLK_GENCTRL_Type GENCTRL[12]; /**< \brief Offset: 0x20 (R/W 32) Generic Clock Generator Control */ 94 RoReg8 Reserved3[0x30]; 95 __IO GCLK_PCHCTRL_Type PCHCTRL[48]; /**< \brief Offset: 0x80 (R/W 32) Peripheral Clock Control */ 96 } Gclk; 97 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 98 99 #endif /* _MICROCHIP_PIC32CXSG_GCLK_COMPONENT_FIXUP_H_ */ 100
