1 /******************************************************************************* 2 * Copyright 2020 Microchip Corporation. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Register bit offsets and masks definitions for PolarFire SoC MSS MAC. 7 * 8 */ 9 #ifndef MSS_ETHERNET_MAC_REGS_H_ 10 #define MSS_ETHERNET_MAC_REGS_H_ 11 12 #ifdef __cplusplus 13 extern "C" { 14 #endif 15 16 #define BIT_31 ((uint32_t)(0x80000000UL)) 17 #define BIT_30 ((uint32_t)(0x40000000UL)) 18 #define BIT_29 ((uint32_t)(0x20000000UL)) 19 #define BIT_28 ((uint32_t)(0x10000000UL)) 20 #define BIT_27 ((uint32_t)(0x08000000UL)) 21 #define BIT_26 ((uint32_t)(0x04000000UL)) 22 #define BIT_25 ((uint32_t)(0x02000000UL)) 23 #define BIT_24 ((uint32_t)(0x01000000UL)) 24 #define BIT_23 ((uint32_t)(0x00800000UL)) 25 #define BIT_22 ((uint32_t)(0x00400000UL)) 26 #define BIT_21 ((uint32_t)(0x00200000UL)) 27 #define BIT_20 ((uint32_t)(0x00100000UL)) 28 #define BIT_19 ((uint32_t)(0x00080000UL)) 29 #define BIT_18 ((uint32_t)(0x00040000UL)) 30 #define BIT_17 ((uint32_t)(0x00020000UL)) 31 #define BIT_16 ((uint32_t)(0x00010000UL)) 32 #define BIT_15 ((uint32_t)(0x00008000UL)) 33 #define BIT_14 ((uint32_t)(0x00004000UL)) 34 #define BIT_13 ((uint32_t)(0x00002000UL)) 35 #define BIT_12 ((uint32_t)(0x00001000UL)) 36 #define BIT_11 ((uint32_t)(0x00000800UL)) 37 #define BIT_10 ((uint32_t)(0x00000400UL)) 38 #define BIT_09 ((uint32_t)(0x00000200UL)) 39 #define BIT_08 ((uint32_t)(0x00000100UL)) 40 #define BIT_07 ((uint32_t)(0x00000080UL)) 41 #define BIT_06 ((uint32_t)(0x00000040UL)) 42 #define BIT_05 ((uint32_t)(0x00000020UL)) 43 #define BIT_04 ((uint32_t)(0x00000010UL)) 44 #define BIT_03 ((uint32_t)(0x00000008UL)) 45 #define BIT_02 ((uint32_t)(0x00000004UL)) 46 #define BIT_01 ((uint32_t)(0x00000002UL)) 47 #define BIT_00 ((uint32_t)(0x00000001UL)) 48 49 #define BITS_30 ((uint32_t)(0x3FFFFFFFUL)) 50 #define BITS_24 ((uint32_t)(0x00FFFFFFUL)) 51 #define BITS_22 ((uint32_t)(0x003FFFFFUL)) 52 #define BITS_18 ((uint32_t)(0x0003FFFFUL)) 53 #define BITS_16 ((uint32_t)(0x0000FFFFUL)) 54 #define BITS_15 ((uint32_t)(0x00007FFFUL)) 55 #define BITS_14 ((uint32_t)(0x00003FFFUL)) 56 #define BITS_13 ((uint32_t)(0x00001FFFUL)) 57 #define BITS_12 ((uint32_t)(0x00000FFFUL)) 58 #define BITS_11 ((uint32_t)(0x000007FFUL)) 59 #define BITS_10 ((uint32_t)(0x000003FFUL)) 60 #define BITS_09 ((uint32_t)(0x000001FFUL)) 61 #define BITS_08 ((uint32_t)(0x000000FFUL)) 62 #define BITS_07 ((uint32_t)(0x0000007FUL)) 63 #define BITS_06 ((uint32_t)(0x0000003FUL)) 64 #define BITS_05 ((uint32_t)(0x0000001FUL)) 65 #define BITS_04 ((uint32_t)(0x0000000FUL)) 66 #define BITS_03 ((uint32_t)(0x00000007UL)) 67 #define BITS_02 ((uint32_t)(0x00000003UL)) 68 69 70 /******************************************************************************* 71 Register Bit definitions 72 */ 73 74 /* General MAC Network Control register bit definitions */ 75 /* eMAC Network Control register bit definitions */ 76 77 #define GEM_IFG_EATS_QAV_CREDIT BIT_30 78 #define GEM_TWO_PT_FIVE_GIG BIT_29 79 #define GEM_SEL_MII_ON_RGMII BIT_28 80 #define GEM_OSS_CORRECTION_FIELD BIT_27 81 #define GEM_EXT_RXQ_SEL_EN BIT_26 82 #define GEM_PFC_CTRL BIT_25 83 #define GEM_ONE_STEP_SYNC_MODE BIT_24 84 #define GEM_EXT_TSU_PORT_ENABLE BIT_23 85 #define GEM_STORE_UDP_OFFSET BIT_22 86 #define GEM_ALT_SGMII_MODE BIT_21 87 #define GEM_PTP_UNICAST_ENA BIT_20 88 #define GEM_TX_LPI_EN BIT_19 89 #define GEM_FLUSH_RX_PKT_PCLK BIT_18 90 #define GEM_TRANSMIT_PFC_PRIORITY_BASED_PAUSE_FRAME BIT_17 91 #define GEM_PFC_ENABLE BIT_16 92 #define GEM_STORE_RX_TS BIT_15 93 #define GEM_TX_PAUSE_FRAME_ZERO BIT_12 94 #define GEM_TX_PAUSE_FRAME_REQ BIT_11 95 #define GEM_TRANSMIT_HALT BIT_10 96 #define GEM_TRANSMIT_START BIT_09 97 #define GEM_BACK_PRESSURE BIT_08 98 #define GEM_STATS_WRITE_EN BIT_07 99 #define GEM_INC_ALL_STATS_REGS BIT_06 100 #define GEM_CLEAR_ALL_STATS_REGS BIT_05 101 #define GEM_MAN_PORT_EN BIT_04 102 #define GEM_ENABLE_TRANSMIT BIT_03 103 #define GEM_ENABLE_RECEIVE BIT_02 104 #define GEM_LOOPBACK_LOCAL BIT_01 105 #define GEM_LOOPBACK BIT_00 106 107 /* General MAC Network Configuration register bit definitions */ 108 /* eMAC Network Configuration register bit definitions */ 109 110 #define GEM_UNI_DIRECTION_ENABLE BIT_31 111 #define GEM_IGNORE_IPG_RX_ER BIT_30 112 #define GEM_NSP_CHANGE BIT_29 113 #define GEM_IPG_STRETCH_ENABLE BIT_28 114 #define GEM_SGMII_MODE_ENABLE BIT_27 115 #define GEM_IGNORE_RX_FCS BIT_26 116 #define GEM_EN_HALF_DUPLEX_RX BIT_25 117 #define GEM_RECEIVE_CHECKSUM_OFFLOAD_ENABLE BIT_24 118 #define GEM_DISABLE_COPY_OF_PAUSE_FRAMES BIT_23 119 #define GEM_DATA_BUS_WIDTH (BIT_21 | BIT_22) 120 #define GEM_MDC_CLOCK_DIVISOR (BIT_18 | BIT_19 | BIT_20) 121 #define GEM_FCS_REMOVE BIT_17 122 #define GEM_LENGTH_FIELD_ERROR_FRAME_DISCARD BIT_16 123 #define GEM_RECEIVE_BUFFER_OFFSET (BIT_14 | BIT_15) 124 #define GEM_PAUSE_ENABLE BIT_13 125 #define GEM_RETRY_TEST BIT_12 126 #define GEM_PCS_SELECT BIT_11 127 #define GEM_GIGABIT_MODE_ENABLE BIT_10 128 #define GEM_EXTERNAL_ADDRESS_MATCH_ENABLE BIT_09 129 #define GEM_RECEIVE_1536_BYTE_FRAMES BIT_08 130 #define GEM_UNICAST_HASH_ENABLE BIT_07 131 #define GEM_MULTICAST_HASH_ENABLE BIT_06 132 #define GEM_NO_BROADCAST BIT_05 133 #define GEM_COPY_ALL_FRAMES BIT_04 134 #define GEM_JUMBO_FRAMES BIT_03 135 #define GEM_DISCARD_NON_VLAN_FRAMES BIT_02 136 #define GEM_FULL_DUPLEX BIT_01 137 #define GEM_SPEED BIT_00 138 139 #define GEM_DATA_BUS_WIDTH_SHIFT 21 140 #define GEM_MDC_CLOCK_DIVISOR_SHIFT 18 141 #define GEM_MDC_CLOCK_DIVISOR_MASK BITS_03 142 #define GEM_RECEIVE_BUFFER_OFFSET_SHIFT 14 143 144 /* General MAC Network Status register bit definitions */ 145 /* eMAC Network Status register bit definitions */ 146 147 #define GEM_LPI_INDICATE_PCLK BIT_07 148 #define GEM_PFC_NEGOTIATE_PCLK BIT_06 149 #define GEM_MAC_PAUSE_TX_EN BIT_05 150 #define GEM_MAC_PAUSE_RX_EN BIT_04 151 #define GEM_MAC_FULL_DUPLEX BIT_03 152 #define GEM_MAN_DONE BIT_02 153 #define GEM_MDIO_IN BIT_01 154 #define GEM_PCS_LINK_STATE BIT_00 155 156 /* General MAC User IO register bit definitions */ 157 158 #define GEM_CODEGROUP_BYPASS BIT_05 159 #define GEM_COMMA_BYPASS BIT_04 160 #define GEM_TSU_CLK_SOURCE BIT_00 161 162 /* General MAC DMA Config register bit definitions */ 163 /* eMAC DMA Config register bit definitions */ 164 165 #define GEM_DMA_ADDR_BUS_WIDTH_1 BIT_30 166 #define GEM_TX_BD_EXTENDED_MODE_EN BIT_29 167 #define GEM_RX_BD_EXTENDED_MODE_EN BIT_28 168 #define GEM_FORCE_MAX_AMBA_BURST_TX BIT_26 169 #define GEM_FORCE_MAX_AMBA_BURST_RX BIT_25 170 #define GEM_FORCE_DISCARD_ON_ERR BIT_24 171 #define GEM_RX_BUF_SIZE (BITS_08 << 16) 172 #define GEM_CRC_ERROR_REPORT BIT_13 173 #define GEM_INFINITE_LAST_DBUF_SIZE_EN BIT_12 174 #define GEM_TX_PBUF_TCP_EN BIT_11 175 #define GEM_TX_PBUF_SIZE BIT_10 176 #define GEM_RX_PBUF_SIZE (BIT_08 | BIT_09) 177 #define GEM_ENDIAN_SWAP_PACKET BIT_07 178 #define GEM_ENDIAN_SWAP_MANAGEMENT BIT_06 179 #define GEM_HDR_DATA_SPLITTING_EN BIT_05 180 #define GEM_AMBA_BURST_LENGTH BITS_05 181 182 #define GEM_RX_BUF_SIZE_SHIFT 16 183 #define GEM_RX_PBUF_SIZE_SHIFT 8 184 185 /* General MAC Transmit Status register bit definitions */ 186 /* eMAC Transmit Status register bit definitions */ 187 188 #define GEM_TX_DMA_LOCKUP_DETECTED BIT_10 189 #define GEM_TX_MAC_LOCKUP_DETECTED BIT_09 190 #define GEM_TX_RESP_NOT_OK BIT_08 191 #define GEM_LATE_COLLISION_OCCURRED BIT_07 192 #define GEM_STAT_TRANSMIT_UNDER_RUN BIT_06 193 #define GEM_STAT_TRANSMIT_COMPLETE BIT_05 194 #define GEM_STAT_AMBA_ERROR BIT_04 195 #define GEM_TRANSMIT_GO BIT_03 196 #define GEM_RETRY_LIMIT_EXCEEDED BIT_02 197 #define GEM_COLLISION_OCCURRED BIT_01 198 #define GEM_USED_BIT_READ BIT_00 199 200 /* General MAC Receive Queue Pointer register bit definitions */ 201 /* General MAC Receive Queue 1 Pointer register bit definitions */ 202 /* General MAC Receive Queue 2 Pointer register bit definitions */ 203 /* General MAC Receive Queue 3 Pointer register bit definitions */ 204 /* eMAC Receive Queue Pointer register bit definitions */ 205 206 #define GEM_DMA_RX_Q_PTR (~(BIT_00 | BIT_01)) 207 #define GEM_DMA_RX_DIS_Q BIT_00 208 209 /* General MAC Transmit Queue Pointer register bit definitions */ 210 /* General MAC Transmit Queue 1 Pointer register bit definitions */ 211 /* General MAC Transmit Queue 2 Pointer register bit definitions */ 212 /* General MAC Transmit Queue 3 Pointer register bit definitions */ 213 /* eMAC Transmit Queue Pointer register bit definitions */ 214 215 #define GEM_DMA_TX_Q_PTR (~(BIT_00 | BIT_01)) 216 #define GEM_DMA_TX_DIS_Q BIT_00 217 218 /* General MAC Receive Status register bit definitions */ 219 /* eMAC Receive Status register bit definitions */ 220 221 #define GEM_RX_DMA_LOCKUP_DETECTED BIT_05 222 #define GEM_RX_MAC_LOCKUP_DETECTED BIT_04 223 #define GEM_RX_RESP_NOT_OK BIT_03 224 #define GEM_RECEIVE_OVERRUN BIT_02 225 #define GEM_FRAME_RECEIVED BIT_01 226 #define GEM_BUFFER_NOT_AVAILABLE BIT_00 227 228 /* General MAC Interrupt Status register bit definitions */ 229 /* General MAC Interrupt Enable register bit definitions */ 230 /* General MAC Interrupt Disable register bit definitions */ 231 /* General MAC Interrupt Mask register bit definitions */ 232 /* General MAC Priority Queue 1 Interrupt Status register bit definitions - b01 to b11 only */ 233 /* General MAC Priority Queue 2 Interrupt Status register bit definitions - b01 to b11 only */ 234 /* General MAC Priority Queue 3 Interrupt Status register bit definitions - b01 to b11 only */ 235 /* General MAC Priority Queue 1 Interrupt Enable register bit definitions - b01 to b11 only */ 236 /* General MAC Priority Queue 2 Interrupt Enable register bit definitions - b01 to b11 only */ 237 /* General MAC Priority Queue 3 Interrupt Enable register bit definitions - b01 to b11 only */ 238 /* General MAC Priority Queue 1 Interrupt Disable register bit definitions - b01 to b11 only */ 239 /* General MAC Priority Queue 2 Interrupt Disable register bit definitions - b01 to b11 only */ 240 /* General MAC Priority Queue 3 Interrupt Disable register bit definitions - b01 to b11 only */ 241 /* General MAC Priority Queue 1 Interrupt Mask register bit definitions - b01 to b11 only */ 242 /* General MAC Priority Queue 2 Interrupt Mask register bit definitions - b01 to b11 only */ 243 /* General MAC Priority Queue 3 Interrupt Mask register bit definitions - b01 to b11 only */ 244 /* eMAC Interrupt Status register bit definitions */ 245 /* eMAC Interrupt Enable register bit definitions */ 246 /* eMAC Interrupt Disable register bit definitions */ 247 /* eMAC Interrupt Mask register bit definitions */ 248 249 #define GEM_TX_LOCKUP_DETECTED BIT_31 250 #define GEM_RX_LOCKUP_DETECTED BIT_30 251 #define GEM_TSU_TIMER_COMPARISON_INTERRUPT BIT_29 252 #define GEM_WOL_INTERRUPT BIT_28 253 #define GEM_RX_LPI_INDICATION_STATUS_BIT_CHANGE BIT_27 254 #define GEM_TSU_SECONDS_REGISTER_INCREMENT BIT_26 255 #define GEM_PTP_PDELAY_RESP_FRAME_TRANSMITTED BIT_25 256 #define GEM_PTP_PDELAY_REQ_FRAME_TRANSMITTED BIT_24 257 #define GEM_PTP_PDELAY_RESP_FRAME_RECEIVED BIT_23 258 #define GEM_PTP_PDELAY_REQ_FRAME_RECEIVED BIT_22 259 #define GEM_PTP_SYNC_FRAME_TRANSMITTED BIT_21 260 #define GEM_PTP_DELAY_REQ_FRAME_TRANSMITTED BIT_20 261 #define GEM_PTP_SYNC_FRAME_RECEIVED BIT_19 262 #define GEM_PTP_DELAY_REQ_FRAME_RECEIVED BIT_18 263 #define GEM_PCS_LINK_PARTNER_PAGE_RECEIVED BIT_17 264 #define GEM_PCS_AUTO_NEGOTIATION_COMPLETE BIT_16 265 #define GEM_EXTERNAL_INTERRUPT BIT_15 266 #define GEM_PAUSE_FRAME_TRANSMITTED BIT_14 267 #define GEM_PAUSE_TIME_ELAPSED BIT_13 268 #define GEM_PAUSE_FRAME_WITH_NON_0_PAUSE_QUANTUM_RX BIT_12 269 #define GEM_RESP_NOT_OK_INT BIT_11 270 #define GEM_RECEIVE_OVERRUN_INT BIT_10 271 #define GEM_LINK_CHANGE BIT_09 272 #define GEM_TRANSMIT_COMPLETE BIT_07 273 #define GEM_AMBA_ERROR BIT_06 274 #define GEM_RETRY_LIMIT_EXCEEDED_OR_LATE_COLLISION BIT_05 275 #define GEM_TRANSMIT_UNDER_RUN BIT_04 276 #define GEM_TX_USED_BIT_READ BIT_03 277 #define GEM_RX_USED_BIT_READ BIT_02 278 #define GEM_RECEIVE_COMPLETE BIT_01 279 #define GEM_MANAGEMENT_FRAME_SENT BIT_00 280 281 /* 282 * General MAC Fatal or Non Fatal Interrupt register bit definitions 283 * Note bits 0 to 15 are as per interrupt mask etc registers above. 284 */ 285 286 #define GEM_LOCKUP_DETECTED_INT_TYPE BIT_22 287 #define GEM_TSU_TIMER_COMPARISON_INTERRUPT_INT_TYPE BIT_21 288 #define GEM_WOL_INTERRUPT_INT_TYPE BIT_20 289 #define GEM_RECEIVE_LPI_INT_TYPE BIT_19 290 #define GEM_TSU_SECONDS_REGISTER_INCREMENT_INT_TYPE BIT_18 291 #define GEM_PTP_FRAME_RECEIVED_INT_TYPE BIT_17 292 #define GEM_PCS_INT_TYPE BIT_16 293 294 /* General MAC Phy Management register bit definitions */ 295 /* eMAC Phy Management register bit definitions */ 296 297 #define GEM_WRITE0 BIT_31 298 #define GEM_WRITE1 BIT_30 299 #define GEM_OPERATION (BIT_28 | BIT_29) 300 #define GEM_PHY_ADDRESS (BITS_05 << 23) 301 #define GEM_REGISTER_ADDRESS (BITS_05 << 18) 302 #define GEM_WRITE10 (BIT_16 | BIT_17) 303 #define GEM_PHY_WRITE_READ_DATA BITS_16 304 305 #define GEM_PHY_OP_CL22_WRITE ((uint32_t)(1UL)) 306 #define GEM_PHY_OP_CL22_READ ((uint32_t)(2UL)) 307 308 #define GEM_PHY_OP_CL45_ADDRESS ((uint32_t)(0UL)) 309 #define GEM_PHY_OP_CL45_WRITE ((uint32_t)(1UL)) 310 #define GEM_PHY_OP_CL45_POST_READ_INC ((uint32_t)(2UL)) 311 #define GEM_PHY_OP_CL45_READ ((uint32_t)(3UL)) 312 313 #define GEM_OPERATION_SHIFT 28 314 #define GEM_PHY_ADDRESS_SHIFT 23 315 #define GEM_REGISTER_ADDRESS_SHIFT 18 316 #define GEM_WRITE10_SHIFT 16 317 318 /* General MAC Pause Time register bit definitions */ 319 /* General MAC Transmit Pause Time register bit definitions */ 320 /* eMAC Pause Time register bit definitions */ 321 /* eMAC Transmit Pause Time register bit definitions */ 322 323 #define GEM_QUANTUM BITS_16 324 325 /* General MAC PBuff TX Cutthru register bit definitions */ 326 /* General MAC PBuff RX Cutthru register bit definitions */ 327 /* eMAC PBuff TX Cutthru register bit definitions */ 328 /* eMAC PBuff RX Cutthru register bit definitions */ 329 330 #define GEM_DMA_CUTTHRU BIT_31 331 #define GEM_DMA_TX_CUTTHRU_THRESHOLD BITS_11 332 #define GEM_DMA_RX_CUTTHRU_THRESHOLD BITS_10 333 #define GEM_DMA_EMAC_CUTTHRU_THRESHOLD BITS_09 334 335 /* General MAC Jumbo Max Length register bit definitions */ 336 /* eMAC Jumbo Max Length register bit definitions */ 337 338 #define GEM_JUMBO_MAX_LENGTH BITS_14 339 340 /* General MAC AXI Max Pipeline register bit definitions */ 341 /* eMAC AXI Max Pipeline register bit definitions */ 342 343 #define GEM_USE_AW2B_FILL BIT_16 344 #define GEM_AW2W_MAX_PIPELINE (BITS_08 << 8) 345 #define GEM_AR2R_MAX_PIPELINE BITS_08 346 347 /* General MAC Int Moderation register bit definitions */ 348 /* eMAC Int Moderation register bit definitions */ 349 350 #define GEM_TX_INT_MODERATION (BITS_08 << 16) 351 #define GEM_RX_INT_MODERATION BITS_08 352 353 /* General MAC Sys Wake Time register bit definitions */ 354 /* eMAC Sys Wake Time register bit definitions */ 355 356 #define GEM_SYS_WAKE_TIME BITS_16 357 358 /* General MAC Lockup Config register bit definitions */ 359 /* General RX MAC Lockup Time register bit definitions */ 360 /* eMAC Lockup Config register bit definitions */ 361 /* RX eMAC Lockup Time register bit definitions */ 362 363 #define GEM_TX_DMA_LOCKUP_MON_EN BIT_31 364 #define GEM_TX_MAC_LOCKUP_MON_EN BIT_30 365 #define GEM_RX_DMA_LOCKUP_MON_EN BIT_29 366 #define GEM_RX_MAC_LOCKUP_MON_EN BIT_28 367 #define GEM_LOCKUP_RECOVERY_EN BIT_27 368 #define GEM_LOCKUP_TIME BITS_16 369 370 /* General MAC Specific Address 1 Top register bit definitions */ 371 /* General MAC Specific Address 2 Top register bit definitions */ 372 /* General MAC Specific Address 3 Top register bit definitions */ 373 /* General MAC Specific Address 4 Top register bit definitions */ 374 /* eMAC Specific Address 1 Top register bit definitions */ 375 /* eMAC Specific Address 2 Top register bit definitions */ 376 /* eMAC Specific Address 3 Top register bit definitions */ 377 /* eMAC Specific Address 4 Top register bit definitions */ 378 379 #define GEM_FILTER_BYTE_MASK (BITS_06 << 24) 380 #define GEM_FILTER_TYPE BIT_16 381 #define GEM_SPEC_ADDRESS BITS_16 382 383 /* General MAC Specific Address Type 1 register bit definitions */ 384 /* General MAC Specific Address Type 2 register bit definitions */ 385 /* General MAC Specific Address Type 3 register bit definitions */ 386 /* General MAC Specific Address Type 4 register bit definitions */ 387 /* eMAC Specific Address Type 1 register bit definitions */ 388 /* eMAC Specific Address Type 2 register bit definitions */ 389 /* eMAC Specific Address Type 3 register bit definitions */ 390 /* eMAC Specific Address Type 4 register bit definitions */ 391 392 #define GEM_ENABLE_COPY BIT_31 393 #define GEM_SPEC_ADDR_MATCH BITS_16 394 395 /* General MAC Wake On LAN register bit definitions */ 396 /* eMAC Wake On LAN register bit definitions */ 397 398 #define GEM_WOL_MULTICAST_HASH BIT_19 399 #define GEM_WOL_SPEC_ADDRESS_1 BIT_18 400 #define GEM_WOL_ARP_REQUEST BIT_17 401 #define GEM_WOL_MAGIC_PACKET BIT_16 402 #define GEM_WOL_ADDRESS BITS_16 403 404 /* General MAC Stretch Ratio register bit definitions */ 405 /* eMAC Stretch Ratio register bit definitions */ 406 407 #define GEM_IPG_STRETCH BITS_16 408 #define GEM_IPG_STRETCH_DIV (BITS_8 << 8) 409 #define GEM_IPG_STRETCH_MUL BITS_08 410 411 #define GEM_IPG_STRETCH_DIV_MASK BITS_08 412 #define GEM_IPG_STRETCH_DIV_SHIFT 8 413 #define GEM_IPG_STRETCH_MUL_MASK BITS_08 414 415 /* General MAC Stacked VLAN register bit definitions */ 416 /* eMAC Stacked VLAN register bit definitions */ 417 418 #define GEM_ENABLE_PROCESSING BIT_31 419 #define GEM_VLAN_MATCH BITS_16 420 #define GEM_VLAN_C_TAG (0x8100U) 421 #define GEM_VLAN_S_TAG (0x88A8U) 422 423 /* Valid EtherTypes including VLAN tags must be bigger than this */ 424 #define GEM_VLAN_ETHERTYPE_MIN (1536U) 425 #define GEM_VLAN_NO_STACK (0U) 426 427 /* General MAC Transmit PFC Pause register bit definitions */ 428 /* eMAC Transmit PFC Pause register bit definitions */ 429 430 #define GEM_VECTOR (BITS_08 << 8) 431 #define GEM_VECTOR_ENABLE BITS_08 432 433 /* General MAC Specific Address Type 1 Mask register bit definitions */ 434 /* eMAC Specific Address Type 1 Mask register bit definitions */ 435 436 #define GEM_SPEC_ADDR_MASK BITS_16 437 438 /* General MAC Receive DMA Data Buffer Address Mask register bit definitions */ 439 /* eMAC Receive DMA Data Buffer Address Mask register bit definitions */ 440 441 #define GEM_DMA_DBUF_ADDR_MASK_VALUE (BITS_04 << 28) 442 #define GEM_DMA_DBUF_ADDR_MASK_ENABLE BITS_04 443 444 /* General MAC TSU timer comparison value nanosecond register bit definitions */ 445 /* eMAC TSU timer comparison value nanosecond register bit definitions */ 446 447 #define GEM_NSEC_COMPARISON_VALUE BITS_22 448 449 /* General MAC TSU timer comparison value seconds 47:32 register bit definitions */ 450 /* General MAC PTP Event Frame Transmitted Seconds Register 47:32 register bit definitions */ 451 /* General MAC PTP Event Frame Received Seconds Register 47:32 register bit definitions */ 452 /* General MAC PTP Peer Event Frame Transmitted Seconds Register 47:32 register bit definitions */ 453 /* General MAC PTP Peer Event Frame Received Seconds Register 47:32 register bit definitions */ 454 /* eMAC TSU timer comparison value seconds 47:32 register bit definitions */ 455 /* eMAC PTP Event Frame Transmitted Seconds Register 47:32 register bit definitions */ 456 /* eMAC PTP Event Frame Received Seconds Register 47:32 register bit definitions */ 457 /* eMAC PTP Peer Event Frame Transmitted Seconds Register 47:32 register bit definitions */ 458 /* eMAC PTP Peer Event Frame Received Seconds Register 47:32 register bit definitions */ 459 460 #define GEM_SEC_VALUE_UPPER BITS_16 461 462 /* General MAC DP RAM Fill Debug register bit definitions */ 463 /* eMAC DP RAM Fill Debug register bit definitions */ 464 465 #define GEM_DMA_TX_RX_FILL_LEVEL (BITS_16 << 16) 466 #define GEM_DMA_TX_Q_FILL_LEVEL_SELECT (BITS_04 << 4) 467 #define GEM_DMA_TX_RX_FILL_LEVEL_SELECT BIT_00 468 469 /* General MAC Revision register bit definitions */ 470 /* eMAC Revision register bit definitions */ 471 472 #define GEM_FIX_NUMBER (BITS_04 << 24) 473 #define GEM_MODULE_IDENTIFICATION_NUMBER (BITS_12 << 16) 474 #define GEM_MODULE_REVISION BITS_16 475 476 /* General MAC Octets Transmitted Top register bit definitions */ 477 /* General MAC Octets Received Top register bit definitions */ 478 /* eMAC Octets Transmitted Top register bit definitions */ 479 /* eMAC Octets Received Top register bit definitions */ 480 481 #define GEM_UPPER_BITS_OF_48 BITS_16 482 483 /* General MAC Pause Frames Transmitted register bit definitions */ 484 /* General MAC Pause Frames Received register bit definitions */ 485 /* eMAC Pause Frames Transmitted register bit definitions */ 486 /* eMAC Pause Frames Received register bit definitions */ 487 488 #define GEM_FRAME_COUNT BITS_16 489 490 /* General MAC Transmit Underruns register bit definitions */ 491 /* eMAC Transmit Underruns register bit definitions */ 492 493 #define GEM_UNDERRUN_COUNT BITS_10 494 495 /* General MAC Single Collision register bit definitions */ 496 /* General MAC Multiple Collisions register bit definitions */ 497 /* eMAC Single Collision register bit definitions */ 498 /* eMAC Multiple Collisions register bit definitions */ 499 500 #define GEM_SM_COLLISION_COUNT BITS_18 501 502 /* General MAC Late Collisions register bit definitions */ 503 /* eMAC Late Collisions register bit definitions */ 504 505 #define GEM_LATE_COLLISION_COUNT BITS_10 506 507 /* General MAC Deferred Frames register bit definitions */ 508 /* eMAC Deferred Frames register bit definitions */ 509 510 #define GEM_DEFERRED_FRAMES_COUNT BITS_18 511 512 /* General MAC CRS Errors register bit definitions */ 513 /* eMAC CRS Errors register bit definitions */ 514 515 #define GEM_CRS_ERROR_COUNT BITS_10 516 517 /* General MAC Undersize Frames Received register bit definitions */ 518 /* eMAC Undersize Frames Received register bit definitions */ 519 520 #define GEM_RUNT_FRAME_COUNT BITS_10 521 522 /* General MAC Oversize Frames Received register bit definitions */ 523 /* eMAC Oversize Frames Received register bit definitions */ 524 525 #define GEM_OVERSIZE_FRAME_COUNT BITS_10 526 527 /* General MAC Jabbers Received register bit definitions */ 528 /* eMAC Jabbers Received register bit definitions */ 529 530 #define GEM_JABBER_COUNT BITS_10 531 532 /* General MAC FCS Error register bit definitions */ 533 /* eMAC FCS Error register bit definitions */ 534 535 #define GEM_FCS_ERROR_COUNT BITS_10 536 537 /* General MAC Length Field Frame Errors register bit definitions */ 538 /* eMAC Length Field Frame Errors register bit definitions */ 539 540 #define GEM_LENGTH_ERROR_COUNT BITS_10 541 542 /* General MAC Receive Symbol Errors register bit definitions */ 543 /* eMAC Receive Symbol Errors register bit definitions */ 544 545 #define GEM_SYMBOL_ERROR_COUNT BITS_10 546 547 /* General MAC Receive Alignment Errors register bit definitions */ 548 /* eMAC Receive Alignment Errors register bit definitions */ 549 550 #define GEM_ALIGNMENT_ERROR_COUNT BITS_10 551 552 /* General MAC Receive Resource Error register bit definitions */ 553 /* eMAC Receive Resource Error register bit definitions */ 554 555 #define GEM_RESOURCE_ERROR_COUNT BITS_10 556 557 /* General MAC Receive Overrun register bit definitions */ 558 /* eMAC Receive Overrun register bit definitions */ 559 560 #define GEM_OVERRUN_COUNT BITS_10 561 562 /* General MAC IP Checksum Error register bit definitions */ 563 /* General MAC TCP Checksum Error register bit definitions */ 564 /* General MAC UDP Checksum Error register bit definitions */ 565 /* eMAC IP Checksum Error register bit definitions */ 566 /* eMAC TCP Checksum Error register bit definitions */ 567 /* eMAC UDP Checksum Error register bit definitions */ 568 569 #define GEM_IP_CHECKSUM_ERROR_COUNT BITS_08 570 571 /* General MAC Auto Flushed Packets register bit definitions */ 572 /* eMAC Auto Flushed Packets register bit definitions */ 573 574 #define GEM_AUTO_FLUSHED_COUNT BITS_16 575 576 /* General MAC TSU Timer Increment Sub Nanoseconds register bit definitions */ 577 /* eMAC TSU Timer Increment Sub Nanoseconds register bit definitions */ 578 579 #define GEM_SUB_NS_INCR_LSB (BITS_08 << 24) 580 #define GEM_SUB_NS_INCR BITS_16 581 582 /* General MAC TSU Timer Seconds MSB register bit definitions */ 583 /* General MAC TSU Strobe Seconds MSB register bit definitions */ 584 585 #define GEM_TSU_SECONDS_MSB BITS_16 586 587 /* General MAC TSU Timer Sync Strobe Nanoseconds register bit definitions */ 588 /* General MAC TSU Timer Nanoseconds register bit definitions */ 589 /* General MAC TSU Timer Adjust register bit definitions */ 590 /* General MAC PTP Event Frame Transmitted Nanoseconds register bit definitions */ 591 /* General MAC PTP Event Frame Received Nanoseconds register bit definitions */ 592 /* General MAC PTP Peer Event Frame Transmitted Nanoseconds register bit definitions */ 593 /* General MAC PTP Peer Event Frame Received Nanoseconds register bit definitions */ 594 /* eMAC TSU Timer Sync Strobe Nanoseconds register bit definitions */ 595 /* eMAC TSU Timer Nanoseconds register bit definitions */ 596 /* eMAC TSU Timer Adjust register bit definitions */ 597 /* eMAC PTP Event Frame Transmitted Nanoseconds register bit definitions */ 598 /* eMAC PTP Event Frame Received Nanoseconds register bit definitions */ 599 /* eMAC PTP Peer Event Frame Transmitted Nanoseconds register bit definitions */ 600 /* eMAC PTP Peer Event Frame Received Nanoseconds register bit definitions */ 601 602 #define GEM_ADD_SUBTRACT BIT_31 /* Adjust register only... */ 603 #define GEM_TSU_NANOSECONDS BITS_30 604 605 /* General MAC TSU Timer Adjust register bit definitions */ 606 /* eMAC TSU Timer Adjust register bit definitions */ 607 608 #define GEM_NUM_INCS (BITS_08 << 16) 609 #define GEM_ALT_NS_INC (BITS_08 << 8) 610 #define GEM_NS_INCREMENT BITS_08 611 612 /* General MAC PCS Control register bit definitions */ 613 614 #define GEM_PCS_SOFTWARE_RESET BIT_15 615 #define GEM_LOOPBACK_MODE BIT_14 616 #define GEM_SPEED_SELECT_BIT_1 BIT_13 617 #define GEM_ENABLE_AUTO_NEG BIT_12 618 #define GEM_RESTART_AUTO_NEG BIT_09 619 #define GEM_MAC_DUPLEX_STATE BIT_08 620 #define GEM_COLLISION_TEST BIT_07 621 #define GEM_SPEED_SELECT_BIT_0 BIT_06 622 623 /* General MAC PCS Status register bit definitions */ 624 625 #define GEM_BASE_100_T4 BIT_15 626 #define GEM_BASE_100_X_FULL_DUPLEX BIT_14 627 #define GEM_BASE_100_X_HALF_DUPLEX BIT_13 628 #define GEM_MBPS_10_FULL_DUPLEX BIT_12 629 #define GEM_MBPS_10_HALF_DUPLEX BIT_11 630 #define GEM_BASE_100_T2_FULL_DUPLEX BIT_10 631 #define GEM_BASE_100_T2_HALF_DUPLEX BIT_09 632 #define GEM_EXTENDED_STATUS BIT_08 633 #define GEM_AUTO_NEG_COMPLETE BIT_05 634 #define GEM_REMOTE_FAULT BIT_04 635 #define GEM_AUTO_NEG_ABILITY BIT_03 636 #define GEM_LINK_STATUS BIT_02 637 #define GEM_EXTENDED_CAPABILITIES BIT_00 638 639 /* General MAC PCS PHY Top ID register bit definitions */ 640 /* General MAC PCS PHY Bottom ID register bit definitions */ 641 642 #define GEM_ID_CODE BITS_16 643 644 /* General MAC PCS Autonegotiation Advertisment register bit definitions */ 645 646 #define GEM_AN_AV_NEXT_PAGE BIT_15 647 #define GEM_AN_AV_REMOTE_FAULT (BIT_12 | BIT_13) 648 #define GEM_AN_AV_PAUSE (BIT_08 | BIT_07) 649 #define GEM_AN_AV_HALF_DUPLEX BIT_06 650 #define GEM_AN_AV_FULL_DUPLEX BIT_05 651 652 /* General MAC PCS Autonegotiation Link Partner Base register bit definitions */ 653 654 #define GEM_LINK_PARTNER_NEXT_PAGE_STATUS BIT_15 655 #define GEM_LINK_PARTNER_ACKNOWLEDGE BIT_14 656 #define GEM_LINK_PARTNER_REMOTE_FAULT_DUPLEX_MODE (BIT_12 | BIT_13) 657 #define GEM_LINK_PARTNER_SPEED (BIT_10 | BIT_11) 658 #define GEM_LINK_PARTNER_PAUSE (BIT_07 | BIT_08) 659 #define GEM_LINK_PARTNER_HALF_DUPLEX BIT_06 660 #define GEM_LINK_PARTNER_FULL_DUPLEX BIT_05 661 662 /* General MAC PCS Autonegotiation Next Page Ability register bit definitions */ 663 664 #define GEM_NEXT_PAGE_CAPABILITY BIT_02 665 #define GEM_PAGE_RECEIVED BIT_01 666 667 /* General MAC PCS Autonegotiation Next Page Transmit register bit definitions */ 668 /* General MAC PCS Autonegotiation Next Page Receive register bit definitions */ 669 670 #define GEM_NEXT_PAGE_TO_TRANSMIT BIT_15 671 #define GEM_NEXT_PAGE_TO_RECEIVE BIT_15 672 #define GEM_ACKNOWLEDGE BIT_14 673 #define GEM_MESSAGE_PAGE_INDICATOR BIT_13 674 #define GEM_ACKNOWLEDGE_2 BIT_12 675 #define GEM_TOGGLE BIT_11 676 #define GEM_AN_MESSAGE BITS_11 677 678 /* General MAC PCS Autonegotiation Extended Status register bit definitions */ 679 680 #define GEM_FULL_DUPLEX_1000BASE_X BIT_15 681 #define GEM_HALF_DUPLEX_1000BASE_X BIT_14 682 #define GEM_FULL_DUPLEX_1000BASE_T BIT_13 683 #define GEM_HALF_DUPLEX_1000BASE_T BIT_12 684 685 /* General MAC Received LPI Transitions register bit definitions */ 686 /* General MAC Transmitted LPI Transitions register bit definitions */ 687 /* eMAC Received LPI Transitions register bit definitions */ 688 /* eMAC Transmitted LPI Transitions register bit definitions */ 689 690 #define GEM_LPI_COUNT BITS_16 691 692 /* General MAC Received LPI Time register bit definitions */ 693 /* General MAC Transmitted LPI Time register bit definitions */ 694 /* eMAC Received LPI Time register bit definitions */ 695 /* eMAC Transmitted LPI Time register bit definitions */ 696 697 #define GEM_LPI_TIME BITS_24 698 699 /* General MAC Design Configuration Debug 1 register bit definitions */ 700 /* eMAC Design Configuration Debug 1 register bit definitions */ 701 702 #define GEM_AXI_CACHE_VALUE (BITS_04 << 28) 703 #define GEM_DMA_BUS_WIDTH (BIT_25 | BIT_26 | BIT 27) 704 #define GEM_EXCLUDE_CBS BIT_24 705 #define GEM_IRQ_READ_CLEAR BIT_23 706 #define GEM_NO_SNAPSHOT BIT_22 707 #define GEM_NO_STATS BIT_21 708 #define GEM_USER_IN_WIDTH (BITS_05 << 15) 709 #define GEM_USER_OUT_WIDTH (BITS_05 << 10) 710 #define GEM_USER_IO BIT_09 711 #define GEM_EXT_FIFO_INTERFACE BIT_06 712 #define GEM_INT_LOOPBACK BIT_04 713 #define GEM_EXCLUDE_QBV BIT_01 714 #define GEM_NO_PCS BIT_00 715 716 /* General MAC Design Configuration Debug 2 register bit definitions */ 717 /* eMAC Design Configuration Debug 2 register bit definitions */ 718 719 #define GEM_SPRAM BIT_31 720 #define GEM_AXI BIT_30 721 #define GEM_TX_PBUF_ADDR (BITS_04 << 26) 722 #define GEM_RX_PBUF_ADDR (BITS_04 << 22) 723 #define GEM_TX_PKT_BUFFER BIT_21 724 #define GEM_RX_PKT_BUFFER BIT_20 725 #define GEM_HPROT_VALUE (BITS_04 << 16) 726 #define GEM_JUMBO_MAX_LENGTH BITS_14 727 728 /* General MAC Design Configuration Debug 3 register bit definitions */ 729 /* eMAC Design Configuration Debug 3 register bit definitions */ 730 731 #define GEM_NUM_SPEC_ADD_FILTERS (BITS_06 << 24) 732 733 /* General MAC Design Configuration Debug 5 register bit definitions */ 734 /* eMAC Design Configuration Debug 5 register bit definitions */ 735 736 #define GEM_AXI_PROT_VALUE (BIT_29 | BIT_30 | BIT_31) 737 #define GEM_TSU_CLK BIT_28 738 #define GEM_RX_BUFFER_LENGTH_DEF (BITS_08 << 20) 739 #define GEM_TX_PBUF_SIZE_DEF BIT_19 740 #define GEM_RX_PBUF_SIZE_DEF (BIT_17 | BIT_18) 741 #define GEM_ENDIAN_SWAP_DEF (BIT_15 | BIT_16) 742 #define GEM_MDC_CLOCK_DIV (BIT_12 | BIT_13 | BIT_14) 743 #define GEM_DMA_BUS_WIDTH_DEF (BIT_10 | BIT_11) 744 #define GEM_PHY_IDENT BIT_09 745 #define GEM_TSU BIT_08 746 #define GEM_TX_FIFO_CNT_WIDTH (BITS_04 << 4) 747 #define GEM_RX_FIFO_CNT_WIDTH BITS_04 748 749 /* General MAC Design Configuration Debug 6 register bit definitions */ 750 /* eMAC Design Configuration Debug 6 register bit definitions */ 751 752 #define GEM_PBUF_LSO BIT_27 753 #define GEM_PBUF_RSC BIT_26 754 #define GEM_PBUF_CUTTHRU BIT_25 755 #define GEM_PFC_MULTI_QUANTUM BIT_24 756 #define GEM_DMA_ADDR_WIDTH_IS_64B BIT_23 757 #define GEM_HOST_IF_SOFT_SEL BIT_22 758 #define GEM_TX_ADD_FIFO_IF BIT_21 759 #define GEM_EXT_TSU_TIMER BIT_20 760 #define GEM_TX_PBUF_QUEUE_SEGMENT_SIZE (BITS_04 << 16) 761 #define GEM_DMA_PRIORITY_QUEUE15 BIT_15 762 #define GEM_DMA_PRIORITY_QUEUE14 BIT_14 763 #define GEM_DMA_PRIORITY_QUEUE13 BIT_13 764 #define GEM_DMA_PRIORITY_QUEUE12 BIT_12 765 #define GEM_DMA_PRIORITY_QUEUE11 BIT_11 766 #define GEM_DMA_PRIORITY_QUEUE10 BIT_10 767 #define GEM_DMA_PRIORITY_QUEUE9 BIT_09 768 #define GEM_DMA_PRIORITY_QUEUE8 BIT_08 769 #define GEM_DMA_PRIORITY_QUEUE7 BIT_07 770 #define GEM_DMA_PRIORITY_QUEUE6 BIT_06 771 #define GEM_DMA_PRIORITY_QUEUE5 BIT_05 772 #define GEM_DMA_PRIORITY_QUEUE4 BIT_04 773 #define GEM_DMA_PRIORITY_QUEUE3 BIT_03 774 #define GEM_DMA_PRIORITY_QUEUE2 BIT_02 775 #define GEM_DMA_PRIORITY_QUEUE1 BIT_01 776 777 /* General MAC Design Configuration Debug 7 register bit definitions */ 778 /* eMAC Design Configuration Debug 7 register bit definitions */ 779 780 #define GEM_TX_PBUF_NUM_SEGMENTS_Q7 (BITS_04 << 28) 781 #define GEM_TX_PBUF_NUM_SEGMENTS_Q6 (BITS_04 << 24) 782 #define GEM_TX_PBUF_NUM_SEGMENTS_Q5 (BITS_04 << 20) 783 #define GEM_TX_PBUF_NUM_SEGMENTS_Q4 (BITS_04 << 16) 784 #define GEM_TX_PBUF_NUM_SEGMENTS_Q3 (BITS_04 << 12) 785 #define GEM_TX_PBUF_NUM_SEGMENTS_Q2 (BITS_04 << 8) 786 #define GEM_TX_PBUF_NUM_SEGMENTS_Q1 (BITS_04 << 4) 787 #define GEM_TX_PBUF_NUM_SEGMENTS_Q0 BITS_04 788 789 /* General MAC Design Configuration Debug 8 register bit definitions */ 790 /* eMAC Design Configuration Debug 8 register bit definitions */ 791 792 #define GEM_NUM_TYPE1_SCREENERS (BITS_08 << 24) 793 #define GEM_NUM_TYPE2_SCREENERS (BITS_08 << 16) 794 #define GEM_NUM_SCR2_ETHTYPE_REGS (BITS_08 << 8) 795 #define GEM_NUM_SCR2_COMPARE_REGS BITS_08 796 797 /* General MAC Design Configuration Debug 9 register bit definitions */ 798 /* eMAC Design Configuration Debug 9 register bit definitions */ 799 800 #define GEM_TX_PBUF_NUM_SEGMENTS_Q15 (BITS_04 << 28) 801 #define GEM_TX_PBUF_NUM_SEGMENTS_Q14 (BITS_04 << 24) 802 #define GEM_TX_PBUF_NUM_SEGMENTS_Q13 (BITS_04 << 20) 803 #define GEM_TX_PBUF_NUM_SEGMENTS_Q12 (BITS_04 << 16) 804 #define GEM_TX_PBUF_NUM_SEGMENTS_Q11 (BITS_04 << 12) 805 #define GEM_TX_PBUF_NUM_SEGMENTS_Q10 (BITS_04 << 8) 806 #define GEM_TX_PBUF_NUM_SEGMENTS_Q9 (BITS_04 << 4) 807 #define GEM_TX_PBUF_NUM_SEGMENTS_Q8 BITS_04 808 809 /* General MAC Design Configuration Debug 10 register bit definitions */ 810 /* eMAC Design Configuration Debug 10 register bit definitions */ 811 812 #define GEM_EMAC_BUS_WIDTH (BITS_04 << 28) 813 #define GEM_TX_PBUF_DATA (BITS_04 << 24) 814 #define GEM_RX_PBUF_DATA (BITS_04 << 20) 815 #define GEM_AXI_ACCESS_PIPELINE_BITS (BITS_04 << 16) 816 #define GEM_AXI_TX_DESCR_RD_BUFF_BITS (BITS_04 << 12) 817 #define GEM_AXI_RX_DESCR_RD_BUFF_BITS (BITS_04 << 8) 818 #define GEM_AXI_TX_DESCR_WR_BUFF_BITS (BITS_04 << 4) 819 #define GEM_AXI_RX_DESCR_WR_BUFF_BITS BITS_04 820 821 /* General MAC Design Configuration Debug 11 register bit definitions */ 822 /* eMAC Design Configuration Debug 11 register bit definitions */ 823 824 #define GEM_PROTECT_DESCR_ADDR BIT_04 825 #define GEM_PROTECT_TSU BIT_03 826 #define GEM_ADD_CSR_PARITY BIT_02 827 #define GEM_ADD_DP_PARITY BIT_01 828 #define GEM_ADD_ECC_DPRAM BIT_00 829 830 /* General MAC Design Configuration Debug 12 register bit definitions */ 831 /* eMAC Design Configuration Debug 12 register bit definitions */ 832 833 #define GEM_GEM_HAS_802P3_BR BIT_25 834 #define GEM_EMAC_TX_PBUF_ADDR (BITS_04 << 21) 835 #define GEM_EMAC_RX_PBUF_ADDR (BITS_04 << 17) 836 #define GEM_GEM_HAS_CB BIT_16 837 #define GEM_GEM_CB_HISTORY_LEN (BITS_08 << 8) 838 #define GEM_GEM_NUM_CB_STREAMS BITS_08 839 840 /* General MAC Queue 1 DMA Receive Buffer Size register bit definitions */ 841 /* General MAC Queue 2 DMA Receive Buffer Size register bit definitions */ 842 /* General MAC Queue 3 DMA Receive Buffer Size register bit definitions */ 843 844 #define GEM_DMA_RX_Q_BUF_SIZE BITS_08 845 846 /* General MAC CBS Control register bit definitions */ 847 /* eMAC CBS Control register bit definitions */ 848 849 #define GEM_CBS_ENABLE_QUEUE_B BIT_01 850 #define GEM_CBS_ENABLE_QUEUE_A BIT_00 851 852 /* General MAC TX BD Control register bit definitions */ 853 /* General MAC RX BD Control register bit definitions */ 854 /* eMAC TX BD Control register bit definitions */ 855 /* eMAC RX BD Control register bit definitions */ 856 857 #define GEM_BD_TS_MODE (BIT_04 | BIT_05) 858 #define GEM_BD_TS_MODE_SHIFT 4 859 860 /* General MAC WD Counter register bit definitions */ 861 862 #define GEM_RX_BD_REREAD_TIMER BITS_04 863 864 /* General MAC AXI TX Full Threshold 0 register bit definitions */ 865 866 #define GEM_AXI_TX_FULL_ADJ_0 (BITS_11 << 16) 867 #define GEM_AXI_TX_FULL_ADJ_1 BITS_11 868 869 /* General MAC AXI TX Full Threshold 1 register bit definitions */ 870 871 #define GEM_AXI_TX_FULL_ADJ_2 (BITS_11 << 16) 872 #define GEM_AXI_TX_FULL_ADJ_3 BITS_11 873 874 /* General Screening Type 1 Register register bit definitions */ 875 876 #define GEM_DROP_ON_MATCH BIT_30 877 #define GEM_UDP_PORT_MATCH_ENABLE BIT_29 878 #define GEM_DSTC_ENABLE BIT_28 879 #define GEM_UDP_PORT_MATCH (BITS_16 << 12) 880 #define GEM_DSTC_MATCH (BITS_08 << 4) 881 #define GEM_QUEUE_NUMBER BITS_04 882 883 #define GEM_UDP_PORT_MATCH_SHIFT 12 884 #define GEM_DSTC_MATCH_SHIFT 4 885 886 /* General Screening Type 2 Register register bit definitions */ 887 888 #define GEM_T2_DROP_ON_MATCH BIT_31 889 #define GEM_COMPARE_C_ENABLE BIT_30 890 #define GEM_COMPARE_C (BITS_05 << 25) 891 #define GEM_COMPARE_B_ENABLE BIT_24 892 #define GEM_COMPARE_B (BITS_05 << 19) 893 #define GEM_COMPARE_A_ENABLE BIT_18 894 #define GEM_COMPARE_A (BITS_05 << 13) 895 #define GEM_ETHERTYPE_ENABLE BIT_12 896 #define GEM_ETHERTYPE_REG_INDEX (BITS_03 << 9) 897 #define GEM_VLAN_ENABLE BIT_08 898 #define GEM_VLAN_PRIORITY (BITS_03 << 4) 899 900 #define GEM_COMPARE_C_SHIFT 25 901 #define GEM_COMPARE_B_SHIFT 19 902 #define GEM_COMPARE_A_SHIFT 13 903 #define GEM_ETHERTYPE_REG_INDEX_SHIFT 9 904 #define GEM_VLAN_PRIORITY_SHIFT 4 905 906 /* General MAC TX Schedule Control register bit definitions */ 907 908 #define GEM_TX_SCHED_Q3 (BIT_06 | BIT_07) 909 #define GEM_TX_SCHED_Q2 (BIT_04 | BIT_05) 910 #define GEM_TX_SCHED_Q1 (BIT_02 | BIT_03) 911 #define GEM_TX_SCHED_Q0 (BIT_00 | BIT_01) 912 913 /* General MAC TX Bandwidth Rate Limit Queue 0 to 3 register bit definitions */ 914 915 #define GEM_DWRR_ETS_WEIGHT_Q3 (BITS_08 << 24) 916 #define GEM_DWRR_ETS_WEIGHT_Q2 (BITS_08 << 16) 917 #define GEM_DWRR_ETS_WEIGHT_Q1 (BITS_08 << 8) 918 #define GEM_DWRR_ETS_WEIGHT_Q0 BITS_08 919 920 /* General MAC TX Queue Segment Alloc Queue 0 to 3 register bit definitions */ 921 922 #define GEM_SEGMENT_ALLOC_Q3 (BIT_12 | BIT_13 | BIT_14) 923 #define GEM_SEGMENT_ALLOC_Q2 (BIT_08 | BIT_09 | BIT_10) 924 #define GEM_SEGMENT_ALLOC_Q1 (BIT_04 | BIT_05 | BIT_06) 925 #define GEM_SEGMENT_ALLOC_Q0 (BIT_00 | BIT_01 | BIT_02) 926 927 /* General MAC Screening Type 2 Ethertype Reg 0 register bit definitions */ 928 929 #define GEM_COMPARE_VALUE BITS_16 930 931 /* General MAC Type 2 Compare 0 Word 0 register bit definitions */ 932 /* eMAC Type 2 Compare 0 Word 0 register bit definitions */ 933 /* eMAC Type 2 Compare 1 Word 0 register bit definitions */ 934 /* eMAC Type 2 Compare 2 Word 0 register bit definitions */ 935 /* eMAC Type 2 Compare 3 Word 0 register bit definitions */ 936 /* eMAC Type 2 Compare 4 Word 0 register bit definitions */ 937 /* eMAC Type 2 Compare 5 Word 0 register bit definitions */ 938 939 #define GEM_W0_COMPARE_VALUE (BITS_16 << 16) 940 #define GEM_W0_MASK_VALUE BITS_16 941 942 /* General MAC Type 2 Compare 0 Word 1 register bit definitions */ 943 /* eMAC Type 2 Compare 0 Word 1 register bit definitions */ 944 /* eMAC Type 2 Compare 1 Word 1 register bit definitions */ 945 /* eMAC Type 2 Compare 2 Word 1 register bit definitions */ 946 /* eMAC Type 2 Compare 3 Word 1 register bit definitions */ 947 /* eMAC Type 2 Compare 4 Word 1 register bit definitions */ 948 /* eMAC Type 2 Compare 5 Word 1 register bit definitions */ 949 950 #define GEM_COMPARE_VLAN_ID BIT_10 951 #define GEM_DISABLE_MASK BIT_09 952 #define GEM_COMPARE_OFFSET (BIT_07 | BIT_08) 953 #define GEM_COMPARE_S_TAG BIT_07 954 #define GEM_OFFSET_VALUE BITS_07 955 956 #define GEM_COMPARE_OFFSET_SHIFT 7 957 958 /* General MAC Enst Start Time Queue 0 register bit definitions */ 959 /* General MAC Enst Start Time Queue 1 register bit definitions */ 960 /* General MAC Enst Start Time Queue 2 register bit definitions */ 961 /* General MAC Enst Start Time Queue 3 register bit definitions */ 962 /* eMAC Enst Start Time register bit definitions */ 963 964 #define GEM_START_TIME_SEC (BIT_30 | BIT_31) 965 #define GEM_START_TIME_NSEC BITS_30 966 967 /* General MAC Enst Start Time Queue 0 register bit definitions */ 968 /* General MAC Enst Start Time Queue 1 register bit definitions */ 969 /* General MAC Enst Start Time Queue 2 register bit definitions */ 970 /* General MAC Enst Start Time Queue 3 register bit definitions */ 971 /* General MAC Enst Off Time Queue 0 register bit definitions */ 972 /* General MAC Enst Off Time Queue 1 register bit definitions */ 973 /* General MAC Enst Off Time Queue 2 register bit definitions */ 974 /* General MAC Enst Off Time Queue 3 register bit definitions */ 975 /* eMAC Enst Start Time register bit definitions */ 976 /* eMAC Enst Off Time register bit definitions */ 977 978 #define GEM_ON_OFF_TIME BITS_17 979 980 /* General MAC Enst Control register bit definitions */ 981 /* eMAC Enst Control register bit definitions */ 982 983 #define GEM_ENST_DISABLE_Q_3 BIT_19 984 #define GEM_ENST_DISABLE_Q_2 BIT_18 985 #define GEM_ENST_DISABLE_Q_1 BIT_17 986 #define GEM_ENST_DISABLE_Q_0 BIT_16 987 #define GEM_ENST_ENABLE_Q_3 BIT_03 988 #define GEM_ENST_ENABLE_Q_2 BIT_02 989 #define GEM_ENST_ENABLE_Q_1 BIT_01 990 #define GEM_ENST_ENABLE_Q_0 BIT_00 991 992 /* General MAC MMSL Control register bit definitions */ 993 994 #define GEM_MMSL_DEBUG_MODE BIT_06 995 #define GEM_ROUTE_RX_TO_PMAC BIT_05 996 #define GEM_RESTART_VER BIT_04 997 #define GEM_PRE_ENABLE BIT_03 998 #define GEM_VERIFY_DISABLE BIT_02 999 #define GEM_ADD_FRAG_SIZE (BIT_00 | BIT_01) 1000 1001 /* General MAC MMSL Status register bit definitions */ 1002 1003 #define GEM_SMD_ERROR BIT_10 1004 #define GEM_FRER_COUNT_ERR BIT_09 1005 #define GEM_SMDC_ERROR BIT_08 1006 #define GEM_SMDS_ERROR BIT_07 1007 #define GEM_RCV_V_ERROR BIT_06 1008 #define GEM_RCV_R_ERROR BIT_05 1009 #define GEM_VERIFY_STATUS (BIT_02 | BIT_03 | BIT_04) 1010 #define GEM_RESPOND_STATUS BIT_01 1011 #define GEM_PRE_ACTIVE BIT_00 1012 1013 #define GEM_VERIFY_STATUS_SHIFT 2 1014 1015 #define GEM_VERIFY_INIT ((uint32_t)(0x00UL)) 1016 #define GEM_VERIFY_IDLE ((uint32_t)(0x01UL)) 1017 #define GEM_VERIFY_SEND ((uint32_t)(0x02UL)) 1018 #define GEM_VERIFY_WAIT ((uint32_t)(0x03UL)) 1019 #define GEM_VERIFY_DONE_OK ((uint32_t)(0x04UL)) 1020 #define GEM_VERIFY_DONE_FAIL ((uint32_t)(0x05UL)) 1021 1022 /* General MAC MMSL Error Stats register bit definitions */ 1023 1024 #define GEM_SMD_ERR_COUNT (BITS_08 << 16) 1025 #define GEM_ASS_ERR_COUNT BITS_08 1026 1027 #define GEM_SMD_ERR_COUNT_SHIFT 16 1028 1029 /* General MAC MMSL Ass OK Count register bit definitions */ 1030 1031 #define GEM_ASS_OK_COUNT BITS_17 1032 1033 /* General MAC MMSL Frag Count RX register bit definitions */ 1034 /* General MAC MMSL Frag Count TX register bit definitions */ 1035 1036 #define GEM_FRAG_COUNT BITS_17 1037 1038 /* General MAC MMSL Interrupt Status register bit definitions */ 1039 /* General MAC MMSL Interrupt Enable register bit definitions */ 1040 /* General MAC MMSL Interrupt Disable register bit definitions */ 1041 /* General MAC MMSL Interrupt Mask register bit definitions */ 1042 1043 #define GEM_INT_SMD_ERROR BIT_05 1044 #define GEM_INT_FRER_COUNT_ERR BIT_04 1045 #define GEM_INT_SMDC_ERROR BIT_03 1046 #define GEM_INT_SMDS_ERROR BIT_02 1047 #define GEM_INT_RCV_V_ERROR BIT_01 1048 #define GEM_INT_RCV_R_ERROR BIT_00 1049 1050 #ifdef __cplusplus 1051 } 1052 #endif 1053 1054 #endif /* MSS_ETHERNET_MAC_REGS_H_ */ 1055 1056 1057 1058
