1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_DSU_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_DSU_COMPONENT_FIXUP_H_ 9 10 /* -------- DSU_CTRL : (DSU Offset: 0x00) ( /W 8) Control -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint8_t :1; /*!< bit: 1 Reserved */ 16 uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Code */ 17 uint8_t MBIST:1; /*!< bit: 3 Memory built-in self-test */ 18 uint8_t CE:1; /*!< bit: 4 Chip-Erase */ 19 uint8_t :1; /*!< bit: 5 Reserved */ 20 uint8_t ARR:1; /*!< bit: 6 Auxiliary Row Read */ 21 uint8_t SMSA:1; /*!< bit: 7 Start Memory Stream Access */ 22 } bit; /*!< Structure used for bit access */ 23 uint8_t reg; /*!< Type used for register access */ 24 } DSU_CTRL_Type; 25 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 26 27 /* -------- DSU_STATUSA : (DSU Offset: 0x01) (R/W 8) Status A -------- */ 28 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 29 typedef union { 30 struct { 31 uint8_t DONE:1; /*!< bit: 0 Done */ 32 uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */ 33 uint8_t BERR:1; /*!< bit: 2 Bus Error */ 34 uint8_t FAIL:1; /*!< bit: 3 Failure */ 35 uint8_t PERR:1; /*!< bit: 4 Protection Error */ 36 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 37 } bit; /*!< Structure used for bit access */ 38 uint8_t reg; /*!< Type used for register access */ 39 } DSU_STATUSA_Type; 40 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 41 42 /* -------- DSU_STATUSB : (DSU Offset: 0x02) ( R/ 8) Status B -------- */ 43 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 44 typedef union { 45 struct { 46 uint8_t PROT:1; /*!< bit: 0 Protected */ 47 uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */ 48 uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */ 49 uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */ 50 uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */ 51 uint8_t CELCK:1; /*!< bit: 5 Chip Erase Locked */ 52 uint8_t CEHL:1; /*!< bit: 6 Chip Erase Hard Locked */ 53 uint8_t :1; /*!< bit: 7 Reserved */ 54 } bit; /*!< Structure used for bit access */ 55 struct { 56 uint8_t :2; /*!< bit: 0.. 1 Reserved */ 57 uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */ 58 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 59 } vec; /*!< Structure used for vec access */ 60 uint8_t reg; /*!< Type used for register access */ 61 } DSU_STATUSB_Type; 62 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 63 64 /* -------- DSU_ADDR : (DSU Offset: 0x04) (R/W 32) Address -------- */ 65 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 66 typedef union { 67 struct { 68 uint32_t AMOD:2; /*!< bit: 0.. 1 Access Mode */ 69 uint32_t ADDR:30; /*!< bit: 2..31 Address */ 70 } bit; /*!< Structure used for bit access */ 71 uint32_t reg; /*!< Type used for register access */ 72 } DSU_ADDR_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 /* -------- DSU_LENGTH : (DSU Offset: 0x08) (R/W 32) Length -------- */ 76 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 77 typedef union { 78 struct { 79 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 80 uint32_t LENGTH:30; /*!< bit: 2..31 Length */ 81 } bit; /*!< Structure used for bit access */ 82 uint32_t reg; /*!< Type used for register access */ 83 } DSU_LENGTH_Type; 84 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 85 86 /* -------- DSU_DATA : (DSU Offset: 0x0C) (R/W 32) Data -------- */ 87 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 88 typedef union { 89 struct { 90 uint32_t DATA:32; /*!< bit: 0..31 Data */ 91 } bit; /*!< Structure used for bit access */ 92 uint32_t reg; /*!< Type used for register access */ 93 } DSU_DATA_Type; 94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 /* -------- DSU_DCC : (DSU Offset: 0x10) (R/W 32) Debug Communication Channel n -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint32_t DATA:32; /*!< bit: 0..31 Data */ 101 } bit; /*!< Structure used for bit access */ 102 uint32_t reg; /*!< Type used for register access */ 103 } DSU_DCC_Type; 104 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 105 106 /* -------- DSU_DID : (DSU Offset: 0x18) ( R/ 32) Device Identification -------- */ 107 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 108 typedef union { 109 struct { 110 uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */ 111 uint32_t REVISION:4; /*!< bit: 8..11 Revision Number */ 112 uint32_t DIE:4; /*!< bit: 12..15 Die Number */ 113 uint32_t SERIES:6; /*!< bit: 16..21 Series */ 114 uint32_t :1; /*!< bit: 22 Reserved */ 115 uint32_t FAMILY:5; /*!< bit: 23..27 Family */ 116 uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */ 117 } bit; /*!< Structure used for bit access */ 118 uint32_t reg; /*!< Type used for register access */ 119 } DSU_DID_Type; 120 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 121 122 /* -------- DSU_CFG : (DSU Offset: 0x1C) (R/W 32) Configuration -------- */ 123 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 124 typedef union { 125 struct { 126 uint32_t LQOS:2; /*!< bit: 0.. 1 Latency Quality Of Service */ 127 uint32_t DCCDMALEVEL:2; /*!< bit: 2.. 3 DMA Trigger Level */ 128 uint32_t ETBRAMEN:1; /*!< bit: 4 Trace Control */ 129 uint32_t :27; /*!< bit: 5..31 Reserved */ 130 } bit; /*!< Structure used for bit access */ 131 uint32_t reg; /*!< Type used for register access */ 132 } DSU_CFG_Type; 133 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 134 135 /* -------- DSU_DCFG : (DSU Offset: 0xF0) (R/W 32) Device Configuration -------- */ 136 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 137 typedef union { 138 struct { 139 uint32_t DCFG:32; /*!< bit: 0.. 32 Device Configuration */ 140 } bit; /*!< Structure used for bit access */ 141 uint32_t reg; /*!< Type used for register access */ 142 } DSU_DCFG_Type; 143 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 144 145 /* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) ( R/ 32) CoreSight ROM Table Entry 0 -------- */ 146 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 147 typedef union { 148 struct { 149 uint32_t EPRES:1; /*!< bit: 0 Entry Present */ 150 uint32_t FMT:1; /*!< bit: 1 Format */ 151 uint32_t :10; /*!< bit: 2..11 Reserved */ 152 uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */ 153 } bit; /*!< Structure used for bit access */ 154 uint32_t reg; /*!< Type used for register access */ 155 } DSU_ENTRY0_Type; 156 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 157 158 /* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) ( R/ 32) CoreSight ROM Table Entry 1 -------- */ 159 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 160 typedef union { 161 uint32_t reg; /*!< Type used for register access */ 162 } DSU_ENTRY1_Type; 163 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 164 165 /* -------- DSU_END : (DSU Offset: 0x1008) ( R/ 32) CoreSight ROM Table End -------- */ 166 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 167 typedef union { 168 struct { 169 uint32_t END:32; /*!< bit: 0..31 End Marker */ 170 } bit; /*!< Structure used for bit access */ 171 uint32_t reg; /*!< Type used for register access */ 172 } DSU_END_Type; 173 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 174 175 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) ( R/ 32) CoreSight ROM Table Memory Type -------- */ 176 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 177 typedef union { 178 struct { 179 uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */ 180 uint32_t :31; /*!< bit: 1..31 Reserved */ 181 } bit; /*!< Structure used for bit access */ 182 uint32_t reg; /*!< Type used for register access */ 183 } DSU_MEMTYPE_Type; 184 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 185 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) ( R/ 32) Peripheral Identification 4 -------- */ 186 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 187 typedef union { 188 struct { 189 uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */ 190 uint32_t FKBC:4; /*!< bit: 4.. 7 4KB count */ 191 uint32_t :24; /*!< bit: 8..31 Reserved */ 192 } bit; /*!< Structure used for bit access */ 193 uint32_t reg; /*!< Type used for register access */ 194 } DSU_PID4_Type; 195 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 196 197 /* -------- DSU_PID5 : (DSU Offset: 0x1FD4) ( R/ 32) Peripheral Identification 5 -------- */ 198 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 199 typedef union { 200 uint32_t reg; /*!< Type used for register access */ 201 } DSU_PID5_Type; 202 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 203 204 /* -------- DSU_PID6 : (DSU Offset: 0x1FD8) ( R/ 32) Peripheral Identification 6 -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 uint32_t reg; /*!< Type used for register access */ 208 } DSU_PID6_Type; 209 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 210 211 /* -------- DSU_PID7 : (DSU Offset: 0x1FDC) ( R/ 32) Peripheral Identification 7 -------- */ 212 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 213 typedef union { 214 uint32_t reg; /*!< Type used for register access */ 215 } DSU_PID7_Type; 216 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 217 218 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) ( R/ 32) Peripheral Identification 0 -------- */ 219 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 220 typedef union { 221 struct { 222 uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */ 223 uint32_t :24; /*!< bit: 8..31 Reserved */ 224 } bit; /*!< Structure used for bit access */ 225 uint32_t reg; /*!< Type used for register access */ 226 } DSU_PID0_Type; 227 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 228 229 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) ( R/ 32) Peripheral Identification 1 -------- */ 230 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 231 typedef union { 232 struct { 233 uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */ 234 uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */ 235 uint32_t :24; /*!< bit: 8..31 Reserved */ 236 } bit; /*!< Structure used for bit access */ 237 uint32_t reg; /*!< Type used for register access */ 238 } DSU_PID1_Type; 239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 240 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) ( R/ 32) Peripheral Identification 2 -------- */ 241 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 242 typedef union { 243 struct { 244 uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */ 245 uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */ 246 uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */ 247 uint32_t :24; /*!< bit: 8..31 Reserved */ 248 } bit; /*!< Structure used for bit access */ 249 uint32_t reg; /*!< Type used for register access */ 250 } DSU_PID2_Type; 251 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 252 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) ( R/ 32) Peripheral Identification 3 -------- */ 253 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 254 typedef union { 255 struct { 256 uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */ 257 uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */ 258 uint32_t :24; /*!< bit: 8..31 Reserved */ 259 } bit; /*!< Structure used for bit access */ 260 uint32_t reg; /*!< Type used for register access */ 261 } DSU_PID3_Type; 262 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 263 264 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) ( R/ 32) Component Identification 0 -------- */ 265 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 266 typedef union { 267 struct { 268 uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */ 269 uint32_t :24; /*!< bit: 8..31 Reserved */ 270 } bit; /*!< Structure used for bit access */ 271 uint32_t reg; /*!< Type used for register access */ 272 } DSU_CID0_Type; 273 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 274 275 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) ( R/ 32) Component Identification 1 -------- */ 276 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 277 typedef union { 278 struct { 279 uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */ 280 uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */ 281 uint32_t :24; /*!< bit: 8..31 Reserved */ 282 } bit; /*!< Structure used for bit access */ 283 uint32_t reg; /*!< Type used for register access */ 284 } DSU_CID1_Type; 285 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 286 287 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) ( R/ 32) Component Identification 2 -------- */ 288 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 289 typedef union { 290 struct { 291 uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */ 292 uint32_t :24; /*!< bit: 8..31 Reserved */ 293 } bit; /*!< Structure used for bit access */ 294 uint32_t reg; /*!< Type used for register access */ 295 } DSU_CID2_Type; 296 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 297 298 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) ( R/ 32) Component Identification 3 -------- */ 299 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 300 typedef union { 301 struct { 302 uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */ 303 uint32_t :24; /*!< bit: 8..31 Reserved */ 304 } bit; /*!< Structure used for bit access */ 305 uint32_t reg; /*!< Type used for register access */ 306 } DSU_CID3_Type; 307 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 308 309 /** \brief DSU hardware registers */ 310 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 311 typedef struct { 312 __O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */ 313 __IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */ 314 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */ 315 RoReg8 Reserved1[0x1]; 316 __IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */ 317 __IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */ 318 __IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */ 319 __IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */ 320 __I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */ 321 __IO DSU_CFG_Type CFG; /**< \brief Offset: 0x001C (R/W 32) Configuration */ 322 RoReg8 Reserved2[0xD0]; 323 __IO DSU_DCFG_Type DSU_DCFG[2]; /**< Offset: 0xF0 (R/W 32) Device Configuration */ 324 RoReg8 Reserved3[0xF08]; 325 __I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */ 326 __I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */ 327 __I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Table End */ 328 RoReg8 Reserved4[0xFC0]; 329 __I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */ 330 __I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ 331 __I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ 332 __I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */ 333 __I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */ 334 __I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ 335 __I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ 336 __I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ 337 __I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ 338 __I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */ 339 __I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */ 340 __I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */ 341 __I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */ 342 } Dsu; 343 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 344 345 #endif /* _MICROCHIP_PIC32CXSG_DSU_COMPONENT_FIXUP_H_ */ 346
