Searched refs:EN_SET (Results 1 – 6 of 6) sorted by relevance
18 …__IOM uint32_t EN_SET; /*!< (@ 0x00000004) Individual interrupt enable set … member
322 MEC_ECIA0->GIRQ[0].EN_SET = UINT32_MAX; in enable_girq_direct_bitmap()453 MEC_ECIA0->GIRQ[gidx].EN_SET = bitmap; in mec_hal_girq_bm_en()519 MEC_ECIA0->GIRQ[gidx].EN_SET = MEC_BIT(gpos); in mec_hal_girq_ctrl()
100 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].EN_SET = MEC_BIT(MEC_ESPI_VW_CHEN_CHG_GIRQ19_POS); in mec_hal_espi_vw_en_ien()177 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_SET = MEC_BIT(bitpos); in mec_hal_espi_vw_ct_girq_ctrl()184 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_SET = MEC_BIT(bitpos); in mec_hal_espi_vw_ct_girq_ctrl()196 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_SET = UINT32_MAX; in mec_hal_espi_vw_ct_girq_ctrl_all()197 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_SET = UINT32_MAX; in mec_hal_espi_vw_ct_girq_ctrl_all()373 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_SET = regval << bitpos; in mec_hal_espi_vw_ct_group_girq_ctrl()380 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_SET = regval << bitpos; in mec_hal_espi_vw_ct_group_girq_ctrl()
347 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_SET = 0x0fffffffu; in mec_hal_espi_init()348 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_SET = 0x0000ffffu; in mec_hal_espi_init()387 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].EN_SET = girq_en; in mec_hal_espi_init()
1078 MEC_ECIA0->GIRQ[girq_idx].EN_SET = MEC_BIT(port_pin_pos); in mec_hal_gpio_port_pin_ia_enable()
764 __IOM uint32_t EN_SET; /* R/W1S Write 1 to set enable(s) */ member
