Searched refs:EN_CLR (Results 1 – 5 of 5) sorted by relevance
21 …__IOM uint32_t EN_CLR; /*!< (@ 0x0000000C) Individual interrupt enable clea… member
403 MEC_ECIA0->GIRQ[i].EN_CLR = UINT32_MAX; in mec_hal_ecia_init()455 MEC_ECIA0->GIRQ[gidx].EN_CLR = bitmap; in mec_hal_girq_bm_en()521 MEC_ECIA0->GIRQ[gidx].EN_CLR = MEC_BIT(gpos); in mec_hal_girq_ctrl()
102 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ19].EN_CLR = MEC_BIT(MEC_ESPI_VW_CHEN_CHG_GIRQ19_POS); in mec_hal_espi_vw_en_ien()179 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_CLR = MEC_BIT(bitpos); in mec_hal_espi_vw_ct_girq_ctrl()186 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_CLR = MEC_BIT(bitpos); in mec_hal_espi_vw_ct_girq_ctrl()199 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_CLR = UINT32_MAX; in mec_hal_espi_vw_ct_girq_ctrl_all()200 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_CLR = UINT32_MAX; in mec_hal_espi_vw_ct_girq_ctrl_all()375 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ24].EN_CLR = regval << bitpos; in mec_hal_espi_vw_ct_group_girq_ctrl()382 MEC_ECIA0->GIRQ[MEC_GIRQ_IDX_GIRQ25].EN_CLR = regval << bitpos; in mec_hal_espi_vw_ct_group_girq_ctrl()
1080 MEC_ECIA0->GIRQ[girq_idx].EN_CLR = MEC_BIT(port_pin_pos); in mec_hal_gpio_port_pin_ia_enable()
766 __IOM uint32_t EN_CLR; /* R/W1S Write 1 to clear enable(s) */ member
