1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_DAC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_DAC_COMPONENT_FIXUP_H_ 9 10 /* -------- DAC_CTRLA : (DAC Offset: 0x00) (R/W 8) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint8_t ENABLE:1; /*!< bit: 1 Enable DAC Controller */ 16 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 17 } bit; /*!< Structure used for bit access */ 18 uint8_t reg; /*!< Type used for register access */ 19 } DAC_CTRLA_Type; 20 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 21 22 /* -------- DAC_CTRLB : (DAC Offset: 0x01) (R/W 8) Control B -------- */ 23 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 24 typedef union { 25 struct { 26 uint8_t DIFF:1; /*!< bit: 0 Differential mode enable */ 27 uint8_t REFSEL:2; /*!< bit: 1.. 2 Reference Selection for DAC0/1 */ 28 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 29 } bit; /*!< Structure used for bit access */ 30 uint8_t reg; /*!< Type used for register access */ 31 } DAC_CTRLB_Type; 32 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 33 34 /* -------- DAC_EVCTRL : (DAC Offset: 0x02) (R/W 8) Event Control -------- */ 35 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 36 typedef union { 37 struct { 38 uint8_t STARTEI0:1; /*!< bit: 0 Start Conversion Event Input DAC 0 */ 39 uint8_t STARTEI1:1; /*!< bit: 1 Start Conversion Event Input DAC 1 */ 40 uint8_t EMPTYEO0:1; /*!< bit: 2 Data Buffer Empty Event Output DAC 0 */ 41 uint8_t EMPTYEO1:1; /*!< bit: 3 Data Buffer Empty Event Output DAC 1 */ 42 uint8_t INVEI0:1; /*!< bit: 4 Enable Invertion of DAC 0 input event */ 43 uint8_t INVEI1:1; /*!< bit: 5 Enable Invertion of DAC 1 input event */ 44 uint8_t :1; /*!< bit: 6 Deprecated */ 45 uint8_t :1; /*!< bit: 7 Deprecated */ 46 } bit; /*!< Structure used for bit access */ 47 struct { 48 uint8_t STARTEI:2; /*!< bit: 0.. 1 Start Conversion Event Input DAC x */ 49 uint8_t EMPTYEO:2; /*!< bit: 2.. 3 Data Buffer Empty Event Output DAC x */ 50 uint8_t INVEI:2; /*!< bit: 4.. 5 Enable Invertion of DAC x input event */ 51 uint8_t :2; /*!< bit: 6.. 7 Deprecated */ 52 } vec; /*!< Structure used for vec access */ 53 uint8_t reg; /*!< Type used for register access */ 54 } DAC_EVCTRL_Type; 55 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 56 57 /* -------- DAC_INTENCLR : (DAC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */ 58 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 59 typedef union { 60 struct { 61 uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ 62 uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ 63 uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ 64 uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ 65 uint8_t :1; /*!< bit: 4 Deprecated */ 66 uint8_t :1; /*!< bit: 5 Deprecated */ 67 uint8_t :1; /*!< bit: 6 Deprecated */ 68 uint8_t :1; /*!< bit: 7 Deprecated */ 69 } bit; /*!< Structure used for bit access */ 70 struct { 71 uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ 72 uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ 73 uint8_t :2; /*!< bit: 4.. 5 Deprecated */ 74 uint8_t :2; /*!< bit: 6.. 7 Deprecated */ 75 } vec; /*!< Structure used for vec access */ 76 uint8_t reg; /*!< Type used for register access */ 77 } DAC_INTENCLR_Type; 78 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 79 80 /* -------- DAC_INTENSET : (DAC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */ 81 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 82 typedef union { 83 struct { 84 uint8_t UNDERRUN0:1; /*!< bit: 0 Underrun 0 Interrupt Enable */ 85 uint8_t UNDERRUN1:1; /*!< bit: 1 Underrun 1 Interrupt Enable */ 86 uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty Interrupt Enable */ 87 uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty Interrupt Enable */ 88 uint8_t :1; /*!< bit: 4 Deprecated */ 89 uint8_t :1; /*!< bit: 5 Deprecated */ 90 uint8_t :1; /*!< bit: 6 Deprecated */ 91 uint8_t :1; /*!< bit: 7 Deprecated */ 92 } bit; /*!< Structure used for bit access */ 93 struct { 94 uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Underrun x Interrupt Enable */ 95 uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty Interrupt Enable */ 96 uint8_t :2; /*!< bit: 4.. 5 Deprecated */ 97 uint8_t :2; /*!< bit: 6.. 7 Deprecated */ 98 } vec; /*!< Structure used for vec access */ 99 uint8_t reg; /*!< Type used for register access */ 100 } DAC_INTENSET_Type; 101 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 /* -------- DAC_INTFLAG : (DAC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */ 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 105 typedef union { // __I to avoid read-modify-write on write-to-clear register 106 struct { 107 __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */ 108 __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */ 109 __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */ 110 __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */ 111 __I uint8_t :1; /*!< bit: 4 Deprecated */ 112 __I uint8_t :1; /*!< bit: 5 Deprecated */ 113 __I uint8_t :1; /*!< bit: 6 Deprecated */ 114 __I uint8_t :1; /*!< bit: 7 Deprecated */ 115 } bit; /*!< Structure used for bit access */ 116 struct { 117 __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */ 118 __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */ 119 __I uint8_t :2; /*!< bit: 4.. 5 Deprecated */ 120 __I uint8_t :2; /*!< bit: 6.. 7 Deprecated */ 121 } vec; /*!< Structure used for vec access */ 122 uint8_t reg; /*!< Type used for register access */ 123 } DAC_INTFLAG_Type; 124 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 125 126 /* -------- DAC_STATUS : (DAC Offset: 0x07) ( R/ 8) Status -------- */ 127 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 128 typedef union { 129 struct { 130 uint8_t READY0:1; /*!< bit: 0 DAC 0 Startup Ready */ 131 uint8_t READY1:1; /*!< bit: 1 DAC 1 Startup Ready */ 132 uint8_t EOC0:1; /*!< bit: 2 DAC 0 End of Conversion */ 133 uint8_t EOC1:1; /*!< bit: 3 DAC 1 End of Conversion */ 134 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 135 } bit; /*!< Structure used for bit access */ 136 struct { 137 uint8_t READY:2; /*!< bit: 0.. 1 DAC x Startup Ready */ 138 uint8_t EOC:2; /*!< bit: 2.. 3 DAC x End of Conversion */ 139 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 140 } vec; /*!< Structure used for vec access */ 141 uint8_t reg; /*!< Type used for register access */ 142 } DAC_STATUS_Type; 143 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 144 145 /* -------- DAC_SYNCBUSY : (DAC Offset: 0x08) ( R/ 32) Synchronization Busy -------- */ 146 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 147 typedef union { 148 struct { 149 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 150 uint32_t ENABLE:1; /*!< bit: 1 DAC Enable Status */ 151 uint32_t DATA0:1; /*!< bit: 2 Data DAC 0 */ 152 uint32_t DATA1:1; /*!< bit: 3 Data DAC 1 */ 153 uint32_t DATABUF0:1; /*!< bit: 4 Data Buffer DAC 0 */ 154 uint32_t DATABUF1:1; /*!< bit: 5 Data Buffer DAC 1 */ 155 uint32_t :26; /*!< bit: 6..31 Reserved */ 156 } bit; /*!< Structure used for bit access */ 157 struct { 158 uint32_t :2; /*!< bit: 0.. 1 Reserved */ 159 uint32_t DATA:2; /*!< bit: 2.. 3 Data DAC x */ 160 uint32_t DATABUF:2; /*!< bit: 4.. 5 Data Buffer DAC x */ 161 uint32_t :26; /*!< bit: 6..31 Reserved */ 162 } vec; /*!< Structure used for vec access */ 163 uint32_t reg; /*!< Type used for register access */ 164 } DAC_SYNCBUSY_Type; 165 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 166 167 /* -------- DAC_DACCTRL : (DAC Offset: 0x0C) (R/W 16) DAC n Control -------- */ 168 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 169 typedef union { 170 struct { 171 uint16_t LEFTADJ:1; /*!< bit: 0 Left Adjusted Data */ 172 uint16_t ENABLE:1; /*!< bit: 1 Enable DAC0 */ 173 uint16_t CCTRL:2; /*!< bit: 2.. 3 Current Control */ 174 uint16_t :1; /*!< bit: 4 Reserved */ 175 uint16_t FEXT:1; /*!< bit: 5 Standalone Filter */ 176 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 177 uint16_t DITHER:1; /*!< bit: 7 Dithering Mode */ 178 uint16_t REFRESH:4; /*!< bit: 8..11 Refresh period */ 179 uint16_t :1; /*!< bit: 12 Reserved */ 180 uint16_t OSR:3; /*!< bit: 13..15 Sampling Rate */ 181 } bit; /*!< Structure used for bit access */ 182 uint16_t reg; /*!< Type used for register access */ 183 } DAC_DACCTRL_Type; 184 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 185 186 /* -------- DAC_DATA : (DAC Offset: 0x10) ( /W 16) DAC n Data -------- */ 187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 188 typedef union { 189 struct { 190 uint16_t DATA:16; /*!< bit: 0..15 DAC0 Data */ 191 } bit; /*!< Structure used for bit access */ 192 uint16_t reg; /*!< Type used for register access */ 193 } DAC_DATA_Type; 194 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 195 196 /* -------- DAC_DATABUF : (DAC Offset: 0x14) ( /W 16) DAC n Data Buffer -------- */ 197 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 198 typedef union { 199 struct { 200 uint16_t DATABUF:16; /*!< bit: 0..15 DAC0 Data Buffer */ 201 } bit; /*!< Structure used for bit access */ 202 uint16_t reg; /*!< Type used for register access */ 203 } DAC_DATABUF_Type; 204 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 205 206 /* -------- DAC_DBGCTRL : (DAC Offset: 0x18) (R/W 8) Debug Control -------- */ 207 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 208 typedef union { 209 struct { 210 uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */ 211 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 212 } bit; /*!< Structure used for bit access */ 213 uint8_t reg; /*!< Type used for register access */ 214 } DAC_DBGCTRL_Type; 215 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 216 217 /** \brief DAC hardware registers */ 218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 219 typedef struct { 220 __IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 221 __IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 (R/W 8) Control B */ 222 __IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 8) Event Control */ 223 RoReg8 Reserved1[0x1]; 224 __IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */ 225 __IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */ 226 __IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */ 227 __I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x07 (R/ 8) Status */ 228 __I DAC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x08 (R/ 32) Synchronization Busy */ 229 __IO DAC_DACCTRL_Type DACCTRL[2]; /**< \brief Offset: 0x0C (R/W 16) DAC n Control */ 230 __O DAC_DATA_Type DATA[2]; /**< \brief Offset: 0x10 ( /W 16) DAC n Data */ 231 __O DAC_DATABUF_Type DATABUF[2]; /**< \brief Offset: 0x14 ( /W 16) DAC n Data Buffer */ 232 __IO DAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x18 (R/W 8) Debug Control */ 233 /* RoReg8 Reserved2[0x3]; - Deprecated */ 234 /*__I DAC_RESULT_Type RESULT[2]; - Deprecated */ /**< \brief Offset: 0x1C (R/ 16) Filter Result */ 235 } Dac; 236 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 237 238 #endif /* _MICROCHIP_PIC32CXSG_DAC_COMPONENT_FIXUP_H_ */ 239
