1 /******************************************************************************* 2 * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Register bit offsets and masks definitions for PolarFire SoC(MPFS) MSS QSPI. 7 * 8 * 9 */ 10 #ifndef MSS_QSPI_REGS_H_ 11 #define MSS_QSPI_REGS_H_ 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /******************************************************************************* 18 Register Bit definitions 19 */ 20 #define CTRL_EN 0u 21 #define CTRL_XIP 2u 22 #define CTRL_XIPADDR 3u 23 #define CTRL_CLKIDL 10u 24 #define CTRL_SAMPLE 11u 25 #define CTRL_QMODE0 13u 26 #define CTRL_QMODE12 14u 27 #define CTRL_FLAGSX4 16u 28 #define CTRL_CLKRATE 24u 29 30 #define CTRL_EN_MASK (0x1u << CTRL_EN) 31 #define CTRL_XIP_MASK (0x1u << CTRL_XIP) 32 #define CTRL_XIPADDR_MASK (0x1u << CTRL_XIPADDR) 33 #define CTRL_CLKIDL_MASK (0x1u << CTRL_CLKIDL) 34 #define CTRL_SAMPLE_MASK (0x3u << CTRL_SAMPLE) 35 #define CTRL_QMODE0_MASK (0x1u << CTRL_QMODE0) 36 #define CTRL_QMODE12_MASK (0x3u << CTRL_QMODE12) 37 #define CTRL_FLAGSX4_MASK (0x1u << CTRL_FLAGSX4) 38 #define CTRL_CLKRATE_MASK (0xFu << CTRL_CLKRATE) 39 40 #define CTRL_SAMPLE_SCK (0x0u << CTRL_SAMPLE) 41 #define CTRL_SAMPLE_HCLKF (0x1u << CTRL_SAMPLE) 42 #define CTRL_SAMPLE_HCLKR (0x2u << CTRL_SAMPLE) 43 44 #define FRMS_TBYTES 0u 45 #define FRMS_CBYTES 16u 46 #define FRMS_QSPI 25u 47 #define FRMS_IDLE 26u 48 #define FRMS_FBYTE 30u 49 #define FRMS_FWORD 31u 50 51 #define FRMS_TBYTES_MASK (0xFFFFu << FRMS_TBYTES) 52 #define FRMS_CBYTES_MASK (0x1FFu << FRMS_CBYTES) 53 #define FRMS_QXIP_MASK (0x1u << FRMS_QXIP) 54 #define FRMS_IDLE_MASK (0xFu << FRMS_IDLE) 55 #define FRMS_FBYTE_MASK (0x1u << FRMS_FBYTE) 56 #define FRMS_FWORD_MASK (0x1u << FRMS_FWORD) 57 58 #define INTE_TDONE 0u 59 #define INTE_RDONE 1u 60 #define INTE_RAVLB 2u 61 #define INTE_TAVLB 3u 62 #define INTE_RFEMPTY 4u 63 #define INTE_TFFULL 5u 64 65 #define INTE_TDONE_MASK (0x1u << INTE_TDONE) 66 #define INTE_RDONE_MASK (0x1u << INTE_RDONE) 67 #define INTE_RAVLB_MASK (0x1u << INTE_RAVLB) 68 #define INTE_TAVLB_MASK (0x1u << INTE_TAVLB) 69 #define INTE_RFEMPTY_MASK (0x1u << INTE_RFEMPTY) 70 #define INTE_TFFULL_MASK (0x1u << INTE_TFFULL) 71 72 73 #define STTS_TDONE 0u 74 #define STTS_RDONE 1u 75 #define STTS_RAVLB 2u 76 #define STTS_TAVLB 3u 77 #define STTS_RFEMPTY 4u 78 #define STTS_TFFULL 5u 79 #define STTS_READY 7u 80 #define STTS_FLAGSX4 8u 81 82 #define STTS_TDONE_MASK (0x1u << STTS_TDONE) 83 #define STTS_RDONE_MASK (0x1u << STTS_RDONE) 84 #define STTS_RAVLB_MASK (0x1u << STTS_RAVLB) 85 #define STTS_TAVLB_MASK (0x1u << STTS_TAVLB) 86 #define STTS_RFEMPTY_MASK (0x1u << STTS_RFEMPTY) 87 #define STTS_TFFULL_MASK (0x1u << STTS_TFFULL) 88 #define STTS_READY_MASK (0x1u << STTS_READY) 89 #define STTS_FLAGSX4_MASK (0x1u << STTS_FLAGSX4) 90 91 92 #define RDAT 0u 93 94 #define RDAT_MASK 0xFFu 95 96 #define TDAT 0u 97 98 #define TDAT_MASK 0xFFu 99 100 #define X4RDAT 0u 101 102 #define X4RDAT_MASK 0xFFFFFFFFu 103 104 #define X4TDAT 0u 105 106 #define X4TDAT_MASK 0xFFFFFFFFu 107 108 #define DIRECT_EN_SSEL 0u 109 #define DIRECT_OP_SSEL 1u 110 #define DIRECT_EN_SCLK 2u 111 #define DIRECT_OP_SCLK 3u 112 #define DIRECT_EN_SDO 4u 113 #define DIRECT_OP_SDO 8u 114 #define DIRECT_OP_SDOE 12u 115 #define DIRECT_IP_SDI 16u 116 #define DIRECT_Reserved 20u 117 #define DIRECT_IP_SCLK 21u 118 #define DIRECT_IP_SSEL 22u 119 #define DIRECT_IDLE 23u 120 121 #define DIRECT_EN_SSEL_MASK (0x1u << DIRECT_EN_SSEL) 122 #define DIRECT_OP_SSEL_MASK (0x1u << DIRECT_OP_SSEL) 123 #define DIRECT_EN_SCLK_MASK (0x1u << DIRECT_EN_SCLK) 124 #define DIRECT_OP_SCLK_MASK (0x1u << DIRECT_OP_SCLK) 125 #define DIRECT_EN_SDO_MASK (0xFu << DIRECT_EN_SDO) 126 #define DIRECT_OP_SDO_MASK (0xFu << DIRECT_OP_SDO) 127 #define DIRECT_OP_SDOE_MASK (0xFu << DIRECT_OP_SDOE) 128 #define DIRECT_IP_SDI_MASK (0xFu << DIRECT_IP_SDI) 129 #define DIRECT_Reserved_MASK (0x1u << DIRECT_Reserved) 130 #define DIRECT_IP_SCLK_MASK (0x1u << DIRECT_IP_SCLK) 131 #define DIRECT_IP_SSEL_MASK (0x1u << DIRECT_IP_SSEL) 132 #define DIRECT_IDLE_MASK (0x1u << DIRECT_IDLE) 133 134 135 #define UADDAR 0u 136 #define UADDAR_MASK 0xFFu 137 138 #ifdef __cplusplus 139 } 140 #endif 141 142 #endif /* MSS_QSPI_REGS_H_ */ 143
