1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_PROCHOT_V1_H 7 #define _MEC5_PROCHOT_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief PROCHOT Monitor (MEC_PROCHOT) 15 */ 16 17 typedef struct mec_phot_regs { /*!< (@ 0x40003400) MEC_PROCHOT Structure */ 18 __IM uint32_t CUM_CNT; /*!< (@ 0x00000000) Cumulative count */ 19 __IM uint32_t DUTY_CNT; /*!< (@ 0x00000004) Duty cycle count */ 20 __IOM uint32_t DUTY_PER; /*!< (@ 0x00000008) Duty cycle period */ 21 __IOM uint32_t CTR_STS; /*!< (@ 0x0000000C) Control and status */ 22 __IM uint32_t ASSERT_CNT; /*!< (@ 0x00000010) 16-bit assertion counter (RO) */ 23 __IOM uint32_t ASSERT_CNT_LIM; /*!< (@ 0x00000014) 16-bit assertion counter limit */ 24 } MEC_PHOT_Type; /*!< Size = 24 (0x18) */ 25 26 /** @} */ /* End of group Device_Peripheral_peripherals */ 27 28 /** @addtogroup PosMask_peripherals 29 * @{ 30 */ 31 /* ======================================================== CTR_STS ======================================================== */ 32 #define MEC_PHOT_CTR_STS_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ 33 #define MEC_PHOT_CTR_STS_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 34 #define MEC_PHOT_CTR_STS_PIN_STATE_Pos (1UL) /*!< PIN_STATE (Bit 1) */ 35 #define MEC_PHOT_CTR_STS_PIN_STATE_Msk (0x2UL) /*!< PIN_STATE (Bitfield-Mask: 0x01) */ 36 #define MEC_PHOT_CTR_STS_ASSERT_IEN_Pos (2UL) /*!< ASSERT_IEN (Bit 2) */ 37 #define MEC_PHOT_CTR_STS_ASSERT_IEN_Msk (0x4UL) /*!< ASSERT_IEN (Bitfield-Mask: 0x01) */ 38 #define MEC_PHOT_CTR_STS_PERIOD_IEN_Pos (3UL) /*!< PERIOD_IEN (Bit 3) */ 39 #define MEC_PHOT_CTR_STS_PERIOD_IEN_Msk (0x8UL) /*!< PERIOD_IEN (Bitfield-Mask: 0x01) */ 40 #define MEC_PHOT_CTR_STS_RESET_Pos (4UL) /*!< RESET (Bit 4) */ 41 #define MEC_PHOT_CTR_STS_RESET_Msk (0x10UL) /*!< RESET (Bitfield-Mask: 0x01) */ 42 #define MEC_PHOT_CTR_STS_FILT_EN_Pos (5UL) /*!< FILT_EN (Bit 5) */ 43 #define MEC_PHOT_CTR_STS_FILT_EN_Msk (0x20UL) /*!< FILT_EN (Bitfield-Mask: 0x01) */ 44 #define MEC_PHOT_CTR_STS_ASSERT_STS_Pos (10UL) /*!< ASSERT_STS (Bit 10) */ 45 #define MEC_PHOT_CTR_STS_ASSERT_STS_Msk (0x400UL) /*!< ASSERT_STS (Bitfield-Mask: 0x01) */ 46 #define MEC_PHOT_CTR_STS_PERIOD_STS_Pos (11UL) /*!< PERIOD_STS (Bit 11) */ 47 #define MEC_PHOT_CTR_STS_PERIOD_STS_Msk (0x800UL) /*!< PERIOD_STS (Bitfield-Mask: 0x01) */ 48 49 /** @} */ /* End of group PosMask_peripherals */ 50 51 #endif /* _MEC5_PROCHOT_V1_H */ 52
