Searched refs:CONTROL2 (Results 1 – 2 of 2) sorted by relevance
618 this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK; in MSS_SPI_set_frame_rx_handler()619 this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_SSEND_IRQ_MASK; in MSS_SPI_set_frame_rx_handler()689 this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK; in MSS_SPI_set_slave_tx_frame()690 this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_SSEND_IRQ_MASK; in MSS_SPI_set_slave_tx_frame()830 this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK; in MSS_SPI_set_slave_block_buffers()839 this_spi->hw_reg->CONTROL2 |= C2_ENABLE_SSEND_IRQ_MASK; in MSS_SPI_set_slave_block_buffers()884 this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK; in MSS_SPI_set_cmd_handler()908 this_spi->hw_reg->CONTROL2 |= C2_ENABLE_CMD_IRQ_MASK; in MSS_SPI_set_cmd_handler()1174 this_spi->hw_reg->CONTROL2 &= ~(uint32_t)C2_ENABLE_CMD_IRQ_MASK; in mss_spi_isr()1239 this_spi->hw_reg->CONTROL2 |= C2_ENABLE_CMD_IRQ_MASK; in mss_spi_isr()[all …]
243 volatile uint32_t CONTROL2; member