1 /******************************************************************************* 2 * Copyright 2019-2020 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * Register bit offsets and masks definitions for PolarFire SoC MSS MMUART 7 * 8 */ 9 10 #ifndef MSS_UART_REGS_H_ 11 #define MSS_UART_REGS_H_ 12 13 #ifdef __cplusplus 14 extern "C" { 15 #endif 16 17 /******************************************************************************* 18 Register Bit definitions 19 */ 20 21 /* Line Control register bit definitions */ 22 #define SB 6u /* Set break */ 23 #define DLAB 7u /* Divisor latch access bit */ 24 25 /* Line Control register bit masks */ 26 #define SB_MASK (0x01u << SB) /* Set break */ 27 #define DLAB_MASK (0x01u << DLAB) /* Divisor latch access bit */ 28 29 /* FIFO Control register bit definitions */ 30 #define RXRDY_TXRDYN_EN 0u /* Enable TXRDY and RXRDY signals */ 31 #define CLEAR_RX_FIFO 1u /* Clear receiver FIFO */ 32 #define CLEAR_TX_FIFO 2u /* Clear transmitter FIFO */ 33 #define RDYMODE 3u /* Mode 0 or Mode 1 for TXRDY and RXRDY */ 34 35 /* FIFO Control register bit MASKS */ 36 #define RXRDY_TXRDYN_EN_MASK (0x01u << 0u) /* Enable TXRDY and RXRDY signals */ 37 #define CLEAR_RX_FIFO_MASK (0x01u << 1u) /* Clear receiver FIFO */ 38 #define CLEAR_TX_FIFO_MASK (0x01u << 2u) /* Clear transmitter FIFO */ 39 #define RDYMODE_MASK (0x01u << 3u) /* Mode 0 or Mode 1 for TXRDY and RXRDY */ 40 41 /* Modem Control register bit definitions */ 42 #define LOOP 4u /* Local loopback */ 43 #define RLOOP 5u /* Remote loopback */ 44 #define ECHO 6u /* Automatic echo */ 45 46 /* Modem Control register bit MASKS */ 47 #define LOOP_MASK (0x01u << 4u) /* Local loopback */ 48 #define RLOOP_MASK (0x01u << 5u) /* Remote loopback & Automatic echo*/ 49 #define ECHO_MASK (0x01u << 6u) /* Automatic echo */ 50 51 /* Line Status register bit definitions */ 52 #define DR 0u /* Data ready */ 53 #define THRE 5u /* Transmitter holding register empty */ 54 #define TEMT 6u /* Transmitter empty */ 55 56 /* Line Status register bit MASKS */ 57 #define DR_MASK (0x01u << 0u) /* Data ready */ 58 #define THRE_MASK (0x01u << 5u) /* Transmitter holding register empty */ 59 #define TEMT_MASK (0x01u << 6u) /* Transmitter empty */ 60 61 /* Interrupt Enable register bit definitions */ 62 #define ERBFI 0u /* Enable receiver buffer full interrupt */ 63 #define ETBEI 1u /* Enable transmitter buffer empty interrupt */ 64 #define ELSI 2u /* Enable line status interrupt */ 65 #define EDSSI 3u /* Enable modem status interrupt */ 66 67 /* Interrupt Enable register bit MASKS */ 68 #define ERBFI_MASK (0x01u << 0u) /* Enable receiver buffer full interrupt */ 69 #define ETBEI_MASK (0x01u << 1u) /* Enable transmitter buffer empty interrupt */ 70 #define ELSI_MASK (0x01u << 2u) /* Enable line status interrupt */ 71 #define EDSSI_MASK (0x01u << 3u) /* Enable modem status interrupt */ 72 73 /* Multimode register 0 bit definitions */ 74 #define ELIN 3u /* Enable LIN header detection */ 75 #define ETTG 5u /* Enable transmitter time guard */ 76 #define ERTO 6u /* Enable receiver time-out */ 77 #define EFBR 7u /* Enable fractional baud rate mode */ 78 79 /* Multimode register 0 bit MASKS */ 80 #define ELIN_MASK (0x01u << 3u) /* Enable LIN header detection */ 81 #define ETTG_MASK (0x01u << 5u) /* Enable transmitter time guard */ 82 #define ERTO_MASK (0x01u << 6u) /* Enable receiver time-out */ 83 #define EFBR_MASK (0x01u << 7u) /* Enable fractional baud rate mode */ 84 85 /* Multimode register 1 bit definitions */ 86 #define E_MSB_RX 0u /* MSB / LSB first for receiver */ 87 #define E_MSB_TX 1u /* MSB / LSB first for transmitter */ 88 #define EIRD 2u /* Enable IrDA modem */ 89 #define EIRX 3u /* Input polarity for IrDA modem */ 90 #define EITX 4u /* Output polarity for IrDA modem */ 91 #define EITP 5u /* Output pulse width for IrDA modem */ 92 93 /* Multimode register 1 bit MASKS */ 94 #define E_MSB_RX_MASK (0x01u << 0u) /* MSB / LSB first for receiver */ 95 #define E_MSB_TX_MASK (0x01u << 1u) /* MSB / LSB first for transmitter */ 96 #define EIRD_MASK (0x01u << 2u) /* Enable IrDA modem */ 97 #define EIRX_MASK (0x01u << 3u) /* Input polarity for IrDA modem */ 98 #define EITX_MASK (0x01u << 4u) /* Output polarity for IrDA modem */ 99 #define EITP_MASK (0x01u << 5u) /* Output pulse width for IrDA modem */ 100 101 /* Multimode register 2 bit definitions */ 102 #define EERR 0u /* Enable ERR / NACK during stop time */ 103 #define EAFM 1u /* Enable 9-bit address flag mode */ 104 #define EAFC 2u /* Enable address flag clear */ 105 #define ESWM 3u /* Enable single wire half-duplex mode */ 106 107 /* Multimode register 2 bit MASKS */ 108 #define EERR_MASK (0x01u << 0u) /* Enable ERR / NACK during stop time */ 109 #define EAFM_MASK (0x01u << 1u) /* Enable 9-bit address flag mode */ 110 #define EAFC_MASK (0x01u << 2u) /* Enable address flag clear */ 111 #define ESWM_MASK (0x01u << 3u) /* Enable single wire half-duplex mode */ 112 113 /* Multimode Interrupt Enable register and 114 Multimode Interrupt Identification register definitions */ 115 #define ERTOI 0u /* Enable receiver timeout interrupt */ 116 #define ENACKI 1u /* Enable NACK / ERR interrupt */ 117 #define EPID_PEI 2u /* Enable PID parity error interrupt */ 118 #define ELINBI 3u /* Enable LIN break interrupt */ 119 #define ELINSI 4u /* Enable LIN sync detection interrupt */ 120 121 /* Multimode Interrupt Enable register and 122 Multimode Interrupt Identification register MASKS */ 123 #define ERTOI_MASK (0x01u << 0u) /* Enable receiver timeout interrupt */ 124 #define ENACKI_MASK (0x01u << 1u) /* Enable NACK / ERR interrupt */ 125 #define EPID_PEI_MASK (0x01u << 2u) /* Enable PID parity error interrupt */ 126 #define ELINBI_MASK (0x01u << 3u) /* Enable LIN break interrupt */ 127 #define ELINSI_MASK (0x01u << 4u) /* Enable LIN sync detection interrupt */ 128 129 #ifdef __cplusplus 130 } 131 #endif 132 133 #endif /* MSS_UART_REGS_H_ */ 134
