1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_EIC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_EIC_COMPONENT_FIXUP_H_ 9 /* -------- EIC_CTRLA : (EIC Offset: 0x00) (R/W 8) Control A -------- */ 10 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 11 typedef union { 12 struct { 13 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 14 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 15 uint8_t :2; /*!< bit: 2.. 3 Reserved */ 16 uint8_t CKSEL:1; /*!< bit: 4 Clock Selection */ 17 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 18 } bit; /*!< Structure used for bit access */ 19 uint8_t reg; /*!< Type used for register access */ 20 } EIC_CTRLA_Type; 21 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 22 23 /* -------- EIC_NMICTRL : (EIC Offset: 0x01) (R/W 8) Non-Maskable Interrupt Control -------- */ 24 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 25 typedef union { 26 struct { 27 uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense Configuration */ 28 uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */ 29 uint8_t NMIASYNCH:1; /*!< bit: 4 Asynchronous Edge Detection Mode */ 30 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 31 } bit; /*!< Structure used for bit access */ 32 uint8_t reg; /*!< Type used for register access */ 33 } EIC_NMICTRL_Type; 34 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 35 36 /* -------- EIC_NMIFLAG : (EIC Offset: 0x02) (R/W 16) Non-Maskable Interrupt Flag Status and Clear -------- */ 37 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 38 typedef union { 39 struct { 40 uint16_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */ 41 uint16_t :15; /*!< bit: 1..15 Reserved */ 42 } bit; /*!< Structure used for bit access */ 43 uint16_t reg; /*!< Type used for register access */ 44 } EIC_NMIFLAG_Type; 45 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 46 47 /* -------- EIC_SYNCBUSY : (EIC Offset: 0x04) ( R/ 32) Synchronization Busy -------- */ 48 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 49 typedef union { 50 struct { 51 uint32_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Busy Status */ 52 uint32_t ENABLE:1; /*!< bit: 1 Enable Synchronization Busy Status */ 53 uint32_t :30; /*!< bit: 2..31 Reserved */ 54 } bit; /*!< Structure used for bit access */ 55 uint32_t reg; /*!< Type used for register access */ 56 } EIC_SYNCBUSY_Type; 57 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 58 59 /* -------- EIC_EVCTRL : (EIC Offset: 0x08) (R/W 32) Event Control -------- */ 60 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 61 typedef union { 62 struct { 63 uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt Event Output Enable */ 64 uint32_t :16; /*!< bit: 16..31 Reserved */ 65 } bit; /*!< Structure used for bit access */ 66 uint32_t reg; /*!< Type used for register access */ 67 } EIC_EVCTRL_Type; 68 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 69 70 /* -------- EIC_INTENCLR : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Clear -------- */ 71 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 72 typedef union { 73 struct { 74 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */ 75 uint32_t :16; /*!< bit: 16..31 Reserved */ 76 } bit; /*!< Structure used for bit access */ 77 uint32_t reg; /*!< Type used for register access */ 78 } EIC_INTENCLR_Type; 79 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 80 81 /* -------- EIC_INTENSET : (EIC Offset: 0x10) (R/W 32) Interrupt Enable Set -------- */ 82 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 83 typedef union { 84 struct { 85 uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt Enable */ 86 uint32_t :16; /*!< bit: 16..31 Reserved */ 87 } bit; /*!< Structure used for bit access */ 88 uint32_t reg; /*!< Type used for register access */ 89 } EIC_INTENSET_Type; 90 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 91 92 /* -------- EIC_INTFLAG : (EIC Offset: 0x14) (R/W 32) Interrupt Flag Status and Clear -------- */ 93 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 94 typedef union { // __I to avoid read-modify-write on write-to-clear register 95 struct { 96 __I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt */ 97 __I uint32_t :16; /*!< bit: 16..31 Reserved */ 98 } bit; /*!< Structure used for bit access */ 99 uint32_t reg; /*!< Type used for register access */ 100 } EIC_INTFLAG_Type; 101 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 102 103 /* -------- EIC_ASYNCH : (EIC Offset: 0x18) (R/W 32) External Interrupt Asynchronous Mode -------- */ 104 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 105 typedef union { 106 struct { 107 uint32_t ASYNCH:16; /*!< bit: 0..15 Asynchronous Edge Detection Mode */ 108 uint32_t :16; /*!< bit: 16..31 Reserved */ 109 } bit; /*!< Structure used for bit access */ 110 uint32_t reg; /*!< Type used for register access */ 111 } EIC_ASYNCH_Type; 112 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 113 /* -------- EIC_CONFIG0 : (EIC Offset: 0x1C) (R/W 32) External Interrupt Sense Configuration -------- */ 114 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 115 typedef union { 116 struct { 117 uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense Configuration 0 */ 118 uint32_t FILTEN0:1; /*!< bit: 3 Filter Enable 0 */ 119 uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense Configuration 1 */ 120 uint32_t FILTEN1:1; /*!< bit: 7 Filter Enable 1 */ 121 uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense Configuration 2 */ 122 uint32_t FILTEN2:1; /*!< bit: 11 Filter Enable 2 */ 123 uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense Configuration 3 */ 124 uint32_t FILTEN3:1; /*!< bit: 15 Filter Enable 3 */ 125 uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense Configuration 4 */ 126 uint32_t FILTEN4:1; /*!< bit: 19 Filter Enable 4 */ 127 uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense Configuration 5 */ 128 uint32_t FILTEN5:1; /*!< bit: 23 Filter Enable 5 */ 129 uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense Configuration 6 */ 130 uint32_t FILTEN6:1; /*!< bit: 27 Filter Enable 6 */ 131 uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense Configuration 7 */ 132 uint32_t FILTEN7:1; /*!< bit: 31 Filter Enable 7 */ 133 } bit; /*!< Structure used for bit access */ 134 uint32_t reg; /*!< Type used for register access */ 135 } EIC_CONFIG_Type; 136 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 137 138 /* For SAM0 compatibily start */ 139 /* -------- EIC_CONFIG0 : (EIC Offset: 0x20) (R/W 32) External Interrupt Sense Configuration -------- */ 140 #define EIC_CONFIG_SENSE0_NONE (EIC_CONFIG0_SENSE0_NONE_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) No detection Position */ 141 #define EIC_CONFIG_SENSE0_RISE (EIC_CONFIG0_SENSE0_RISE_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Rising edge detection Position */ 142 #define EIC_CONFIG_SENSE0_FALL (EIC_CONFIG0_SENSE0_FALL_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Falling edge detection Position */ 143 #define EIC_CONFIG_SENSE0_BOTH (EIC_CONFIG0_SENSE0_BOTH_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Both edges detection Position */ 144 #define EIC_CONFIG_SENSE0_HIGH (EIC_CONFIG0_SENSE0_HIGH_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) High level detection Position */ 145 #define EIC_CONFIG_SENSE0_LOW (EIC_CONFIG0_SENSE0_LOW_Val << EIC_CONFIG0_SENSE0_Pos) /* (EIC_CONFIG0) Low level detection Position */ 146 #define EIC_CONFIG_FILTEN0 ((uint32_t)(0x1) << EIC_CONFIG0_FILTEN0_Pos) /* (EIC_CONFIG0) Filter Enable 0 Mask */ 147 /* For SAM0 compatibily end */ 148 149 /* -------- EIC_DEBOUNCEN : (EIC Offset: 0x30) (R/W 32) Debouncer Enable -------- */ 150 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 151 typedef union { 152 struct { 153 uint32_t DEBOUNCEN:16; /*!< bit: 0..15 Debouncer Enable */ 154 uint32_t :16; /*!< bit: 16..31 Reserved */ 155 } bit; /*!< Structure used for bit access */ 156 uint32_t reg; /*!< Type used for register access */ 157 } EIC_DEBOUNCEN_Type; 158 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 159 160 /* -------- EIC_DPRESCALER : (EIC Offset: 0x34) (R/W 32) Debouncer Prescaler -------- */ 161 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 162 typedef union { 163 struct { 164 uint32_t PRESCALER0:3; /*!< bit: 0.. 2 Debouncer Prescaler */ 165 uint32_t STATES0:1; /*!< bit: 3 Debouncer number of states */ 166 uint32_t PRESCALER1:3; /*!< bit: 4.. 6 Debouncer Prescaler */ 167 uint32_t STATES1:1; /*!< bit: 7 Debouncer number of states */ 168 uint32_t :8; /*!< bit: 8..15 Reserved */ 169 uint32_t TICKON:1; /*!< bit: 16 Pin Sampler frequency selection */ 170 uint32_t :15; /*!< bit: 17..31 Reserved */ 171 } bit; /*!< Structure used for bit access */ 172 uint32_t reg; /*!< Type used for register access */ 173 } EIC_DPRESCALER_Type; 174 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 175 176 /* -------- EIC_PINSTATE : (EIC Offset: 0x38) ( R/ 32) Pin State -------- */ 177 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 178 typedef union { 179 struct { 180 uint32_t PINSTATE:16; /*!< bit: 0..15 Pin State */ 181 uint32_t :16; /*!< bit: 16..31 Reserved */ 182 } bit; /*!< Structure used for bit access */ 183 uint32_t reg; /*!< Type used for register access */ 184 } EIC_PINSTATE_Type; 185 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 186 187 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 188 typedef struct { 189 __IO EIC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */ 190 __IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x01 (R/W 8) Non-Maskable Interrupt Control */ 191 __IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x02 (R/W 16) Non-Maskable Interrupt Flag Status and Clear */ 192 __I EIC_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x04 (R/ 32) Synchronization Busy */ 193 __IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x08 (R/W 32) Event Control */ 194 __IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Clear */ 195 __IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Set */ 196 __IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 32) Interrupt Flag Status and Clear */ 197 __IO EIC_ASYNCH_Type ASYNCH; /**< \brief Offset: 0x18 (R/W 32) External Interrupt Asynchronous Mode */ 198 __IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x1C (R/W 32) External Interrupt Sense Configuration */ 199 RoReg8 Reserved1[0xC]; 200 __IO EIC_DEBOUNCEN_Type DEBOUNCEN; /**< \brief Offset: 0x30 (R/W 32) Debouncer Enable */ 201 __IO EIC_DPRESCALER_Type DPRESCALER; /**< \brief Offset: 0x34 (R/W 32) Debouncer Prescaler */ 202 __I EIC_PINSTATE_Type PINSTATE; /**< \brief Offset: 0x38 (R/ 32) Pin State */ 203 } Eic; 204 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 205 206 207 #endif /* _MICROCHIP_PIC32CXSG_EIC_COMPONENT_FIXUP_H_ */ 208
