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Searched refs:CFG_DDR_SGMII_PHY (Results 1 – 6 of 6) sorted by relevance

/hal_microchip-latest/mpfs/mpfs_hal/common/nwc/
Dmss_sgmii.c102 CFG_DDR_SGMII_PHY->SOFT_RESET_SGMII.SOFT_RESET_SGMII = \ in sgmii_channel_setup()
104 CFG_DDR_SGMII_PHY->SOFT_RESET_SGMII.SOFT_RESET_SGMII = 1U; in sgmii_channel_setup()
124 if((CFG_DDR_SGMII_PHY->PVT_STAT.PVT_STAT & (0x01U<<6U)) != 0U) in sgmii_channel_setup()
214 CFG_DDR_SGMII_PHY->DYN_CNTL.DYN_CNTL = (0x01U<< 10U) | (0x7FU<<0U); in sgmii_channel_setup()
216 CFG_DDR_SGMII_PHY->DYN_CNTL.DYN_CNTL = (0x7FU<<0U); in sgmii_channel_setup()
238 if((CFG_DDR_SGMII_PHY->PVT_STAT.PVT_STAT & (1U << 14U)) == (1U << 14U)) in sgmii_channel_setup()
250 CFG_DDR_SGMII_PHY->PVT_STAT.PVT_STAT |= 0x40000000UL; in sgmii_channel_setup()
271 if (CFG_DDR_SGMII_PHY->PLL_CNTL.PLL_CNTL & (1U<<7U)) in sgmii_channel_setup()
278 if (CFG_DDR_SGMII_PHY->RECAL_CNTL.RECAL_CNTL & (1U<<23U)) in sgmii_channel_setup()
305 sro_dll_90_code = ((CFG_DDR_SGMII_PHY->RECAL_CNTL.RECAL_CNTL >> 16U) & 0x7FU); in sgmii_channel_setup()
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Dmss_ddr.c497 CFG_DDR_SGMII_PHY->training_start.training_start = 0x0U; in ddr_setup()
506 CFG_DDR_SGMII_PHY->training_start.training_start = 0x0U; in ddr_setup()
581 CFG_DDR_SGMII_PHY->training_start.training_start = 0x00000000U; in ddr_setup()
782 CFG_DDR_SGMII_PHY->SOFT_RESET_DECODER_DRIVER.SOFT_RESET_DECODER_DRIVER = 1U; in ddr_setup()
783 CFG_DDR_SGMII_PHY->SOFT_RESET_DECODER_ODT.SOFT_RESET_DECODER_ODT=1U; in ddr_setup()
784 CFG_DDR_SGMII_PHY->SOFT_RESET_DECODER_IO.SOFT_RESET_DECODER_IO = 1U; in ddr_setup()
811 (CFG_DDR_SGMII_PHY->IOC_REG2.IOC_REG2 & 0x7FU)); in ddr_setup()
813 (((CFG_DDR_SGMII_PHY->IOC_REG2.IOC_REG2) >> 7U) & 0x7FU)); in ddr_setup()
881 CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000002U; in ddr_setup()
904 CFG_DDR_SGMII_PHY->training_reset.training_reset = 0x00000002U; in ddr_setup()
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Dmss_ddr_debug.c548 CFG_DDR_SGMII_PHY->expert_wrcalib.expert_wrcalib); in wrcalib_status()
574 CFG_DDR_SGMII_PHY->training_status.training_status); in tip_register_status()
576 (CFG_DDR_SGMII_PHY->IOC_REG2.IOC_REG2 & 0x7F)); in tip_register_status()
578 (((CFG_DDR_SGMII_PHY->IOC_REG2.IOC_REG2) >> 7) & 0x7F)); in tip_register_status()
580 , CFG_DDR_SGMII_PHY->expert_wrcalib.expert_wrcalib); in tip_register_status()
582 (((CFG_DDR_SGMII_PHY->IOC_REG5.IOC_REG5) >> 0) & 0x3F)); in tip_register_status()
584 (((CFG_DDR_SGMII_PHY->IOC_REG5.IOC_REG5) >> 6) & 0xFFF)); in tip_register_status()
586 (((CFG_DDR_SGMII_PHY->IOC_REG5.IOC_REG5) >> 18) & 0x3F)); in tip_register_status()
588 (((CFG_DDR_SGMII_PHY->IOC_REG5.IOC_REG5) >> 24) & 0x3F)); in tip_register_status()
595 CFG_DDR_SGMII_PHY->lane_select.lane_select = ddr_lane_sel; in tip_register_status()
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Dmss_pll.c552 CFG_DDR_SGMII_PHY->PLL_CTRL_MAIN.PLL_CTRL_MAIN =\ in ddr_pll_config()
554 CFG_DDR_SGMII_PHY->PLL_REF_FB_MAIN.PLL_REF_FB_MAIN =\ in ddr_pll_config()
559 CFG_DDR_SGMII_PHY->PLL_DIV_0_1_MAIN.PLL_DIV_0_1_MAIN =\ in ddr_pll_config()
561 CFG_DDR_SGMII_PHY->PLL_DIV_2_3_MAIN.PLL_DIV_2_3_MAIN =\ in ddr_pll_config()
563 CFG_DDR_SGMII_PHY->PLL_CTRL2_MAIN.PLL_CTRL2_MAIN =\ in ddr_pll_config()
568 CFG_DDR_SGMII_PHY->PLL_PHADJ_MAIN.PLL_PHADJ_MAIN =\ in ddr_pll_config()
572 CFG_DDR_SGMII_PHY->SSCG_REG_2_MAIN.SSCG_REG_2_MAIN =\ in ddr_pll_config()
Dmss_nwc_init.c32 CFG_DDR_SGMII_PHY_TypeDef * const CFG_DDR_SGMII_PHY = ((CFG_DDR_SGMII_PHY_TypeDef *) CFG_D… variable
159 CFG_DDR_SGMII_PHY->DDRPHY_STARTUP.DDRPHY_STARTUP =\ in mss_nwc_init()
166 CFG_DDR_SGMII_PHY->DYN_CNTL.DYN_CNTL = (0x01U<< 10U) | (0x7FU<<0U); in mss_nwc_init()
Dmss_ddr_sgmii_regs.h5549 extern CFG_DDR_SGMII_PHY_TypeDef * const CFG_DDR_SGMII_PHY ;