1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_FREQM_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_FREQM_COMPONENT_FIXUP_H_ 9 10 /* -------- FREQM_CTRLA : (FREQM Offset: 0x00) (R/W 8) Control A Register -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint8_t SWRST:1; /*!< bit: 0 Software Reset */ 15 uint8_t ENABLE:1; /*!< bit: 1 Enable */ 16 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 17 } bit; /*!< Structure used for bit access */ 18 uint8_t reg; /*!< Type used for register access */ 19 } FREQM_CTRLA_Type; 20 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 21 22 /* -------- FREQM_CTRLB : (FREQM Offset: 0x01) ( /W 8) Control B Register -------- */ 23 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 24 typedef union { 25 struct { 26 uint8_t START:1; /*!< bit: 0 Start Measurement */ 27 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 28 } bit; /*!< Structure used for bit access */ 29 uint8_t reg; /*!< Type used for register access */ 30 } FREQM_CTRLB_Type; 31 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 32 33 /* -------- FREQM_CFGA : (FREQM Offset: 0x02) (R/W 16) Config A register -------- */ 34 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 35 typedef union { 36 struct { 37 uint16_t REFNUM:8; /*!< bit: 0.. 7 Number of Reference Clock Cycles */ 38 uint16_t :8; /*!< bit: 8..15 Reserved */ 39 } bit; /*!< Structure used for bit access */ 40 uint16_t reg; /*!< Type used for register access */ 41 } FREQM_CFGA_Type; 42 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 43 44 /* -------- FREQM_INTENCLR : (FREQM Offset: 0x08) (R/W 8) Interrupt Enable Clear Register -------- */ 45 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 46 typedef union { 47 struct { 48 uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */ 49 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 50 } bit; /*!< Structure used for bit access */ 51 uint8_t reg; /*!< Type used for register access */ 52 } FREQM_INTENCLR_Type; 53 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 54 55 /* -------- FREQM_INTENSET : (FREQM Offset: 0x09) (R/W 8) Interrupt Enable Set Register -------- */ 56 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 57 typedef union { 58 struct { 59 uint8_t DONE:1; /*!< bit: 0 Measurement Done Interrupt Enable */ 60 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 61 } bit; /*!< Structure used for bit access */ 62 uint8_t reg; /*!< Type used for register access */ 63 } FREQM_INTENSET_Type; 64 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 65 66 /* -------- FREQM_INTFLAG : (FREQM Offset: 0x0A) (R/W 8) Interrupt Flag Register -------- */ 67 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 68 typedef union { // __I to avoid read-modify-write on write-to-clear register 69 struct { 70 __I uint8_t DONE:1; /*!< bit: 0 Measurement Done */ 71 __I uint8_t :7; /*!< bit: 1.. 7 Reserved */ 72 } bit; /*!< Structure used for bit access */ 73 uint8_t reg; /*!< Type used for register access */ 74 } FREQM_INTFLAG_Type; 75 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 76 77 /* -------- FREQM_STATUS : (FREQM Offset: 0x0B) (R/W 8) Status Register -------- */ 78 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 79 typedef union { 80 struct { 81 uint8_t BUSY:1; /*!< bit: 0 FREQM Status */ 82 uint8_t OVF:1; /*!< bit: 1 Sticky Count Value Overflow */ 83 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 84 } bit; /*!< Structure used for bit access */ 85 uint8_t reg; /*!< Type used for register access */ 86 } FREQM_STATUS_Type; 87 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 88 89 /* -------- FREQM_SYNCBUSY : (FREQM Offset: 0x0C) ( R/ 32) Synchronization Busy Register -------- */ 90 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 91 typedef union { 92 struct { 93 uint32_t SWRST:1; /*!< bit: 0 Software Reset */ 94 uint32_t ENABLE:1; /*!< bit: 1 Enable */ 95 uint32_t :30; /*!< bit: 2..31 Reserved */ 96 } bit; /*!< Structure used for bit access */ 97 uint32_t reg; /*!< Type used for register access */ 98 } FREQM_SYNCBUSY_Type; 99 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 100 101 /* -------- FREQM_VALUE : (FREQM Offset: 0x10) ( R/ 32) Count Value Register -------- */ 102 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 103 typedef union { 104 struct { 105 uint32_t VALUE:24; /*!< bit: 0..23 Measurement Value */ 106 uint32_t :8; /*!< bit: 24..31 Reserved */ 107 } bit; /*!< Structure used for bit access */ 108 uint32_t reg; /*!< Type used for register access */ 109 } FREQM_VALUE_Type; 110 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 111 112 /** \brief FREQM hardware registers */ 113 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 114 typedef struct { 115 __IO FREQM_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A Register */ 116 __O FREQM_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B Register */ 117 __IO FREQM_CFGA_Type CFGA; /**< \brief Offset: 0x02 (R/W 16) Config A register */ 118 RoReg8 Reserved1[0x4]; 119 __IO FREQM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 8) Interrupt Enable Clear Register */ 120 __IO FREQM_INTENSET_Type INTENSET; /**< \brief Offset: 0x09 (R/W 8) Interrupt Enable Set Register */ 121 __IO FREQM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0A (R/W 8) Interrupt Flag Register */ 122 __IO FREQM_STATUS_Type STATUS; /**< \brief Offset: 0x0B (R/W 8) Status Register */ 123 __I FREQM_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x0C (R/ 32) Synchronization Busy Register */ 124 __I FREQM_VALUE_Type VALUE; /**< \brief Offset: 0x10 (R/ 32) Count Value Register */ 125 } Freqm; 126 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 127 128 #endif /* _MICROCHIP_PIC32CXSG_FREQM_COMPONENT_FIXUP_H_ */ 129
