1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_OSC32KCTRL_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_OSC32KCTRL_COMPONENT_FIXUP_H_ 9 10 /* -------- OSC32KCTRL_INTENCLR : (OSC32KCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ 15 uint32_t :1; /*!< bit: 1 Reserved */ 16 uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */ 17 uint32_t :29; /*!< bit: 3..31 Reserved */ 18 } bit; /*!< Structure used for bit access */ 19 uint32_t reg; /*!< Type used for register access */ 20 } OSC32KCTRL_INTENCLR_Type; 21 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 22 23 /* -------- OSC32KCTRL_INTENSET : (OSC32KCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ 24 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 25 typedef union { 26 struct { 27 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready Interrupt Enable */ 28 uint32_t :1; /*!< bit: 1 Reserved */ 29 uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector Interrupt Enable */ 30 uint32_t :29; /*!< bit: 3..31 Reserved */ 31 } bit; /*!< Structure used for bit access */ 32 uint32_t reg; /*!< Type used for register access */ 33 } OSC32KCTRL_INTENSET_Type; 34 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 35 36 /* -------- OSC32KCTRL_INTFLAG : (OSC32KCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ 37 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 38 typedef union { // __I to avoid read-modify-write on write-to-clear register 39 struct { 40 __I uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ 41 __I uint32_t :1; /*!< bit: 1 Reserved */ 42 __I uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */ 43 __I uint32_t :29; /*!< bit: 3..31 Reserved */ 44 } bit; /*!< Structure used for bit access */ 45 uint32_t reg; /*!< Type used for register access */ 46 } OSC32KCTRL_INTFLAG_Type; 47 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 48 49 /* -------- OSC32KCTRL_STATUS : (OSC32KCTRL Offset: 0x0C) ( R/ 32) Power and Clocks Status -------- */ 50 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 51 typedef union { 52 struct { 53 uint32_t XOSC32KRDY:1; /*!< bit: 0 XOSC32K Ready */ 54 uint32_t :1; /*!< bit: 1 Reserved */ 55 uint32_t XOSC32KFAIL:1; /*!< bit: 2 XOSC32K Clock Failure Detector */ 56 uint32_t XOSC32KSW:1; /*!< bit: 3 XOSC32K Clock switch */ 57 uint32_t :28; /*!< bit: 4..31 Reserved */ 58 } bit; /*!< Structure used for bit access */ 59 uint32_t reg; /*!< Type used for register access */ 60 } OSC32KCTRL_STATUS_Type; 61 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 62 63 /* -------- OSC32KCTRL_RTCCTRL : (OSC32KCTRL Offset: 0x10) (R/W 8) RTC Clock Selection -------- */ 64 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 65 typedef union { 66 struct { 67 uint8_t RTCSEL:3; /*!< bit: 0.. 2 RTC Clock Selection */ 68 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 69 } bit; /*!< Structure used for bit access */ 70 uint8_t reg; /*!< Type used for register access */ 71 } OSC32KCTRL_RTCCTRL_Type; 72 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 73 74 /* -------- OSC32KCTRL_XOSC32K : (OSC32KCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */ 75 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 76 typedef union { 77 struct { 78 uint16_t :1; /*!< bit: 0 Reserved */ 79 uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */ 80 uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */ 81 uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */ 82 uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */ 83 uint16_t :1; /*!< bit: 5 Reserved */ 84 uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */ 85 uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */ 86 uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */ 87 uint16_t :1; /*!< bit: 11 Reserved */ 88 uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */ 89 uint16_t CGM:2; /*!< bit: 13..14 Control Gain Mode */ 90 uint16_t :1; /*!< bit: 15 Reserved */ 91 } bit; /*!< Structure used for bit access */ 92 uint16_t reg; /*!< Type used for register access */ 93 } OSC32KCTRL_XOSC32K_Type; 94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 /* -------- OSC32KCTRL_CFDCTRL : (OSC32KCTRL Offset: 0x16) (R/W 8) Clock Failure Detector Control -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { 99 struct { 100 uint8_t CFDEN:1; /*!< bit: 0 Clock Failure Detector Enable */ 101 uint8_t SWBACK:1; /*!< bit: 1 Clock Switch Back */ 102 uint8_t CFDPRESC:1; /*!< bit: 2 Clock Failure Detector Prescaler */ 103 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 104 } bit; /*!< Structure used for bit access */ 105 uint8_t reg; /*!< Type used for register access */ 106 } OSC32KCTRL_CFDCTRL_Type; 107 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 108 109 /* -------- OSC32KCTRL_EVCTRL : (OSC32KCTRL Offset: 0x17) (R/W 8) Event Control -------- */ 110 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 111 typedef union { 112 struct { 113 uint8_t CFDEO:1; /*!< bit: 0 Clock Failure Detector Event Output Enable */ 114 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 115 } bit; /*!< Structure used for bit access */ 116 uint8_t reg; /*!< Type used for register access */ 117 } OSC32KCTRL_EVCTRL_Type; 118 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 119 120 /* -------- OSC32KCTRL_OSCULP32K : (OSC32KCTRL Offset: 0x1C) (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */ 121 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 122 typedef union { 123 struct { 124 uint32_t :1; /*!< bit: 0 Reserved */ 125 uint32_t EN32K:1; /*!< bit: 1 Enable Out 32k */ 126 uint32_t EN1K:1; /*!< bit: 2 Enable Out 1k */ 127 uint32_t :5; /*!< bit: 3.. 7 Reserved */ 128 uint32_t CALIB:6; /*!< bit: 8..13 Oscillator Calibration */ 129 uint32_t :1; /*!< bit: 14 Reserved */ 130 uint32_t WRTLOCK:1; /*!< bit: 15 Write Lock */ 131 uint32_t :16; /*!< bit: 16..31 Reserved */ 132 } bit; /*!< Structure used for bit access */ 133 uint32_t reg; /*!< Type used for register access */ 134 } OSC32KCTRL_OSCULP32K_Type; 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 138 typedef struct { 139 __IO OSC32KCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ 140 __IO OSC32KCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ 141 __IO OSC32KCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ 142 __I OSC32KCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ 143 __IO OSC32KCTRL_RTCCTRL_Type RTCCTRL; /**< \brief Offset: 0x10 (R/W 8) RTC Clock Selection */ 144 RoReg8 Reserved1[0x3]; 145 __IO OSC32KCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */ 146 __IO OSC32KCTRL_CFDCTRL_Type CFDCTRL; /**< \brief Offset: 0x16 (R/W 8) Clock Failure Detector Control */ 147 __IO OSC32KCTRL_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x17 (R/W 8) Event Control */ 148 RoReg8 Reserved2[0x4]; 149 __IO OSC32KCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 32) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */ 150 } Osc32kctrl; 151 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 152 153 154 155 #endif /* _MICROCHIP_PIC32CXSG_OSC32KCTRL_COMPONENT_FIXUP_H_ */ 156
