1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_SDHC_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_SDHC_COMPONENT_FIXUP_H_ 9 10 /* -------- SDHC_SSAR : (SDHC Offset: 0x00) (R/W 32) SDMA System Address / Argument 2 -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { // CMD23 mode 14 uint32_t ARG2:32; /*!< bit: 0..31 Argument 2 */ 15 } CMD23; /*!< Structure used for CMD23 */ 16 struct { 17 uint32_t ADDR:32; /*!< bit: 0..31 SDMA System Address */ 18 } bit; /*!< Structure used for bit access */ 19 uint32_t reg; /*!< Type used for register access */ 20 } SDHC_SSAR_Type; 21 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 22 23 /* -------- SDHC_BSR : (SDHC Offset: 0x04) (R/W 16) Block Size -------- */ 24 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 25 typedef union { 26 struct { 27 uint16_t BLOCKSIZE:10; /*!< bit: 0.. 9 Transfer Block Size */ 28 uint16_t :2; /*!< bit: 10..11 Reserved */ 29 uint16_t BOUNDARY:3; /*!< bit: 12..14 SDMA Buffer Boundary */ 30 uint16_t :1; /*!< bit: 15 Reserved */ 31 } bit; /*!< Structure used for bit access */ 32 uint16_t reg; /*!< Type used for register access */ 33 } SDHC_BSR_Type; 34 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 35 36 /* -------- SDHC_BCR : (SDHC Offset: 0x06) (R/W 16) Block Count -------- */ 37 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 38 typedef union { 39 struct { 40 uint16_t BCNT:16; /*!< bit: 0..15 Blocks Count for Current Transfer */ 41 } bit; /*!< Structure used for bit access */ 42 uint16_t reg; /*!< Type used for register access */ 43 } SDHC_BCR_Type; 44 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 45 46 /* -------- SDHC_ARG1R : (SDHC Offset: 0x08) (R/W 32) Argument 1 -------- */ 47 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 48 typedef union { 49 struct { 50 uint32_t ARG:32; /*!< bit: 0..31 Argument 1 */ 51 } bit; /*!< Structure used for bit access */ 52 uint32_t reg; /*!< Type used for register access */ 53 } SDHC_ARG1R_Type; 54 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 55 56 /* -------- SDHC_TMR : (SDHC Offset: 0x0C) (R/W 16) Transfer Mode -------- */ 57 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 58 typedef union { 59 struct { 60 uint16_t DMAEN:1; /*!< bit: 0 DMA Enable */ 61 uint16_t BCEN:1; /*!< bit: 1 Block Count Enable */ 62 uint16_t ACMDEN:2; /*!< bit: 2.. 3 Auto Command Enable */ 63 uint16_t DTDSEL:1; /*!< bit: 4 Data Transfer Direction Selection */ 64 uint16_t MSBSEL:1; /*!< bit: 5 Multi/Single Block Selection */ 65 uint16_t :10; /*!< bit: 6..15 Reserved */ 66 } bit; /*!< Structure used for bit access */ 67 uint16_t reg; /*!< Type used for register access */ 68 } SDHC_TMR_Type; 69 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 70 71 /* -------- SDHC_CR : (SDHC Offset: 0x0E) (R/W 16) Command -------- */ 72 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 73 typedef union { 74 struct { 75 uint16_t RESPTYP:2; /*!< bit: 0.. 1 Response Type */ 76 uint16_t :1; /*!< bit: 2 Reserved */ 77 uint16_t CMDCCEN:1; /*!< bit: 3 Command CRC Check Enable */ 78 uint16_t CMDICEN:1; /*!< bit: 4 Command Index Check Enable */ 79 uint16_t DPSEL:1; /*!< bit: 5 Data Present Select */ 80 uint16_t CMDTYP:2; /*!< bit: 6.. 7 Command Type */ 81 uint16_t CMDIDX:6; /*!< bit: 8..13 Command Index */ 82 uint16_t :2; /*!< bit: 14..15 Reserved */ 83 } bit; /*!< Structure used for bit access */ 84 uint16_t reg; /*!< Type used for register access */ 85 } SDHC_CR_Type; 86 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 87 88 /* -------- SDHC_RR : (SDHC Offset: 0x10) ( R/ 32) Response -------- */ 89 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 90 typedef union { 91 struct { 92 uint32_t CMDRESP:32; /*!< bit: 0..31 Command Response */ 93 } bit; /*!< Structure used for bit access */ 94 uint32_t reg; /*!< Type used for register access */ 95 } SDHC_RR_Type; 96 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 97 98 /* -------- SDHC_BDPR : (SDHC Offset: 0x20) (R/W 32) Buffer Data Port -------- */ 99 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 100 typedef union { 101 struct { 102 uint32_t BUFDATA:32; /*!< bit: 0..31 Buffer Data */ 103 } bit; /*!< Structure used for bit access */ 104 uint32_t reg; /*!< Type used for register access */ 105 } SDHC_BDPR_Type; 106 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 107 108 /* -------- SDHC_PSR : (SDHC Offset: 0x24) ( R/ 32) Present State -------- */ 109 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 110 typedef union { 111 struct { 112 uint32_t CMDINHC:1; /*!< bit: 0 Command Inhibit (CMD) */ 113 uint32_t CMDINHD:1; /*!< bit: 1 Command Inhibit (DAT) */ 114 uint32_t DLACT:1; /*!< bit: 2 DAT Line Active */ 115 uint32_t RTREQ:1; /*!< bit: 3 Re-Tuning Request */ 116 uint32_t :4; /*!< bit: 4.. 7 Reserved */ 117 uint32_t WTACT:1; /*!< bit: 8 Write Transfer Active */ 118 uint32_t RTACT:1; /*!< bit: 9 Read Transfer Active */ 119 uint32_t BUFWREN:1; /*!< bit: 10 Buffer Write Enable */ 120 uint32_t BUFRDEN:1; /*!< bit: 11 Buffer Read Enable */ 121 uint32_t :4; /*!< bit: 12..15 Reserved */ 122 uint32_t CARDINS:1; /*!< bit: 16 Card Inserted */ 123 uint32_t CARDSS:1; /*!< bit: 17 Card State Stable */ 124 uint32_t CARDDPL:1; /*!< bit: 18 Card Detect Pin Level */ 125 uint32_t WRPPL:1; /*!< bit: 19 Write Protect Pin Level */ 126 uint32_t DATLL:4; /*!< bit: 20..23 DAT[3:0] Line Level */ 127 uint32_t CMDLL:1; /*!< bit: 24 CMD Line Level */ 128 uint32_t :7; /*!< bit: 25..31 Reserved */ 129 } bit; /*!< Structure used for bit access */ 130 uint32_t reg; /*!< Type used for register access */ 131 } SDHC_PSR_Type; 132 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 133 134 /* -------- SDHC_HC1R : (SDHC Offset: 0x28) (R/W 8) Host Control 1 -------- */ 135 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 136 typedef union { 137 struct { 138 uint8_t LEDCTRL:1; /*!< bit: 0 LED Control */ 139 uint8_t DW:1; /*!< bit: 1 Data Width */ 140 uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */ 141 uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */ 142 uint8_t :1; /*!< bit: 5 Reserved */ 143 uint8_t CARDDTL:1; /*!< bit: 6 Card Detect Test Level */ 144 uint8_t CARDDSEL:1; /*!< bit: 7 Card Detect Signal Selection */ 145 } bit; /*!< Structure used for bit access */ 146 struct { // EMMC mode 147 uint8_t :1; /*!< bit: 0 Reserved */ 148 uint8_t DW:1; /*!< bit: 1 Data Width */ 149 uint8_t HSEN:1; /*!< bit: 2 High Speed Enable */ 150 uint8_t DMASEL:2; /*!< bit: 3.. 4 DMA Select */ 151 uint8_t :3; /*!< bit: 5.. 7 Reserved */ 152 } EMMC; /*!< Structure used for EMMC */ 153 uint8_t reg; /*!< Type used for register access */ 154 } SDHC_HC1R_Type; 155 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 156 157 /* -------- SDHC_PCR : (SDHC Offset: 0x29) (R/W 8) Power Control -------- */ 158 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 159 typedef union { 160 struct { 161 uint8_t SDBPWR:1; /*!< bit: 0 SD Bus Power */ 162 uint8_t SDBVSEL:3; /*!< bit: 1.. 3 SD Bus Voltage Select */ 163 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 164 } bit; /*!< Structure used for bit access */ 165 uint8_t reg; /*!< Type used for register access */ 166 } SDHC_PCR_Type; 167 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 168 169 /* -------- SDHC_BGCR : (SDHC Offset: 0x2A) (R/W 8) Block Gap Control -------- */ 170 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 171 typedef union { 172 struct { 173 uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */ 174 uint8_t CONTR:1; /*!< bit: 1 Continue Request */ 175 uint8_t RWCTRL:1; /*!< bit: 2 Read Wait Control */ 176 uint8_t INTBG:1; /*!< bit: 3 Interrupt at Block Gap */ 177 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 178 } bit; /*!< Structure used for bit access */ 179 struct { // EMMC mode 180 uint8_t STPBGR:1; /*!< bit: 0 Stop at Block Gap Request */ 181 uint8_t CONTR:1; /*!< bit: 1 Continue Request */ 182 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 183 } EMMC; /*!< Structure used for EMMC */ 184 uint8_t reg; /*!< Type used for register access */ 185 } SDHC_BGCR_Type; 186 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 187 188 /* -------- SDHC_WCR : (SDHC Offset: 0x2B) (R/W 8) Wakeup Control -------- */ 189 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 190 typedef union { 191 struct { 192 uint8_t WKENCINT:1; /*!< bit: 0 Wakeup Event Enable on Card Interrupt */ 193 uint8_t WKENCINS:1; /*!< bit: 1 Wakeup Event Enable on Card Insertion */ 194 uint8_t WKENCREM:1; /*!< bit: 2 Wakeup Event Enable on Card Removal */ 195 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 196 } bit; /*!< Structure used for bit access */ 197 uint8_t reg; /*!< Type used for register access */ 198 } SDHC_WCR_Type; 199 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 200 201 /* -------- SDHC_CCR : (SDHC Offset: 0x2C) (R/W 16) Clock Control -------- */ 202 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 203 typedef union { 204 struct { 205 uint16_t INTCLKEN:1; /*!< bit: 0 Internal Clock Enable */ 206 uint16_t INTCLKS:1; /*!< bit: 1 Internal Clock Stable */ 207 uint16_t SDCLKEN:1; /*!< bit: 2 SD Clock Enable */ 208 uint16_t :2; /*!< bit: 3.. 4 Reserved */ 209 uint16_t CLKGSEL:1; /*!< bit: 5 Clock Generator Select */ 210 uint16_t USDCLKFSEL:2; /*!< bit: 6.. 7 Upper Bits of SDCLK Frequency Select */ 211 uint16_t SDCLKFSEL:8; /*!< bit: 8..15 SDCLK Frequency Select */ 212 } bit; /*!< Structure used for bit access */ 213 uint16_t reg; /*!< Type used for register access */ 214 } SDHC_CCR_Type; 215 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 216 217 /* -------- SDHC_TCR : (SDHC Offset: 0x2E) (R/W 8) Timeout Control -------- */ 218 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 219 typedef union { 220 struct { 221 uint8_t DTCVAL:4; /*!< bit: 0.. 3 Data Timeout Counter Value */ 222 uint8_t :4; /*!< bit: 4.. 7 Reserved */ 223 } bit; /*!< Structure used for bit access */ 224 uint8_t reg; /*!< Type used for register access */ 225 } SDHC_TCR_Type; 226 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 227 228 /* -------- SDHC_SRR : (SDHC Offset: 0x2F) (R/W 8) Software Reset -------- */ 229 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 230 typedef union { 231 struct { 232 uint8_t SWRSTALL:1; /*!< bit: 0 Software Reset For All */ 233 uint8_t SWRSTCMD:1; /*!< bit: 1 Software Reset For CMD Line */ 234 uint8_t SWRSTDAT:1; /*!< bit: 2 Software Reset For DAT Line */ 235 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 236 } bit; /*!< Structure used for bit access */ 237 uint8_t reg; /*!< Type used for register access */ 238 } SDHC_SRR_Type; 239 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 240 241 /* -------- SDHC_NISTR : (SDHC Offset: 0x30) (R/W 16) Normal Interrupt Status -------- */ 242 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 243 typedef union { 244 struct { 245 uint16_t CMDC:1; /*!< bit: 0 Command Complete */ 246 uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */ 247 uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */ 248 uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */ 249 uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */ 250 uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */ 251 uint16_t CINS:1; /*!< bit: 6 Card Insertion */ 252 uint16_t CREM:1; /*!< bit: 7 Card Removal */ 253 uint16_t CINT:1; /*!< bit: 8 Card Interrupt */ 254 uint16_t :6; /*!< bit: 9..14 Reserved */ 255 uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */ 256 } bit; /*!< Structure used for bit access */ 257 struct { // EMMC mode 258 uint16_t CMDC:1; /*!< bit: 0 Command Complete */ 259 uint16_t TRFC:1; /*!< bit: 1 Transfer Complete */ 260 uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event */ 261 uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt */ 262 uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready */ 263 uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready */ 264 uint16_t :8; /*!< bit: 6..13 Reserved */ 265 uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received */ 266 uint16_t ERRINT:1; /*!< bit: 15 Error Interrupt */ 267 } EMMC; /*!< Structure used for EMMC */ 268 uint16_t reg; /*!< Type used for register access */ 269 } SDHC_NISTR_Type; 270 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 271 272 /* -------- SDHC_EISTR : (SDHC Offset: 0x32) (R/W 16) Error Interrupt Status -------- */ 273 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 274 typedef union { 275 struct { 276 uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */ 277 uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */ 278 uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */ 279 uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */ 280 uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */ 281 uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */ 282 uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */ 283 uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */ 284 uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */ 285 uint16_t ADMA:1; /*!< bit: 9 ADMA Error */ 286 uint16_t :6; /*!< bit: 10..15 Reserved */ 287 } bit; /*!< Structure used for bit access */ 288 struct { // EMMC mode 289 uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error */ 290 uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error */ 291 uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error */ 292 uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error */ 293 uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error */ 294 uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error */ 295 uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error */ 296 uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error */ 297 uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error */ 298 uint16_t ADMA:1; /*!< bit: 9 ADMA Error */ 299 uint16_t :2; /*!< bit: 10..11 Reserved */ 300 uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error */ 301 uint16_t :3; /*!< bit: 13..15 Reserved */ 302 } EMMC; /*!< Structure used for EMMC */ 303 uint16_t reg; /*!< Type used for register access */ 304 } SDHC_EISTR_Type; 305 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 306 307 /* -------- SDHC_NISTER : (SDHC Offset: 0x34) (R/W 16) Normal Interrupt Status Enable -------- */ 308 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 309 typedef union { 310 struct { 311 uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */ 312 uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */ 313 uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */ 314 uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */ 315 uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */ 316 uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */ 317 uint16_t CINS:1; /*!< bit: 6 Card Insertion Status Enable */ 318 uint16_t CREM:1; /*!< bit: 7 Card Removal Status Enable */ 319 uint16_t CINT:1; /*!< bit: 8 Card Interrupt Status Enable */ 320 uint16_t :7; /*!< bit: 9..15 Reserved */ 321 } bit; /*!< Structure used for bit access */ 322 struct { // EMMC mode 323 uint16_t CMDC:1; /*!< bit: 0 Command Complete Status Enable */ 324 uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Status Enable */ 325 uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Status Enable */ 326 uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Status Enable */ 327 uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Status Enable */ 328 uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Status Enable */ 329 uint16_t :8; /*!< bit: 6..13 Reserved */ 330 uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Status Enable */ 331 uint16_t :1; /*!< bit: 15 Reserved */ 332 } EMMC; /*!< Structure used for EMMC */ 333 uint16_t reg; /*!< Type used for register access */ 334 } SDHC_NISTER_Type; 335 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 336 337 /* -------- SDHC_EISTER : (SDHC Offset: 0x36) (R/W 16) Error Interrupt Status Enable -------- */ 338 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 339 typedef union { 340 struct { 341 uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */ 342 uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */ 343 uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */ 344 uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */ 345 uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */ 346 uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */ 347 uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */ 348 uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */ 349 uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */ 350 uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */ 351 uint16_t :6; /*!< bit: 10..15 Reserved */ 352 } bit; /*!< Structure used for bit access */ 353 struct { // EMMC mode 354 uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Status Enable */ 355 uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Status Enable */ 356 uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Status Enable */ 357 uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Status Enable */ 358 uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Status Enable */ 359 uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Status Enable */ 360 uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Status Enable */ 361 uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Status Enable */ 362 uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Status Enable */ 363 uint16_t ADMA:1; /*!< bit: 9 ADMA Error Status Enable */ 364 uint16_t :2; /*!< bit: 10..11 Reserved */ 365 uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Status Enable */ 366 uint16_t :3; /*!< bit: 13..15 Reserved */ 367 } EMMC; /*!< Structure used for EMMC */ 368 uint16_t reg; /*!< Type used for register access */ 369 } SDHC_EISTER_Type; 370 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 371 372 /* -------- SDHC_NISIER : (SDHC Offset: 0x38) (R/W 16) Normal Interrupt Signal Enable -------- */ 373 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 374 typedef union { 375 struct { 376 uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */ 377 uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */ 378 uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */ 379 uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */ 380 uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */ 381 uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */ 382 uint16_t CINS:1; /*!< bit: 6 Card Insertion Signal Enable */ 383 uint16_t CREM:1; /*!< bit: 7 Card Removal Signal Enable */ 384 uint16_t CINT:1; /*!< bit: 8 Card Interrupt Signal Enable */ 385 uint16_t :7; /*!< bit: 9..15 Reserved */ 386 } bit; /*!< Structure used for bit access */ 387 struct { // EMMC mode 388 uint16_t CMDC:1; /*!< bit: 0 Command Complete Signal Enable */ 389 uint16_t TRFC:1; /*!< bit: 1 Transfer Complete Signal Enable */ 390 uint16_t BLKGE:1; /*!< bit: 2 Block Gap Event Signal Enable */ 391 uint16_t DMAINT:1; /*!< bit: 3 DMA Interrupt Signal Enable */ 392 uint16_t BWRRDY:1; /*!< bit: 4 Buffer Write Ready Signal Enable */ 393 uint16_t BRDRDY:1; /*!< bit: 5 Buffer Read Ready Signal Enable */ 394 uint16_t :8; /*!< bit: 6..13 Reserved */ 395 uint16_t BOOTAR:1; /*!< bit: 14 Boot Acknowledge Received Signal Enable */ 396 uint16_t :1; /*!< bit: 15 Reserved */ 397 } EMMC; /*!< Structure used for EMMC */ 398 uint16_t reg; /*!< Type used for register access */ 399 } SDHC_NISIER_Type; 400 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 401 402 /* -------- SDHC_EISIER : (SDHC Offset: 0x3A) (R/W 16) Error Interrupt Signal Enable -------- */ 403 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 404 typedef union { 405 struct { 406 uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */ 407 uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */ 408 uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */ 409 uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */ 410 uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */ 411 uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */ 412 uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */ 413 uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */ 414 uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */ 415 uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */ 416 uint16_t :6; /*!< bit: 10..15 Reserved */ 417 } bit; /*!< Structure used for bit access */ 418 struct { // EMMC mode 419 uint16_t CMDTEO:1; /*!< bit: 0 Command Timeout Error Signal Enable */ 420 uint16_t CMDCRC:1; /*!< bit: 1 Command CRC Error Signal Enable */ 421 uint16_t CMDEND:1; /*!< bit: 2 Command End Bit Error Signal Enable */ 422 uint16_t CMDIDX:1; /*!< bit: 3 Command Index Error Signal Enable */ 423 uint16_t DATTEO:1; /*!< bit: 4 Data Timeout Error Signal Enable */ 424 uint16_t DATCRC:1; /*!< bit: 5 Data CRC Error Signal Enable */ 425 uint16_t DATEND:1; /*!< bit: 6 Data End Bit Error Signal Enable */ 426 uint16_t CURLIM:1; /*!< bit: 7 Current Limit Error Signal Enable */ 427 uint16_t ACMD:1; /*!< bit: 8 Auto CMD Error Signal Enable */ 428 uint16_t ADMA:1; /*!< bit: 9 ADMA Error Signal Enable */ 429 uint16_t :2; /*!< bit: 10..11 Reserved */ 430 uint16_t BOOTAE:1; /*!< bit: 12 Boot Acknowledge Error Signal Enable */ 431 uint16_t :3; /*!< bit: 13..15 Reserved */ 432 } EMMC; /*!< Structure used for EMMC */ 433 uint16_t reg; /*!< Type used for register access */ 434 } SDHC_EISIER_Type; 435 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 436 437 /* -------- SDHC_ACESR : (SDHC Offset: 0x3C) ( R/ 16) Auto CMD Error Status -------- */ 438 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 439 typedef union { 440 struct { 441 uint16_t ACMD12NE:1; /*!< bit: 0 Auto CMD12 Not Executed */ 442 uint16_t ACMDTEO:1; /*!< bit: 1 Auto CMD Timeout Error */ 443 uint16_t ACMDCRC:1; /*!< bit: 2 Auto CMD CRC Error */ 444 uint16_t ACMDEND:1; /*!< bit: 3 Auto CMD End Bit Error */ 445 uint16_t ACMDIDX:1; /*!< bit: 4 Auto CMD Index Error */ 446 uint16_t :2; /*!< bit: 5.. 6 Reserved */ 447 uint16_t CMDNI:1; /*!< bit: 7 Command not Issued By Auto CMD12 Error */ 448 uint16_t :8; /*!< bit: 8..15 Reserved */ 449 } bit; /*!< Structure used for bit access */ 450 uint16_t reg; /*!< Type used for register access */ 451 } SDHC_ACESR_Type; 452 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 453 454 /* -------- SDHC_HC2R : (SDHC Offset: 0x3E) (R/W 16) Host Control 2 -------- */ 455 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 456 typedef union { 457 struct { 458 uint16_t UHSMS:3; /*!< bit: 0.. 2 UHS Mode Select */ 459 uint16_t VS18EN:1; /*!< bit: 3 1.8V Signaling Enable */ 460 uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */ 461 uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */ 462 uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */ 463 uint16_t :6; /*!< bit: 8..13 Reserved */ 464 uint16_t ASINTEN:1; /*!< bit: 14 Asynchronous Interrupt Enable */ 465 uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */ 466 } bit; /*!< Structure used for bit access */ 467 struct { // EMMC mode 468 uint16_t HS200EN:4; /*!< bit: 0.. 3 HS200 Mode Enable */ 469 uint16_t DRVSEL:2; /*!< bit: 4.. 5 Driver Strength Select */ 470 uint16_t EXTUN:1; /*!< bit: 6 Execute Tuning */ 471 uint16_t SLCKSEL:1; /*!< bit: 7 Sampling Clock Select */ 472 uint16_t :7; /*!< bit: 8..14 Reserved */ 473 uint16_t PVALEN:1; /*!< bit: 15 Preset Value Enable */ 474 } EMMC; /*!< Structure used for EMMC */ 475 uint16_t reg; /*!< Type used for register access */ 476 } SDHC_HC2R_Type; 477 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 478 /* -------- SDHC_CA0R : (SDHC Offset: 0x40) ( R/ 32) Capabilities 0 -------- */ 479 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 480 typedef union { 481 struct { 482 uint32_t TEOCLKF:6; /*!< bit: 0.. 5 Timeout Clock Frequency */ 483 uint32_t :1; /*!< bit: 6 Reserved */ 484 uint32_t TEOCLKU:1; /*!< bit: 7 Timeout Clock Unit */ 485 uint32_t BASECLKF:8; /*!< bit: 8..15 Base Clock Frequency */ 486 uint32_t MAXBLKL:2; /*!< bit: 16..17 Max Block Length */ 487 uint32_t ED8SUP:1; /*!< bit: 18 8-bit Support for Embedded Device */ 488 uint32_t ADMA2SUP:1; /*!< bit: 19 ADMA2 Support */ 489 uint32_t :1; /*!< bit: 20 Reserved */ 490 uint32_t HSSUP:1; /*!< bit: 21 High Speed Support */ 491 uint32_t SDMASUP:1; /*!< bit: 22 SDMA Support */ 492 uint32_t SRSUP:1; /*!< bit: 23 Suspend/Resume Support */ 493 uint32_t V33VSUP:1; /*!< bit: 24 Voltage Support 3.3V */ 494 uint32_t V30VSUP:1; /*!< bit: 25 Voltage Support 3.0V */ 495 uint32_t V18VSUP:1; /*!< bit: 26 Voltage Support 1.8V */ 496 uint32_t :1; /*!< bit: 27 Reserved */ 497 uint32_t SB64SUP:1; /*!< bit: 28 64-Bit System Bus Support */ 498 uint32_t ASINTSUP:1; /*!< bit: 29 Asynchronous Interrupt Support */ 499 uint32_t SLTYPE:2; /*!< bit: 30..31 Slot Type */ 500 } bit; /*!< Structure used for bit access */ 501 uint32_t reg; /*!< Type used for register access */ 502 } SDHC_CA0R_Type; 503 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 504 505 /* -------- SDHC_CA1R : (SDHC Offset: 0x44) ( R/ 32) Capabilities 1 -------- */ 506 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 507 typedef union { 508 struct { 509 uint32_t SDR50SUP:1; /*!< bit: 0 SDR50 Support */ 510 uint32_t SDR104SUP:1; /*!< bit: 1 SDR104 Support */ 511 uint32_t DDR50SUP:1; /*!< bit: 2 DDR50 Support */ 512 uint32_t :1; /*!< bit: 3 Reserved */ 513 uint32_t DRVASUP:1; /*!< bit: 4 Driver Type A Support */ 514 uint32_t DRVCSUP:1; /*!< bit: 5 Driver Type C Support */ 515 uint32_t DRVDSUP:1; /*!< bit: 6 Driver Type D Support */ 516 uint32_t :1; /*!< bit: 7 Reserved */ 517 uint32_t TCNTRT:4; /*!< bit: 8..11 Timer Count for Re-Tuning */ 518 uint32_t :1; /*!< bit: 12 Reserved */ 519 uint32_t TSDR50:1; /*!< bit: 13 Use Tuning for SDR50 */ 520 uint32_t :2; /*!< bit: 14..15 Reserved */ 521 uint32_t CLKMULT:8; /*!< bit: 16..23 Clock Multiplier */ 522 uint32_t :8; /*!< bit: 24..31 Reserved */ 523 } bit; /*!< Structure used for bit access */ 524 uint32_t reg; /*!< Type used for register access */ 525 } SDHC_CA1R_Type; 526 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 527 528 /* -------- SDHC_MCCAR : (SDHC Offset: 0x48) ( R/ 32) Maximum Current Capabilities -------- */ 529 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 530 typedef union { 531 struct { 532 uint32_t MAXCUR33V:8; /*!< bit: 0.. 7 Maximum Current for 3.3V */ 533 uint32_t MAXCUR30V:8; /*!< bit: 8..15 Maximum Current for 3.0V */ 534 uint32_t MAXCUR18V:8; /*!< bit: 16..23 Maximum Current for 1.8V */ 535 uint32_t :8; /*!< bit: 24..31 Reserved */ 536 } bit; /*!< Structure used for bit access */ 537 uint32_t reg; /*!< Type used for register access */ 538 } SDHC_MCCAR_Type; 539 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 540 /* -------- SDHC_FERACES : (SDHC Offset: 0x50) ( /W 16) Force Event for Auto CMD Error Status -------- */ 541 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 542 typedef union { 543 struct { 544 uint16_t ACMD12NE:1; /*!< bit: 0 Force Event for Auto CMD12 Not Executed */ 545 uint16_t ACMDTEO:1; /*!< bit: 1 Force Event for Auto CMD Timeout Error */ 546 uint16_t ACMDCRC:1; /*!< bit: 2 Force Event for Auto CMD CRC Error */ 547 uint16_t ACMDEND:1; /*!< bit: 3 Force Event for Auto CMD End Bit Error */ 548 uint16_t ACMDIDX:1; /*!< bit: 4 Force Event for Auto CMD Index Error */ 549 uint16_t :2; /*!< bit: 5.. 6 Reserved */ 550 uint16_t CMDNI:1; /*!< bit: 7 Force Event for Command Not Issued By Auto CMD12 Error */ 551 uint16_t :8; /*!< bit: 8..15 Reserved */ 552 } bit; /*!< Structure used for bit access */ 553 uint16_t reg; /*!< Type used for register access */ 554 } SDHC_FERACES_Type; 555 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 556 557 /* -------- SDHC_FEREIS : (SDHC Offset: 0x52) ( /W 16) Force Event for Error Interrupt Status -------- */ 558 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 559 typedef union { 560 struct { 561 uint16_t CMDTEO:1; /*!< bit: 0 Force Event for Command Timeout Error */ 562 uint16_t CMDCRC:1; /*!< bit: 1 Force Event for Command CRC Error */ 563 uint16_t CMDEND:1; /*!< bit: 2 Force Event for Command End Bit Error */ 564 uint16_t CMDIDX:1; /*!< bit: 3 Force Event for Command Index Error */ 565 uint16_t DATTEO:1; /*!< bit: 4 Force Event for Data Timeout Error */ 566 uint16_t DATCRC:1; /*!< bit: 5 Force Event for Data CRC Error */ 567 uint16_t DATEND:1; /*!< bit: 6 Force Event for Data End Bit Error */ 568 uint16_t CURLIM:1; /*!< bit: 7 Force Event for Current Limit Error */ 569 uint16_t ACMD:1; /*!< bit: 8 Force Event for Auto CMD Error */ 570 uint16_t ADMA:1; /*!< bit: 9 Force Event for ADMA Error */ 571 uint16_t :2; /*!< bit: 10..11 Reserved */ 572 uint16_t BOOTAE:1; /*!< bit: 12 Force Event for Boot Acknowledge Error */ 573 uint16_t :3; /*!< bit: 13..15 Reserved */ 574 } bit; /*!< Structure used for bit access */ 575 uint16_t reg; /*!< Type used for register access */ 576 } SDHC_FEREIS_Type; 577 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 578 579 /* -------- SDHC_AESR : (SDHC Offset: 0x54) ( R/ 8) ADMA Error Status -------- */ 580 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 581 typedef union { 582 struct { 583 uint8_t ERRST:2; /*!< bit: 0.. 1 ADMA Error State */ 584 uint8_t LMIS:1; /*!< bit: 2 ADMA Length Mismatch Error */ 585 uint8_t :5; /*!< bit: 3.. 7 Reserved */ 586 } bit; /*!< Structure used for bit access */ 587 uint8_t reg; /*!< Type used for register access */ 588 } SDHC_AESR_Type; 589 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 590 591 /* -------- SDHC_ASAR : (SDHC Offset: 0x58) (R/W 32) ADMA System Address -------- */ 592 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 593 typedef union { 594 struct { 595 uint32_t ADMASA:32; /*!< bit: 0..31 ADMA System Address */ 596 } bit; /*!< Structure used for bit access */ 597 uint32_t reg; /*!< Type used for register access */ 598 } SDHC_ASAR_Type; 599 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 600 601 /* -------- SDHC_PVR : (SDHC Offset: 0x60) (R/W 16) Preset Value n -------- */ 602 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 603 typedef union { 604 struct { 605 uint16_t SDCLKFSEL:10; /*!< bit: 0.. 9 SDCLK Frequency Select Value for Initialization */ 606 uint16_t CLKGSEL:1; /*!< bit: 10 Clock Generator Select Value for Initialization */ 607 uint16_t :3; /*!< bit: 11..13 Reserved */ 608 uint16_t DRVSEL:2; /*!< bit: 14..15 Driver Strength Select Value for Initialization */ 609 } bit; /*!< Structure used for bit access */ 610 uint16_t reg; /*!< Type used for register access */ 611 } SDHC_PVR_Type; 612 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 613 614 /* -------- SDHC_SISR : (SDHC Offset: 0xFC) ( R/ 16) Slot Interrupt Status -------- */ 615 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 616 typedef union { 617 struct { 618 uint16_t INTSSL:1; /*!< bit: 0 Interrupt Signal for Each Slot */ 619 uint16_t :15; /*!< bit: 1..15 Reserved */ 620 } bit; /*!< Structure used for bit access */ 621 uint16_t reg; /*!< Type used for register access */ 622 } SDHC_SISR_Type; 623 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 624 625 /* -------- SDHC_HCVR : (SDHC Offset: 0xFE) ( R/ 16) Host Controller Version -------- */ 626 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 627 typedef union { 628 struct { 629 uint16_t SVER:8; /*!< bit: 0.. 7 Spec Version */ 630 uint16_t VVER:8; /*!< bit: 8..15 Vendor Version */ 631 } bit; /*!< Structure used for bit access */ 632 uint16_t reg; /*!< Type used for register access */ 633 } SDHC_HCVR_Type; 634 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 635 636 /* -------- SDHC_APSR : (SDHC Offset: 0x200) ( R/ 32) Additional Present State Register -------- */ 637 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 638 typedef union { 639 struct { 640 uint32_t HDATLL:4; /*!< bit: 0.. 3 High Line Level */ 641 uint32_t :28; /*!< bit: 4..32 reserved */ 642 } bit; /*!< Structure used for bit access */ 643 uint32_t reg; /*!< Type used for register access */ 644 } SDHC_APSR_Type; 645 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 646 647 /* -------- SDHC_MC1R : (SDHC Offset: 0x204) (R/W 8) MMC Control 1 -------- */ 648 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 649 typedef union { 650 struct { 651 uint8_t CMDTYP:2; /*!< bit: 0.. 1 e.MMC Command Type */ 652 uint8_t :1; /*!< bit: 2 Reserved */ 653 uint8_t DDR:1; /*!< bit: 3 e.MMC HSDDR Mode */ 654 uint8_t OPD:1; /*!< bit: 4 e.MMC Open Drain Mode */ 655 uint8_t BOOTA:1; /*!< bit: 5 e.MMC Boot Acknowledge Enable */ 656 uint8_t RSTN:1; /*!< bit: 6 e.MMC Reset Signal */ 657 uint8_t FCD:1; /*!< bit: 7 e.MMC Force Card Detect */ 658 } bit; /*!< Structure used for bit access */ 659 uint8_t reg; /*!< Type used for register access */ 660 } SDHC_MC1R_Type; 661 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 662 663 /* -------- SDHC_MC2R : (SDHC Offset: 0x205) ( /W 8) MMC Control 2 -------- */ 664 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 665 typedef union { 666 struct { 667 uint8_t SRESP:1; /*!< bit: 0 e.MMC Abort Wait IRQ */ 668 uint8_t ABOOT:1; /*!< bit: 1 e.MMC Abort Boot */ 669 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 670 } bit; /*!< Structure used for bit access */ 671 uint8_t reg; /*!< Type used for register access */ 672 } SDHC_MC2R_Type; 673 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 674 675 /* -------- SDHC_ACR : (SDHC Offset: 0x208) (R/W 32) AHB Control -------- */ 676 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 677 typedef union { 678 struct { 679 uint32_t BMAX:2; /*!< bit: 0.. 1 AHB Maximum Burst */ 680 uint32_t :30; /*!< bit: 2..31 Reserved */ 681 } bit; /*!< Structure used for bit access */ 682 uint32_t reg; /*!< Type used for register access */ 683 } SDHC_ACR_Type; 684 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 685 686 /* -------- SDHC_CC2R : (SDHC Offset: 0x20C) (R/W 32) Clock Control 2 -------- */ 687 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 688 typedef union { 689 struct { 690 uint32_t FSDCLKD:1; /*!< bit: 0 Force SDCK Disabled */ 691 uint32_t :31; /*!< bit: 1..31 Reserved */ 692 } bit; /*!< Structure used for bit access */ 693 uint32_t reg; /*!< Type used for register access */ 694 } SDHC_CC2R_Type; 695 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 696 697 /* -------- SDHC_CACR : (SDHC Offset: 0x230) (R/W 32) Capabilities Control -------- */ 698 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 699 typedef union { 700 struct { 701 uint32_t CAPWREN:1; /*!< bit: 0 Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) */ 702 uint32_t :7; /*!< bit: 1.. 7 Reserved */ 703 uint32_t KEY:8; /*!< bit: 8..15 Key (0x46) */ 704 uint32_t :16; /*!< bit: 16..31 Reserved */ 705 } bit; /*!< Structure used for bit access */ 706 uint32_t reg; /*!< Type used for register access */ 707 } SDHC_CACR_Type; 708 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 709 710 /* -------- SDHC_DBGR : (SDHC Offset: 0x234) (R/W 8) Debug -------- */ 711 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 712 typedef union { 713 struct { 714 uint8_t NIDBG:1; /*!< bit: 0 Non-intrusive debug enable */ 715 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 716 } bit; /*!< Structure used for bit access */ 717 uint8_t reg; /*!< Type used for register access */ 718 } SDHC_DBGR_Type; 719 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 720 721 /** \brief SDHC hardware registers */ 722 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 723 typedef struct { 724 __IO SDHC_SSAR_Type SSAR; /**< \brief Offset: 0x000 (R/W 32) SDMA System Address / Argument 2 */ 725 __IO SDHC_BSR_Type BSR; /**< \brief Offset: 0x004 (R/W 16) Block Size */ 726 __IO SDHC_BCR_Type BCR; /**< \brief Offset: 0x006 (R/W 16) Block Count */ 727 __IO SDHC_ARG1R_Type ARG1R; /**< \brief Offset: 0x008 (R/W 32) Argument 1 */ 728 __IO SDHC_TMR_Type TMR; /**< \brief Offset: 0x00C (R/W 16) Transfer Mode */ 729 __IO SDHC_CR_Type CR; /**< \brief Offset: 0x00E (R/W 16) Command */ 730 __I SDHC_RR_Type RR[4]; /**< \brief Offset: 0x010 (R/ 32) Response */ 731 __IO SDHC_BDPR_Type BDPR; /**< \brief Offset: 0x020 (R/W 32) Buffer Data Port */ 732 __I SDHC_PSR_Type PSR; /**< \brief Offset: 0x024 (R/ 32) Present State */ 733 __IO SDHC_HC1R_Type HC1R; /**< \brief Offset: 0x028 (R/W 8) Host Control 1 */ 734 __IO SDHC_PCR_Type PCR; /**< \brief Offset: 0x029 (R/W 8) Power Control */ 735 __IO SDHC_BGCR_Type BGCR; /**< \brief Offset: 0x02A (R/W 8) Block Gap Control */ 736 __IO SDHC_WCR_Type WCR; /**< \brief Offset: 0x02B (R/W 8) Wakeup Control */ 737 __IO SDHC_CCR_Type CCR; /**< \brief Offset: 0x02C (R/W 16) Clock Control */ 738 __IO SDHC_TCR_Type TCR; /**< \brief Offset: 0x02E (R/W 8) Timeout Control */ 739 __IO SDHC_SRR_Type SRR; /**< \brief Offset: 0x02F (R/W 8) Software Reset */ 740 __IO SDHC_NISTR_Type NISTR; /**< \brief Offset: 0x030 (R/W 16) Normal Interrupt Status */ 741 __IO SDHC_EISTR_Type EISTR; /**< \brief Offset: 0x032 (R/W 16) Error Interrupt Status */ 742 __IO SDHC_NISTER_Type NISTER; /**< \brief Offset: 0x034 (R/W 16) Normal Interrupt Status Enable */ 743 __IO SDHC_EISTER_Type EISTER; /**< \brief Offset: 0x036 (R/W 16) Error Interrupt Status Enable */ 744 __IO SDHC_NISIER_Type NISIER; /**< \brief Offset: 0x038 (R/W 16) Normal Interrupt Signal Enable */ 745 __IO SDHC_EISIER_Type EISIER; /**< \brief Offset: 0x03A (R/W 16) Error Interrupt Signal Enable */ 746 __I SDHC_ACESR_Type ACESR; /**< \brief Offset: 0x03C (R/ 16) Auto CMD Error Status */ 747 __IO SDHC_HC2R_Type HC2R; /**< \brief Offset: 0x03E (R/W 16) Host Control 2 */ 748 __I SDHC_CA0R_Type CA0R; /**< \brief Offset: 0x040 (R/ 32) Capabilities 0 */ 749 __I SDHC_CA1R_Type CA1R; /**< \brief Offset: 0x044 (R/ 32) Capabilities 1 */ 750 __I SDHC_MCCAR_Type MCCAR; /**< \brief Offset: 0x048 (R/ 32) Maximum Current Capabilities */ 751 RoReg8 Reserved1[0x4]; 752 __O SDHC_FERACES_Type FERACES; /**< \brief Offset: 0x050 ( /W 16) Force Event for Auto CMD Error Status */ 753 __O SDHC_FEREIS_Type FEREIS; /**< \brief Offset: 0x052 ( /W 16) Force Event for Error Interrupt Status */ 754 __I SDHC_AESR_Type AESR; /**< \brief Offset: 0x054 (R/ 8) ADMA Error Status */ 755 RoReg8 Reserved2[0x3]; 756 __IO SDHC_ASAR_Type ASAR[1]; /**< \brief Offset: 0x058 (R/W 32) ADMA System Address n */ 757 RoReg8 Reserved3[0x4]; 758 __IO SDHC_PVR_Type PVR[8]; /**< \brief Offset: 0x060 (R/W 16) Preset Value n */ 759 RoReg8 Reserved4[0x8C]; 760 __I SDHC_SISR_Type SISR; /**< \brief Offset: 0x0FC (R/ 16) Slot Interrupt Status */ 761 __I SDHC_HCVR_Type HCVR; /**< \brief Offset: 0x0FE (R/ 16) Host Controller Version */ 762 RoReg8 Reserved5[0x100]; 763 __I SDHC_APSR_Type APSR; /**< Offset: 0x200 (R/ 32) Additional Present State Register */ 764 __IO SDHC_MC1R_Type MC1R; /**< \brief Offset: 0x204 (R/W 8) MMC Control 1 */ 765 __O SDHC_MC2R_Type MC2R; /**< \brief Offset: 0x205 ( /W 8) MMC Control 2 */ 766 RoReg8 Reserved6[0x2]; 767 __IO SDHC_ACR_Type ACR; /**< \brief Offset: 0x208 (R/W 32) AHB Control */ 768 __IO SDHC_CC2R_Type CC2R; /**< \brief Offset: 0x20C (R/W 32) Clock Control 2 */ 769 RoReg8 Reserved7[0x20]; 770 __IO SDHC_CACR_Type CACR; /**< \brief Offset: 0x230 (R/W 32) Capabilities Control */ 771 __IO SDHC_DBGR_Type DBGR; /**< \brief Offset: 0x234 (R/W 8) Debug */ 772 } Sdhc; 773 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 774 775 #endif /* _MICROCHIP_PIC32CXSG_SDHC_COMPONENT_FIXUP_H_ */ 776
