1 /* 2 * Copyright (c) 2024 Microchip 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 7 #ifndef _MICROCHIP_PIC32CXSG_NVMCTRL_COMPONENT_FIXUP_H_ 8 #define _MICROCHIP_PIC32CXSG_NVMCTRL_COMPONENT_FIXUP_H_ 9 10 /* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */ 11 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 12 typedef union { 13 struct { 14 uint16_t :2; /*!< bit: 0.. 1 Reserved */ 15 uint16_t AUTOWS:1; /*!< bit: 2 Auto Wait State Enable */ 16 uint16_t SUSPEN:1; /*!< bit: 3 Suspend Enable */ 17 uint16_t WMODE:2; /*!< bit: 4.. 5 Write Mode */ 18 uint16_t PRM:2; /*!< bit: 6.. 7 Power Reduction Mode during Sleep */ 19 uint16_t RWS:4; /*!< bit: 8..11 NVM Read Wait States */ 20 uint16_t AHBNS0:1; /*!< bit: 12 Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated */ 21 uint16_t AHBNS1:1; /*!< bit: 13 Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated */ 22 uint16_t CACHEDIS0:1; /*!< bit: 14 AHB0 Cache Disable */ 23 uint16_t CACHEDIS1:1; /*!< bit: 15 AHB1 Cache Disable */ 24 } bit; /*!< Structure used for bit access */ 25 uint16_t reg; /*!< Type used for register access */ 26 } NVMCTRL_CTRLA_Type; 27 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 28 29 /* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) ( /W 16) Control B -------- */ 30 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 31 typedef union { 32 struct { 33 uint16_t CMD:7; /*!< bit: 0.. 6 Command */ 34 uint16_t :1; /*!< bit: 7 Reserved */ 35 uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */ 36 } bit; /*!< Structure used for bit access */ 37 uint16_t reg; /*!< Type used for register access */ 38 } NVMCTRL_CTRLB_Type; 39 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 40 41 /* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) ( R/ 32) NVM Parameter -------- */ 42 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 43 typedef union { 44 struct { 45 uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */ 46 uint32_t PSZ:3; /*!< bit: 16..18 Page Size */ 47 uint32_t :12; /*!< bit: 19..30 Reserved */ 48 uint32_t SEE:1; /*!< bit: 31 SmartEEPROM Supported */ 49 } bit; /*!< Structure used for bit access */ 50 uint32_t reg; /*!< Type used for register access */ 51 } NVMCTRL_PARAM_Type; 52 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 53 54 /* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */ 55 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 56 typedef union { 57 struct { 58 uint16_t DONE:1; /*!< bit: 0 Command Done Interrupt Clear */ 59 uint16_t ADDRE:1; /*!< bit: 1 Address Error */ 60 uint16_t PROGE:1; /*!< bit: 2 Programming Error Interrupt Clear */ 61 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Interrupt Clear */ 62 uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error Interrupt Clear */ 63 uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error Interrupt Clear */ 64 uint16_t NVME:1; /*!< bit: 6 NVM Error Interrupt Clear */ 65 uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Interrupt Clear */ 66 uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full Interrupt Clear */ 67 uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow Interrupt Clear */ 68 uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed Interrupt Clear */ 69 uint16_t :5; /*!< bit: 11..15 Reserved */ 70 } bit; /*!< Structure used for bit access */ 71 uint16_t reg; /*!< Type used for register access */ 72 } NVMCTRL_INTENCLR_Type; 73 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 74 75 /* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x0E) (R/W 16) Interrupt Enable Set -------- */ 76 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 77 typedef union { 78 struct { 79 uint16_t DONE:1; /*!< bit: 0 Command Done Interrupt Enable */ 80 uint16_t ADDRE:1; /*!< bit: 1 Address Error Interrupt Enable */ 81 uint16_t PROGE:1; /*!< bit: 2 Programming Error Interrupt Enable */ 82 uint16_t LOCKE:1; /*!< bit: 3 Lock Error Interrupt Enable */ 83 uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error Interrupt Enable */ 84 uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error Interrupt Enable */ 85 uint16_t NVME:1; /*!< bit: 6 NVM Error Interrupt Enable */ 86 uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Interrupt Enable */ 87 uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full Interrupt Enable */ 88 uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow Interrupt Enable */ 89 uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed Interrupt Enable */ 90 uint16_t :5; /*!< bit: 11..15 Reserved */ 91 } bit; /*!< Structure used for bit access */ 92 uint16_t reg; /*!< Type used for register access */ 93 } NVMCTRL_INTENSET_Type; 94 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 95 96 /* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x10) (R/W 16) Interrupt Flag Status and Clear -------- */ 97 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 98 typedef union { // __I to avoid read-modify-write on write-to-clear register 99 struct { 100 __I uint16_t DONE:1; /*!< bit: 0 Command Done */ 101 __I uint16_t ADDRE:1; /*!< bit: 1 Address Error */ 102 __I uint16_t PROGE:1; /*!< bit: 2 Programming Error */ 103 __I uint16_t LOCKE:1; /*!< bit: 3 Lock Error */ 104 __I uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error */ 105 __I uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error */ 106 __I uint16_t NVME:1; /*!< bit: 6 NVM Error */ 107 __I uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Operation */ 108 __I uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full */ 109 __I uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow */ 110 __I uint16_t SEEWRC:1; /*!< bit: 10 SEE Write Completed */ 111 __I uint16_t :5; /*!< bit: 11..15 Reserved */ 112 } bit; /*!< Structure used for bit access */ 113 uint16_t reg; /*!< Type used for register access */ 114 } NVMCTRL_INTFLAG_Type; 115 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 116 117 /* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x12) ( R/ 16) Status -------- */ 118 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 119 typedef union { 120 struct { 121 uint16_t READY:1; /*!< bit: 0 Ready to accept a command */ 122 uint16_t PRM:1; /*!< bit: 1 Power Reduction Mode */ 123 uint16_t LOAD:1; /*!< bit: 2 NVM Page Buffer Active Loading */ 124 uint16_t SUSP:1; /*!< bit: 3 NVM Write Or Erase Operation Is Suspended */ 125 uint16_t AFIRST:1; /*!< bit: 4 BANKA First */ 126 uint16_t BPDIS:1; /*!< bit: 5 Boot Loader Protection Disable */ 127 uint16_t :2; /*!< bit: 6.. 7 Reserved */ 128 uint16_t BOOTPROT:4; /*!< bit: 8..11 Boot Loader Protection Size */ 129 uint16_t DPBE:1; /*!< bit: 12 Dual Boot Protection Enable */ 130 uint16_t BPHL:1; /*!< bit: 13 Boot Protect Hard Lock */ 131 uint16_t :2; /*!< bit: 14..15 Reserved */ 132 } bit; /*!< Structure used for bit access */ 133 uint16_t reg; /*!< Type used for register access */ 134 } NVMCTRL_STATUS_Type; 135 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 136 137 /* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x14) (R/W 32) Address -------- */ 138 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 139 typedef union { 140 struct { 141 uint32_t ADDR:24; /*!< bit: 0..23 NVM Address */ 142 uint32_t :8; /*!< bit: 24..31 Reserved */ 143 } bit; /*!< Structure used for bit access */ 144 uint32_t reg; /*!< Type used for register access */ 145 } NVMCTRL_ADDR_Type; 146 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 147 148 /* -------- NVMCTRL_RUNLOCK : (NVMCTRL Offset: 0x18) ( R/ 32) Lock Section -------- */ 149 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 150 typedef union { 151 struct { 152 uint32_t RUNLOCK:32; /*!< bit: 0..31 Region Un-Lock Bits */ 153 } bit; /*!< Structure used for bit access */ 154 uint32_t reg; /*!< Type used for register access */ 155 } NVMCTRL_RUNLOCK_Type; 156 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 157 158 /* -------- NVMCTRL_PBLDATA : (NVMCTRL Offset: 0x1C) ( R/ 32) Page Buffer Load Data x -------- */ 159 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 160 typedef union { 161 struct { 162 uint32_t DATA:32; /*!< bit: 0..31 Page Buffer Data */ 163 } bit; /*!< Structure used for bit access */ 164 uint32_t reg; /*!< Type used for register access */ 165 } NVMCTRL_PBLDATA_Type; 166 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 167 168 /* -------- NVMCTRL_ECCERR : (NVMCTRL Offset: 0x24) ( R/ 32) ECC Error Status Register -------- */ 169 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 170 typedef union { 171 struct { 172 uint32_t ADDR:24; /*!< bit: 0..23 Error Address */ 173 uint32_t :4; /*!< bit: 24..27 Reserved */ 174 uint32_t TYPEL:2; /*!< bit: 28..29 Low Double-Word Error Type */ 175 uint32_t TYPEH:2; /*!< bit: 30..31 High Double-Word Error Type */ 176 } bit; /*!< Structure used for bit access */ 177 uint32_t reg; /*!< Type used for register access */ 178 } NVMCTRL_ECCERR_Type; 179 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 180 181 /* -------- NVMCTRL_DBGCTRL : (NVMCTRL Offset: 0x28) (R/W 8) Debug Control -------- */ 182 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 183 typedef union { 184 struct { 185 uint8_t ECCDIS:1; /*!< bit: 0 Debugger ECC Read Disable */ 186 uint8_t ECCELOG:1; /*!< bit: 1 Debugger ECC Error Tracking Mode */ 187 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 188 } bit; /*!< Structure used for bit access */ 189 uint8_t reg; /*!< Type used for register access */ 190 } NVMCTRL_DBGCTRL_Type; 191 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 192 193 /* -------- NVMCTRL_BCTRL : (NVMCTRL Offset: 0x29) (R/W 8) Boot Control -------- */ 194 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 195 typedef union { 196 struct { 197 uint8_t BRPE:1; /*!< bit: 0 Boot Read Protection Enable */ 198 uint8_t :7; /*!< bit: 1.. 7 Reserved */ 199 } bit; /*!< Structure used for bit access */ 200 uint8_t reg; /*!< Type used for register access */ 201 } NVMCTRL_BCTRL_Type; 202 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 203 204 /* -------- NVMCTRL_SEECFG : (NVMCTRL Offset: 0x2A) (R/W 8) SmartEEPROM Configuration Register -------- */ 205 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 206 typedef union { 207 struct { 208 uint8_t WMODE:1; /*!< bit: 0 Write Mode */ 209 uint8_t APRDIS:1; /*!< bit: 1 Automatic Page Reallocation Disable */ 210 uint8_t :6; /*!< bit: 2.. 7 Reserved */ 211 } bit; /*!< Structure used for bit access */ 212 uint8_t reg; /*!< Type used for register access */ 213 } NVMCTRL_SEECFG_Type; 214 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 215 216 /* -------- NVMCTRL_SEESTAT : (NVMCTRL Offset: 0x2C) ( R/ 32) SmartEEPROM Status Register -------- */ 217 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 218 typedef union { 219 struct { 220 uint32_t ASEES:1; /*!< bit: 0 Active SmartEEPROM Sector */ 221 uint32_t LOAD:1; /*!< bit: 1 Page Buffer Loaded */ 222 uint32_t BUSY:1; /*!< bit: 2 Busy */ 223 uint32_t LOCK:1; /*!< bit: 3 SmartEEPROM Write Access Is Locked */ 224 uint32_t RLOCK:1; /*!< bit: 4 SmartEEPROM Write Access To Register Address Space Is Locked */ 225 uint32_t :3; /*!< bit: 5.. 7 Reserved */ 226 uint32_t SBLK:4; /*!< bit: 8..11 Blocks Number In a Sector */ 227 uint32_t :4; /*!< bit: 12..15 Reserved */ 228 uint32_t PSZ:3; /*!< bit: 16..18 SmartEEPROM Page Size */ 229 uint32_t :13; /*!< bit: 19..31 Reserved */ 230 } bit; /*!< Structure used for bit access */ 231 uint32_t reg; /*!< Type used for register access */ 232 } NVMCTRL_SEESTAT_Type; 233 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 234 235 /** \brief NVMCTRL APB hardware registers */ 236 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) 237 typedef struct { 238 __IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */ 239 RoReg8 Reserved1[0x2]; 240 __O NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 ( /W 16) Control B */ 241 RoReg8 Reserved2[0x2]; 242 __I NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/ 32) NVM Parameter */ 243 __IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */ 244 __IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x0E (R/W 16) Interrupt Enable Set */ 245 __IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 16) Interrupt Flag Status and Clear */ 246 __I NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x12 (R/ 16) Status */ 247 __IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x14 (R/W 32) Address */ 248 __I NVMCTRL_RUNLOCK_Type RUNLOCK; /**< \brief Offset: 0x18 (R/ 32) Lock Section */ 249 __I NVMCTRL_PBLDATA_Type PBLDATA[2]; /**< \brief Offset: 0x1C (R/ 32) Page Buffer Load Data x */ 250 __I NVMCTRL_ECCERR_Type ECCERR; /**< \brief Offset: 0x24 (R/ 32) ECC Error Status Register */ 251 __IO NVMCTRL_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x28 (R/W 8) Debug Control */ 252 __IO NVMCTRL_BCTRL_Type BCTRL; /**< \brief Offset: 0x29 (R/W 8) Boot Control */ 253 __IO NVMCTRL_SEECFG_Type SEECFG; /**< \brief Offset: 0x2A (R/W 8) SmartEEPROM Configuration Register */ 254 RoReg8 Reserved4[0x1]; 255 __I NVMCTRL_SEESTAT_Type SEESTAT; /**< \brief Offset: 0x2C (R/ 32) SmartEEPROM Status Register */ 256 } Nvmctrl; 257 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ 258 259 #endif /* _MICROCHIP_PIC32CXSG_NVMCTRL_COMPONENT_FIXUP_H_ */ 260
