| /hal_microchip-3.7.0/mec5/drivers/ |
| D | mec_espi_oob.c | 42 static uint32_t msk_to_girq_bitmap(uint8_t msk) in msk_to_girq_bitmap() argument
46 if (msk & MEC_ESPI_OOB_DIR_UP) { in msk_to_girq_bitmap()
49 if (msk & MEC_ESPI_OOB_DIR_DN) { in msk_to_girq_bitmap()
58 uint32_t msk = 0; in bitmap_to_msk() local
61 msk |= MEC_ESPI_OOB_DIR_UP; in bitmap_to_msk()
64 msk |= MEC_ESPI_OOB_DIR_DN; in bitmap_to_msk()
67 return msk; in bitmap_to_msk()
72 void mec_hal_espi_oob_girq_ctrl(uint8_t enable, uint8_t msk) in mec_hal_espi_oob_girq_ctrl() argument
74 uint32_t bitmap = msk_to_girq_bitmap(msk); in mec_hal_espi_oob_girq_ctrl()
79 void mec_hal_espi_oob_girq_status_clr(uint8_t msk) in mec_hal_espi_oob_girq_status_clr() argument
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| D | mec_ecs.c | 78 uint32_t msk, temp, val; in mec_hal_ecs_debug_port() local
82 msk = (uint32_t)~MEC_BIT(MEC_ECS_DBG_CTRL_EN_Pos); in mec_hal_ecs_debug_port()
86 msk = MEC_ECS_DBG_CTRL_CFG_Msk; in mec_hal_ecs_debug_port()
90 msk = MEC_ECS_DBG_CTRL_CFG_Msk; in mec_hal_ecs_debug_port()
94 msk = MEC_ECS_DBG_CTRL_CFG_Msk; in mec_hal_ecs_debug_port()
101 temp = MEC_ECS->DBG_CTRL & ~msk; in mec_hal_ecs_debug_port()
114 uint32_t msk = 0, val = 0; in mec_hal_ecs_analog_comparator_config() local
116 msk = MEC_BIT(MEC_ECS_CMPSC_DSLP0_Pos) | MEC_BIT(MEC_ECS_CMPSC_DSLP1_Pos); in mec_hal_ecs_analog_comparator_config()
125 MEC_ECS->CMPSC = (MEC_ECS->CMPSC & (uint32_t)~msk) | val; in mec_hal_ecs_analog_comparator_config()
127 msk = (MEC_BIT(MEC_ECS_CMPC_EN0_Pos) | MEC_BIT(MEC_ECS_CMPC_LKCFG0_Pos) in mec_hal_ecs_analog_comparator_config()
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| D | mec_kbc.c | 71 uint8_t ctrl = 0u, msk = 0u, val = 0u; in mec_hal_kbc_init() local
127 msk |= MEC_KBC_KESTATUS_UD0_Msk; in mec_hal_kbc_init()
134 msk |= MEC_KBC_KESTATUS_UD1_Msk; in mec_hal_kbc_init()
141 msk |= MEC_KBC_KESTATUS_UD2_Msk; in mec_hal_kbc_init()
150 if (msk) { in mec_hal_kbc_init()
151 base->KESTATUS = (base->KESTATUS & ~msk) | val; in mec_hal_kbc_init()
306 void mec_hal_kbc_status_wr(struct mec_kbc_regs *base, uint8_t val, uint8_t msk) in mec_hal_kbc_status_wr() argument
314 base->KESTATUS = (base->KESTATUS & ~msk) | (val & msk); in mec_hal_kbc_status_wr()
317 void mec_hal_kbc_status_set(struct mec_kbc_regs *base, uint8_t msk) in mec_hal_kbc_status_set() argument
325 base->KESTATUS |= msk; in mec_hal_kbc_status_set()
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| D | mec_espi.c | 160 uint8_t msk = MEC_ESPI_IO_CAPFC_MAX_PLD_SIZE_Msk; in set_fc_max_pld() local
164 iobase->CAPFC = (iobase->CAPFC & ~msk) | regval; in set_fc_max_pld()
211 uint8_t msk = MEC_ESPI_IO_CAPFC_SHARING_SUPP_Msk; in set_fc_shared_mode() local
214 iobase->CAPFC = (iobase->CAPFC & ~msk) | regval; in set_fc_shared_mode()
228 uint8_t msk = (MEC_ESPI_IO_CAPFC_MAX_PLD_SIZE_Msk | MEC_ESPI_IO_CAPFC_SHARING_SUPP_Msk in set_fc_capabilities() local
244 iobase->CAPFC = (iobase->CAPFC & ~msk) | regval; in set_fc_capabilities()
535 uint32_t msk = (MEC_ESPI_IO_CAP0_PC_SUPP_Msk | MEC_ESPI_IO_CAP0_VW_SUPP_Msk in set_espi_global_cap() local
551 iobase->CAP0 = (iobase->CAP0 & (uint8_t)~msk) | (uint8_t)(cap & msk); in set_espi_global_cap()
561 msk = (MEC_ESPI_IO_CAP1_MAX_FREQ_SUPP_Msk | MEC_ESPI_IO_CAP1_IO_MODE_SUPP_Msk in set_espi_global_cap()
563 iobase->CAP1 = (iobase->CAP1 & (uint8_t)~msk) | (uint8_t)(cap & msk); in set_espi_global_cap()
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| D | mec_tach.c | 165 uint32_t msk = 0; in mec_hal_tach_intr_enable() local
172 msk |= MEC_BIT(MEC_TACH_CTRL_ENOOL_Pos); in mec_hal_tach_intr_enable()
176 msk |= MEC_BIT(MEC_TACH_CTRL_CNTRDY_IEN_Pos); in mec_hal_tach_intr_enable()
180 msk |= MEC_BIT(MEC_TACH_CTRL_INTOG_IEN_Pos); in mec_hal_tach_intr_enable()
183 if (msk) { in mec_hal_tach_intr_enable()
185 regs->CTRL |= msk; in mec_hal_tach_intr_enable()
187 regs->CTRL &= (uint32_t)~msk; in mec_hal_tach_intr_enable()
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| D | mec_btimer.c | 153 uint32_t ctrl = 0, msk = 0; in mec_hal_btimer_reset() local
160 msk |= MEC_BTMR_CTRL_PRESCALE_Msk; in mec_hal_btimer_reset()
164 msk |= MEC_BTMR_CTRL_CNT_DIR_Msk; in mec_hal_btimer_reset()
171 if (msk) { in mec_hal_btimer_reset()
172 regs->CTRL = (regs->CTRL & (uint32_t)~msk) | (ctrl & msk); in mec_hal_btimer_reset()
273 uint32_t msk = (MEC_BIT(MEC_BTMR_CTRL_ENABLE_Pos) | MEC_BIT(MEC_BTMR_CTRL_START_Pos)); in mec_hal_btimer_is_started() local
275 if ((regs->CTRL & msk) == msk) { in mec_hal_btimer_is_started()
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| D | mec_espi_fc.c | 114 void mec_hal_espi_fc_intr_ctrl(struct mec_espi_io_regs *iobase, uint32_t msk, uint8_t en) in mec_hal_espi_fc_intr_ctrl() argument
122 if (msk & MEC_BIT(MEC_ESPI_FC_INTR_DONE_POS)) { in mec_hal_espi_fc_intr_ctrl()
125 if (msk & MEC_BIT(MEC_ESPI_FC_INTR_CHEN_CHG_POS)) { in mec_hal_espi_fc_intr_ctrl()
145 void mec_hal_espi_fc_status_clr(struct mec_espi_io_regs *iobase, uint32_t msk) in mec_hal_espi_fc_status_clr() argument
151 iobase->FCSTS = msk; in mec_hal_espi_fc_status_clr()
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| D | mec_espi_oob.h | 56 void mec_hal_espi_oob_girq_ctrl(uint8_t enable, uint8_t msk);
57 void mec_hal_espi_oob_girq_status_clr(uint8_t msk);
75 void mec_hal_espi_oob_intr_ctrl(struct mec_espi_io_regs *iobase, uint32_t msk, uint8_t en);
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| D | mec_espi_vw.c | 392 uint32_t isel = 0, msk = MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_Msk; in mec_hal_espi_vw_ct_irq_sel_set() local
401 isel = vw_ct_ien_xlat_tbl[irq_sel] & msk; in mec_hal_espi_vw_ct_irq_sel_set()
403 msk <<= (src_idx * 8u); in mec_hal_espi_vw_ct_irq_sel_set()
405 ctvw->SRC_ISELS = (ctvw->SRC_ISELS & ~msk) | isel; in mec_hal_espi_vw_ct_irq_sel_set()
483 uint32_t msk = 0xfu << i; in mec_hal_espi_vwg_ct_config() local
489 r[1] = ((r[1] & ~msk) | ((uint32_t)vw_ct_ien_xlat_tbl[j] << (i * 8))); in mec_hal_espi_vwg_ct_config()
582 uint32_t msk = MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_Msk << (src_idx * 8u); in mec_hal_espi_vw_ct_irqsel_set() local
583 uint32_t temp = ctvw->SRC_ISELS & ~msk; in mec_hal_espi_vw_ct_irqsel_set()
585 temp |= ((xlat_isel(irq_sel) << pos) & msk); in mec_hal_espi_vw_ct_irqsel_set()
628 uint32_t msk = MEC_ESPI_VW_CTVW_SRC_ISELS_SRC0_IRQ_SEL_Msk << (src_idx * 8u); in mec_hal_espi_vw_ct_config() local
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| D | mec_kbc_api.h | 97 void mec_hal_kbc_status_wr(struct mec_kbc_regs *base, uint8_t val, uint8_t msk);
100 void mec_hal_kbc_status_set(struct mec_kbc_regs *base, uint8_t msk);
103 void mec_hal_kbc_status_clear(struct mec_kbc_regs *base, uint8_t msk);
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| D | mec_espi_fc.h | 74 void mec_hal_espi_fc_intr_ctrl(struct mec_espi_io_regs *iobase, uint32_t msk, uint8_t en);
76 void mec_hal_espi_fc_status_clr(struct mec_espi_io_regs *iobase, uint32_t msk);
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| D | mec_qspi.c | 544 uint32_t val = 0, msk = 0; in mec_hal_qspi_options() local
551 msk |= MEC_BIT(MEC_QSPI_MODE_ACTV_Pos); in mec_hal_qspi_options()
557 msk |= MEC_BIT(MEC_QSPI_MODE_TAFDMA_Pos); in mec_hal_qspi_options()
563 msk |= MEC_BIT(MEC_QSPI_MODE_RX_LDMA_Pos); in mec_hal_qspi_options()
569 msk |= MEC_BIT(MEC_QSPI_MODE_TX_LDMA_Pos); in mec_hal_qspi_options()
575 regs->MODE = (regs->MODE & ~msk) | (val & msk); in mec_hal_qspi_options()
640 int mec_hal_qspi_hw_status_clr(struct mec_qspi_regs *base, uint32_t msk) in mec_hal_qspi_hw_status_clr() argument
646 base->STATUS = msk; in mec_hal_qspi_hw_status_clr()
677 int mec_hal_qspi_intr_ctrl_msk(struct mec_qspi_regs *base, int enable, uint32_t msk) in mec_hal_qspi_intr_ctrl_msk() argument
684 base->INTR_CTRL |= msk; in mec_hal_qspi_intr_ctrl_msk()
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| D | mec_espi_vw.h | 188 uint8_t val, uint8_t msk);
200 uint8_t val, uint8_t msk, uint32_t flags);
249 uint8_t msk; /* group mask, used with group API's */ member
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| D | mec_acpi_ec.c | 304 void mec_hal_acpi_ec_status_mask(struct mec_acpi_ec_regs *regs, uint8_t val, uint8_t msk) in mec_hal_acpi_ec_status_mask() argument
311 regs->AEC_STATUS = (regs->AEC_STATUS & ~msk) | (val & msk); in mec_hal_acpi_ec_status_mask()
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| D | mec_uart.c | 505 int mec_hal_uart_intr_mask(struct mec_uart_regs *base, uint8_t msk, uint8_t val) in mec_hal_uart_intr_mask() argument
513 base->IER = (base->IER & ~msk) | val; in mec_hal_uart_intr_mask()
619 uint8_t msk = (MEC_BIT(MEC_UART_LSR_THRE_Pos) | MEC_BIT(MEC_UART_LSR_THSE_Pos)); in mec_hal_uart_is_tx_empty() local
625 if ((base->LSR & msk) == msk) { in mec_hal_uart_is_tx_empty()
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| D | mec_qspi_api.h | 211 int mec_hal_qspi_hw_status_clr(struct mec_qspi_regs *base, uint32_t msk);
213 int mec_hal_qspi_intr_ctrl_msk(struct mec_qspi_regs *base, int enable, uint32_t msk);
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| D | mec_acpi_ec_api.h | 59 void mec_hal_acpi_ec_status_mask(struct mec_acpi_ec_regs *regs, uint8_t val, uint8_t msk);
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| D | mec_adc.c | 112 uint32_t msk = MEC_BIT(MEC_ADC_CTRL_RDONE_Pos) | MEC_BIT(MEC_ADC_CTRL_SDONE_Pos); in mec_hal_adc_activate() local
119 ctrl = regs->CTRL & ~msk; in mec_hal_adc_activate()
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| D | mec_uart_api.h | 160 int mec_hal_uart_intr_mask(struct mec_uart_regs *base, uint8_t msk, uint8_t val);
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