1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * MPFS HAL Embedded Software 7 * 8 */ 9 10 /******************************************************************************* 11 * @file simulation.h 12 * @author Microchip-FPGA Embedded Systems Solutions 13 * @brief SGMII defines 14 */ 15 16 #ifndef MSS_DDR_SGMII_SIMULATION_H_ 17 #define MSS_DDR_SGMII_SIMULATION_H_ 18 19 /* todo: remove this file before customer distribution */ 20 21 /***************************************************************************//** 22 Simulation Test commands 23 */ 24 #define DDR_SIM 0x01 25 #define FLASH_FREEZE_SIM 0x02 26 #define DESIGN_INF_TEST_SIM 0x04 27 #define MMSIO_SIM 0x08 28 #define SGMII_SIM 0x10 29 #define BUS_ERROR_UNIT 0x20 30 #define D_CACHE_TEST 0x40 31 #define EXT_CLK_CHOICE 0x80 32 33 /***************************************************************************//** 34 SGMii Test commands 35 * List from Eugene 36 * 1. Full SGMII test- both channels enabled, external loopback and rx_lock for 37 * both channels. (This test is written) 38 * (Will do a version of this for refclk = 125 mhz also- already supported 39 * in sw) 40 * 2. SGMII test, similar to 1 , except chan1 is off. 41 * 3. TEST with both CHAn0 and CHAn 1 off. This is the default state for sgmii 42 * anyway. The SGMII PLL will not be turned on either. This is our SGMII OFF 43 * MODE test. 44 * 4. RECALIB mode on (RECAL_CNTL-reg_recal_start_en =1). Both chans off. As I 45 * understand this is for DDR IO recalibration. I am not sure what I check 46 * for here. SO I will ask Jeff. 47 * 5. PVT recalibration..as per Srikanths presentation...SCB reg_calib_start =1 48 * and APB calib_start =1 (see my earlier email.) This allows us check status 49 * of calib_start and calib_lock and calib_intrpt to be checked as per 50 * Srikanths presentation. 51 * 52 */ 53 #define SGMII_ALL_ON 0x00 54 #define SGMII_CH1_OFF 0x01 55 #define SGMII_ALL_OFF 0x02 56 #define SGMII_RECALIB 0x03 57 #define SGMII_PVT_MONITOR 0x04 58 #define SGMII_CH0_OFF_CH1_ON 0x05 59 #define SGMII_MAC0_LOOPBACK_TEST 0x06 60 #define SGMII_TRIM_IO 0x07 61 #define SGMII_RECALIB_IO 0x08 62 #define SGMII_MAC1_LOOPBACK_TEST 0x09 63 #define SGMII_ALL_OFF_INC_CLK 0x0A 64 65 66 #ifdef SIMULATION_TEST_FEEDBACK 67 #define SIM_FEEDBACK0(x) (SYSREG->TEMP0 = (uint32_t)x) 68 #define SIM_FEEDBACK1(x) (SYSREG->TEMP1 = (uint32_t)x) 69 #else 70 #define SIM_FEEDBACK0(x) 71 #define SIM_FEEDBACK1(x) 72 #endif 73 74 #endif /* MSS_DDR_SGMII_SIMULATION_H_ */ 75
