1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * MPFS HAL Embedded Software 7 * 8 */ 9 10 /************************************************************************** 11 * 12 * @file mss_sysreg.h 13 * @author Microchip-FPGA Embedded Systems Solutions 14 * @brief Hardware register definitions. 15 16 * 17 */ 18 #ifndef MSS_SYSREG_H 19 #define MSS_SYSREG_H 20 21 #include <stdint.h> 22 23 #ifdef __cplusplus 24 extern "C" { 25 #endif 26 27 /* IO definitions (access restrictions to peripheral registers) */ 28 /** 29 \defgroup CMSIS_glob_defs CMSIS Global Defines 30 <strong>IO Type Qualifiers</strong> are used 31 \li to specify the access to peripheral variables. 32 \li for automatic generation of peripheral register debug information. 33 34 */ 35 #ifndef __I 36 #ifdef __cplusplus 37 #define __I volatile /*!< Defines 'read only' permis 38 sions */ 39 #else 40 #define __I volatile const /*!< Defines 'read only' permis 41 sions */ 42 #endif 43 #endif 44 #ifndef __O 45 #define __O volatile /*!< Defines 'write only' permi 46 ssions */ 47 #endif 48 #ifndef __IO 49 #define __IO volatile /*!< Defines 'read / write' per 50 missions */ 51 #endif 52 /* following defines should be used for structure members */ 53 #ifndef __IM 54 #define __IM volatile const /*! Defines 'read only' structu 55 re member permissions */ 56 #endif 57 #ifndef __OM 58 #define __OM volatile /*! Defines 'write only' struct 59 ure member permissions */ 60 #endif 61 #ifndef __IOM 62 #define __IOM volatile /*! Defines 'read / write' stru 63 cture member permissions */ 64 #endif 65 66 /* Defines all Top Register offsets*/ 67 /* Date of Source Revision File: 12-Jul-18*/ 68 /* PROTOCOL=MSS; BASE=32'h20012000*/ 69 /* Hardware Base Address*/ 70 #define BASE32_ADDR_MSS_SYSREG 0x20002000 71 72 73 /*Register for software use*/ 74 #define TEMP0_OFFSET 0x0 75 /* Scratch register for CPUS*/ 76 #define TEMP0_DATA_OFFSET 0x0 77 #define TEMP0_DATA_MASK (0xFFFFFFFF << 0x0) 78 79 /*Register for software use*/ 80 #define TEMP1_OFFSET 0x4 81 /* Scratch register for CPUS*/ 82 #define TEMP1_DATA_OFFSET 0x0 83 #define TEMP1_DATA_MASK (0xFFFFFFFF << 0x0) 84 85 /*Master clock configuration*/ 86 #define CLOCK_CONFIG_CR_OFFSET 0x8 87 /* "Sets the master synchronous clock divider bits [1:0] CPU clock divi 88 der (Reset=/1 =0)bits [3:2] AXI clock divider (Reset=/ 89 1 =0)bits [5:4] AHB/APB clock divider (Reset=/2 =1)00=/1 01=/2 10=/4 11 90 =/8 (AHB/APB divider may not be set to /1)Note at reset MSS corner clock i 91 s 80MHz therefore divider is set to divide by 1"*/ 92 #define CLOCK_CONFIG_CR_DIVIDER_OFFSET 0x0 93 #define CLOCK_CONFIG_CR_DIVIDER_MASK (0x3F << 0x0) 94 /* When '1' requests G5_control to enable the 1mHz (2MHz) on-chip oscil 95 lator*/ 96 #define CLOCK_CONFIG_CR_ENABLE_1MHZ_OFFSET 0x8 97 #define CLOCK_CONFIG_CR_ENABLE_1MHZ_MASK (0x01 << 0x8) 98 99 /*RTC clock divider*/ 100 #define RTC_CLOCK_CR_OFFSET 0xC 101 /* "Sets the division ratio to create the internal RTC clock from the 102 reference clock. The defaults sets the reference clock to 1MHz assuming the 103 reference clock is 100Mhz.If the reference clock is 125MHz then 125 will c 104 reate a 1MHz clockMax divider value is 4095 and value must be an integer.RT 105 C clock must be less 2X the AXI clock rate."*/ 106 #define RTC_CLOCK_CR_PERIOD_OFFSET 0x0 107 #define RTC_CLOCK_CR_PERIOD_MASK (0xFFF << 0x0) 108 /* RTC Clock enable. When chaning the divider the enable should be trur 109 ned off first the divider changed and the enable turned back on.*/ 110 #define RTC_CLOCK_CR_ENABLE_OFFSET 0x10 111 #define RTC_CLOCK_CR_ENABLE_MASK (0x01 << 0x10) 112 113 /*Fabric Reset mask*/ 114 #define FABRIC_RESET_CR_OFFSET 0x10 115 /* Blocks the fabric Reset input preventing the fabric reseting the MSS 116 */ 117 #define FABRIC_RESET_CR_ENABLE_OFFSET 0x0 118 #define FABRIC_RESET_CR_ENABLE_MASK (0x01 << 0x0) 119 120 /**/ 121 #define BOOT_FAIL_CR_OFFSET 0x14 122 /* Written by firmware to indicate that the boot process failed drives 123 the fab_boot_fail signal to the fabric. Is cleared by the fabric asserting 124 fab_boot_fail_clear*/ 125 #define BOOT_FAIL_CR_BOOT_OFFSET 0x0 126 #define BOOT_FAIL_CR_BOOT_MASK (0x01 << 0x0) 127 128 /*Configuration lock*/ 129 #define CONFIG_LOCK_CR_OFFSET 0x1C 130 /* When written to '1' will cause all RWC registers to lock until a mas 131 ter reset occurs.*/ 132 #define CONFIG_LOCK_CR_LOCK_OFFSET 0x0 133 #define CONFIG_LOCK_CR_LOCK_MASK (0x01 << 0x0) 134 135 /*Indicates which reset caused the last reset. After a reset occurs registe 136 r should be read and then zero written to allow the next reset event to be 137 correctly captured.*/ 138 #define RESET_SR_OFFSET 0x20 139 /* Reset was caused by the SCB periphery reset signal*/ 140 #define RESET_SR_SCB_PERIPH_RESET_OFFSET 0x0 141 #define RESET_SR_SCB_PERIPH_RESET_MASK (0x01 << 0x0) 142 /* Reset was caused by the SCB MSS reset register*/ 143 #define RESET_SR_SCB_MSS_RESET_OFFSET 0x1 144 #define RESET_SR_SCB_MSS_RESET_MASK (0x01 << 0x1) 145 /* Reset was caused by the SCB CPU reset register*/ 146 #define RESET_SR_SCB_CPU_RESET_OFFSET 0x2 147 #define RESET_SR_SCB_CPU_RESET_MASK (0x01 << 0x2) 148 /* Reset was caused by the Risc-V Debugger*/ 149 #define RESET_SR_DEBUGER_RESET_OFFSET 0x3 150 #define RESET_SR_DEBUGER_RESET_MASK (0x01 << 0x3) 151 /* Reset was caused by the fabric*/ 152 #define RESET_SR_FABRIC_RESET_OFFSET 0x4 153 #define RESET_SR_FABRIC_RESET_MASK (0x01 << 0x4) 154 /* Reset was caused by the watchdog*/ 155 #define RESET_SR_WDOG_RESET_OFFSET 0x5 156 #define RESET_SR_WDOG_RESET_MASK (0x01 << 0x5) 157 /* Indicates that fabric asserted the GPIO reset inputs*/ 158 #define RESET_SR_GPIO_RESET_OFFSET 0x6 159 #define RESET_SR_GPIO_RESET_MASK (0x01 << 0x6) 160 /* Indicates that SCB bus reset occurred (which causes warm reset of MS 161 S)*/ 162 #define RESET_SR_SCB_BUS_RESET_OFFSET 0x7 163 #define RESET_SR_SCB_BUS_RESET_MASK (0x01 << 0x7) 164 165 /*Indicates the device status in particular the state of the FPGA fabric an 166 d the MSS IO banks*/ 167 #define DEVICE_STATUS_OFFSET 0x24 168 /* Indicates the status of the core_up input from G5 Control.*/ 169 #define DEVICE_STATUS_CORE_UP_OFFSET 0x0 170 #define DEVICE_STATUS_CORE_UP_MASK (0x01 << 0x0) 171 /* Indicates the status of the lp_state input from G5 Control.*/ 172 #define DEVICE_STATUS_LP_STATE_OFFSET 0x1 173 #define DEVICE_STATUS_LP_STATE_MASK (0x01 << 0x1) 174 /* Indicates the status of the ff_in_progress input from G5 Control.*/ 175 #define DEVICE_STATUS_FF_IN_PROGRESS_OFFSET 0x2 176 #define DEVICE_STATUS_FF_IN_PROGRESS_MASK (0x01 << 0x2) 177 /* Indicates the status of the flash_valid input from G5 Control.*/ 178 #define DEVICE_STATUS_FLASH_VALID_OFFSET 0x3 179 #define DEVICE_STATUS_FLASH_VALID_MASK (0x01 << 0x3) 180 /* Power status of IO bank 2*/ 181 #define DEVICE_STATUS_IO_BANK_B2_STATUS_OFFSET 0x8 182 #define DEVICE_STATUS_IO_BANK_B2_STATUS_MASK (0x01 << 0x8) 183 /* Power status of IO bank 4*/ 184 #define DEVICE_STATUS_IO_BANK_B4_STATUS_OFFSET 0x9 185 #define DEVICE_STATUS_IO_BANK_B4_STATUS_MASK (0x01 << 0x9) 186 /* Power status of IO bank 5*/ 187 #define DEVICE_STATUS_IO_BANK_B5_STATUS_OFFSET 0xA 188 #define DEVICE_STATUS_IO_BANK_B5_STATUS_MASK (0x01 << 0xA) 189 /* Power status of IO bank 6*/ 190 #define DEVICE_STATUS_IO_BANK_B6_STATUS_OFFSET 0xB 191 #define DEVICE_STATUS_IO_BANK_B6_STATUS_MASK (0x01 << 0xB) 192 /* Indicates the status of the io_en input from G5 Control.*/ 193 #define DEVICE_STATUS_IO_EN_OFFSET 0xC 194 #define DEVICE_STATUS_IO_EN_MASK (0x01 << 0xC) 195 196 /*MSS Build Info*/ 197 #define MSS_BUILD_OFFSET 0x28 198 #define MSS_BUILD_REVISION_OFFSET 0x0 199 #define MSS_BUILD_REVISION_MASK (0xFFFFFFFF << 0x0) 200 201 /*U54-1 Fabric interrupt enable*/ 202 #define FAB_INTEN_U54_1_OFFSET 0x40 203 /* Enables the F2H_interrupts[31:0] to interrupt U54_1 directly*/ 204 #define FAB_INTEN_U54_1_ENABLE_OFFSET 0x0 205 #define FAB_INTEN_U54_1_ENABLE_MASK (0xFFFFFFFF << 0x0) 206 207 /*U54-2 Fabric interrupt enable*/ 208 #define FAB_INTEN_U54_2_OFFSET 0x44 209 /* Enables the F2H_interrupts[31:0] to interrupt U54_1 directly*/ 210 #define FAB_INTEN_U54_2_ENABLE_OFFSET 0x0 211 #define FAB_INTEN_U54_2_ENABLE_MASK (0xFFFFFFFF << 0x0) 212 213 /*U54-3 Fabric interrupt enable*/ 214 #define FAB_INTEN_U54_3_OFFSET 0x48 215 /* Enables the F2H_interrupts[31:0] to interrupt U54_1 directly*/ 216 #define FAB_INTEN_U54_3_ENABLE_OFFSET 0x0 217 #define FAB_INTEN_U54_3_ENABLE_MASK (0xFFFFFFFF << 0x0) 218 219 /*U54-4 Fabric interrupt enable*/ 220 #define FAB_INTEN_U54_4_OFFSET 0x4C 221 /* Enables the F2H_interrupts[31:0] to interrupt U54_1 directly*/ 222 #define FAB_INTEN_U54_4_ENABLE_OFFSET 0x0 223 #define FAB_INTEN_U54_4_ENABLE_MASK (0xFFFFFFFF << 0x0) 224 225 /*Allows the Ethernat interrupts to be directly routed to the U54 CPUS.*/ 226 #define FAB_INTEN_MISC_OFFSET 0x50 227 /* Enables the Ethernet MAC0 to interrupt U54_1 directly*/ 228 #define FAB_INTEN_MISC_MAC0_U54_1_OFFSET 0x0 229 #define FAB_INTEN_MISC_MAC0_U54_1_MASK (0x01 << 0x0) 230 /* Enables the Ethernet MAC0 to interrupt U54_1 directly*/ 231 #define FAB_INTEN_MISC_MAC0_U54_2_OFFSET 0x1 232 #define FAB_INTEN_MISC_MAC0_U54_2_MASK (0x01 << 0x1) 233 /* Enables the Ethernet MAC1 to interrupt U54_1 directly*/ 234 #define FAB_INTEN_MISC_MAC1_U54_3_OFFSET 0x2 235 #define FAB_INTEN_MISC_MAC1_U54_3_MASK (0x01 << 0x2) 236 /* Enables the Ethernet MAC1 to interrupt U54_1 directly*/ 237 #define FAB_INTEN_MISC_MAC1_U54_4_OFFSET 0x3 238 #define FAB_INTEN_MISC_MAC1_U54_4_MASK (0x01 << 0x3) 239 240 /*Switches GPIO interrupt from PAD to Fabric GPIO*/ 241 #define GPIO_INTERRUPT_FAB_CR_OFFSET 0x54 242 /* Setting these bits will disable the Pad interrupt and enable the fabric 243 GPIO interrupt for bits 31:0. When the bit is set the Pad interrupt will 244 be ORED into the GPIO0 & GPIO1 non-direct interrupts. When the bit is 245 not set the Fabric interrupt is ORED into the GPIO2 non-direct interrupt. 246 To prevent ORING then the interrupt should not be enabled in the GPIO block 247 */ 248 #define GPIO_INTERRUPT_FAB_CR_SELECT_OFFSET 0x0 249 #define GPIO_INTERRUPT_FAB_CR_SELECT_MASK (0xFFFFFFFF << 0x0) 250 251 /*"AMP Mode peripheral mapping register. When the register bit is '0' the p 252 eripheral is mapped into the 0x2000000 address range using AXI bus 5 from t 253 he Coreplex. When the register bit is '1' the peripheral is mapped into the 254 0x28000000 address range using AXI bus 6 from the Coreplex."*/ 255 #define APBBUS_CR_OFFSET 0x80 256 /* */ 257 #define APBBUS_CR_MMUART0_OFFSET 0x0 258 #define APBBUS_CR_MMUART0_MASK (0x01 << 0x0) 259 /* */ 260 #define APBBUS_CR_MMUART1_OFFSET 0x1 261 #define APBBUS_CR_MMUART1_MASK (0x01 << 0x1) 262 /* */ 263 #define APBBUS_CR_MMUART2_OFFSET 0x2 264 #define APBBUS_CR_MMUART2_MASK (0x01 << 0x2) 265 /* */ 266 #define APBBUS_CR_MMUART3_OFFSET 0x3 267 #define APBBUS_CR_MMUART3_MASK (0x01 << 0x3) 268 /* */ 269 #define APBBUS_CR_MMUART4_OFFSET 0x4 270 #define APBBUS_CR_MMUART4_MASK (0x01 << 0x4) 271 /* */ 272 #define APBBUS_CR_WDOG0_OFFSET 0x5 273 #define APBBUS_CR_WDOG0_MASK (0x01 << 0x5) 274 /* */ 275 #define APBBUS_CR_WDOG1_OFFSET 0x6 276 #define APBBUS_CR_WDOG1_MASK (0x01 << 0x6) 277 /* */ 278 #define APBBUS_CR_WDOG2_OFFSET 0x7 279 #define APBBUS_CR_WDOG2_MASK (0x01 << 0x7) 280 /* */ 281 #define APBBUS_CR_WDOG3_OFFSET 0x8 282 #define APBBUS_CR_WDOG3_MASK (0x01 << 0x8) 283 /* */ 284 #define APBBUS_CR_WDOG4_OFFSET 0x9 285 #define APBBUS_CR_WDOG4_MASK (0x01 << 0x9) 286 /* */ 287 #define APBBUS_CR_SPI0_OFFSET 0xA 288 #define APBBUS_CR_SPI0_MASK (0x01 << 0xA) 289 /* */ 290 #define APBBUS_CR_SPI1_OFFSET 0xB 291 #define APBBUS_CR_SPI1_MASK (0x01 << 0xB) 292 /* */ 293 #define APBBUS_CR_I2C0_OFFSET 0xC 294 #define APBBUS_CR_I2C0_MASK (0x01 << 0xC) 295 /* */ 296 #define APBBUS_CR_I2C1_OFFSET 0xD 297 #define APBBUS_CR_I2C1_MASK (0x01 << 0xD) 298 /* */ 299 #define APBBUS_CR_CAN0_OFFSET 0xE 300 #define APBBUS_CR_CAN0_MASK (0x01 << 0xE) 301 /* */ 302 #define APBBUS_CR_CAN1_OFFSET 0xF 303 #define APBBUS_CR_CAN1_MASK (0x01 << 0xF) 304 /* */ 305 #define APBBUS_CR_GEM0_OFFSET 0x10 306 #define APBBUS_CR_GEM0_MASK (0x01 << 0x10) 307 /* */ 308 #define APBBUS_CR_GEM1_OFFSET 0x11 309 #define APBBUS_CR_GEM1_MASK (0x01 << 0x11) 310 /* */ 311 #define APBBUS_CR_TIMER_OFFSET 0x12 312 #define APBBUS_CR_TIMER_MASK (0x01 << 0x12) 313 /* */ 314 #define APBBUS_CR_GPIO0_OFFSET 0x13 315 #define APBBUS_CR_GPIO0_MASK (0x01 << 0x13) 316 /* */ 317 #define APBBUS_CR_GPIO1_OFFSET 0x14 318 #define APBBUS_CR_GPIO1_MASK (0x01 << 0x14) 319 /* */ 320 #define APBBUS_CR_GPIO2_OFFSET 0x15 321 #define APBBUS_CR_GPIO2_MASK (0x01 << 0x15) 322 /* */ 323 #define APBBUS_CR_RTC_OFFSET 0x16 324 #define APBBUS_CR_RTC_MASK (0x01 << 0x16) 325 /* */ 326 #define APBBUS_CR_H2FINT_OFFSET 0x17 327 #define APBBUS_CR_H2FINT_MASK (0x01 << 0x17) 328 329 /*"Enables the clock to the MSS peripheral. By turning clocks off dynamic power 330 can be saved. When the clock is off the peripheral should not be accessed 331 the access may be ignored return unspecified data or result in bus response 332 error."*/ 333 #define SUBBLK_CLOCK_CR_OFFSET 0x84 334 /* */ 335 #define SUBBLK_CLOCK_CR_ENVM_OFFSET 0x0 336 #define SUBBLK_CLOCK_CR_ENVM_MASK (0x01 << 0x0) 337 /* */ 338 #define SUBBLK_CLOCK_CR_MAC0_OFFSET 0x1 339 #define SUBBLK_CLOCK_CR_MAC0_MASK (0x01 << 0x1) 340 /* */ 341 #define SUBBLK_CLOCK_CR_MAC1_OFFSET 0x2 342 #define SUBBLK_CLOCK_CR_MAC1_MASK (0x01 << 0x2) 343 /* */ 344 #define SUBBLK_CLOCK_CR_MMC_OFFSET 0x3 345 #define SUBBLK_CLOCK_CR_MMC_MASK (0x01 << 0x3) 346 /* */ 347 #define SUBBLK_CLOCK_CR_TIMER_OFFSET 0x4 348 #define SUBBLK_CLOCK_CR_TIMER_MASK (0x01 << 0x4) 349 /* */ 350 #define SUBBLK_CLOCK_CR_MMUART0_OFFSET 0x5 351 #define SUBBLK_CLOCK_CR_MMUART0_MASK (0x01 << 0x5) 352 /* */ 353 #define SUBBLK_CLOCK_CR_MMUART1_OFFSET 0x6 354 #define SUBBLK_CLOCK_CR_MMUART1_MASK (0x01 << 0x6) 355 /* */ 356 #define SUBBLK_CLOCK_CR_MMUART2_OFFSET 0x7 357 #define SUBBLK_CLOCK_CR_MMUART2_MASK (0x01 << 0x7) 358 /* */ 359 #define SUBBLK_CLOCK_CR_MMUART3_OFFSET 0x8 360 #define SUBBLK_CLOCK_CR_MMUART3_MASK (0x01 << 0x8) 361 /* */ 362 #define SUBBLK_CLOCK_CR_MMUART4_OFFSET 0x9 363 #define SUBBLK_CLOCK_CR_MMUART4_MASK (0x01 << 0x9) 364 /* */ 365 #define SUBBLK_CLOCK_CR_SPI0_OFFSET 0xA 366 #define SUBBLK_CLOCK_CR_SPI0_MASK (0x01 << 0xA) 367 /* */ 368 #define SUBBLK_CLOCK_CR_SPI1_OFFSET 0xB 369 #define SUBBLK_CLOCK_CR_SPI1_MASK (0x01 << 0xB) 370 /* */ 371 #define SUBBLK_CLOCK_CR_I2C0_OFFSET 0xC 372 #define SUBBLK_CLOCK_CR_I2C0_MASK (0x01 << 0xC) 373 /* */ 374 #define SUBBLK_CLOCK_CR_I2C1_OFFSET 0xD 375 #define SUBBLK_CLOCK_CR_I2C1_MASK (0x01 << 0xD) 376 /* */ 377 #define SUBBLK_CLOCK_CR_CAN0_OFFSET 0xE 378 #define SUBBLK_CLOCK_CR_CAN0_MASK (0x01 << 0xE) 379 /* */ 380 #define SUBBLK_CLOCK_CR_CAN1_OFFSET 0xF 381 #define SUBBLK_CLOCK_CR_CAN1_MASK (0x01 << 0xF) 382 /* */ 383 #define SUBBLK_CLOCK_CR_USB_OFFSET 0x10 384 #define SUBBLK_CLOCK_CR_USB_MASK (0x01 << 0x10) 385 /* */ 386 #define SUBBLK_CLOCK_CR_RSVD_OFFSET 0x11 387 #define SUBBLK_CLOCK_CR_RSVD_MASK (0x01 << 0x11) 388 /* */ 389 #define SUBBLK_CLOCK_CR_RTC_OFFSET 0x12 390 #define SUBBLK_CLOCK_CR_RTC_MASK (0x01 << 0x12) 391 /* */ 392 #define SUBBLK_CLOCK_CR_QSPI_OFFSET 0x13 393 #define SUBBLK_CLOCK_CR_QSPI_MASK (0x01 << 0x13) 394 /* */ 395 #define SUBBLK_CLOCK_CR_GPIO0_OFFSET 0x14 396 #define SUBBLK_CLOCK_CR_GPIO0_MASK (0x01 << 0x14) 397 /* */ 398 #define SUBBLK_CLOCK_CR_GPIO1_OFFSET 0x15 399 #define SUBBLK_CLOCK_CR_GPIO1_MASK (0x01 << 0x15) 400 /* */ 401 #define SUBBLK_CLOCK_CR_GPIO2_OFFSET 0x16 402 #define SUBBLK_CLOCK_CR_GPIO2_MASK (0x01 << 0x16) 403 /* */ 404 #define SUBBLK_CLOCK_CR_DDRC_OFFSET 0x17 405 #define SUBBLK_CLOCK_CR_DDRC_MASK (0x01 << 0x17) 406 /* */ 407 #define SUBBLK_CLOCK_CR_FIC0_OFFSET 0x18 408 #define SUBBLK_CLOCK_CR_FIC0_MASK (0x01 << 0x18) 409 /* */ 410 #define SUBBLK_CLOCK_CR_FIC1_OFFSET 0x19 411 #define SUBBLK_CLOCK_CR_FIC1_MASK (0x01 << 0x19) 412 /* */ 413 #define SUBBLK_CLOCK_CR_FIC2_OFFSET 0x1A 414 #define SUBBLK_CLOCK_CR_FIC2_MASK (0x01 << 0x1A) 415 /* */ 416 #define SUBBLK_CLOCK_CR_FIC3_OFFSET 0x1B 417 #define SUBBLK_CLOCK_CR_FIC3_MASK (0x01 << 0x1B) 418 /* */ 419 #define SUBBLK_CLOCK_CR_ATHENA_OFFSET 0x1C 420 #define SUBBLK_CLOCK_CR_ATHENA_MASK (0x01 << 0x1C) 421 /* */ 422 #define SUBBLK_CLOCK_CR_CFM_OFFSET 0x1D 423 #define SUBBLK_CLOCK_CR_CFM_MASK (0x01 << 0x1D) 424 425 /*"Holds the MSS peripherals in reset. When in reset the peripheral should 426 not be accessed the acess may be ignored return unspecified data or result 427 in bus response error."*/ 428 #define SOFT_RESET_CR_OFFSET 0x88 429 /* */ 430 #define SOFT_RESET_CR_ENVM_OFFSET 0x0 431 #define SOFT_RESET_CR_ENVM_MASK (0x01 << 0x0) 432 /* */ 433 #define SOFT_RESET_CR_MAC0_OFFSET 0x1 434 #define SOFT_RESET_CR_MAC0_MASK (0x01 << 0x1) 435 /* */ 436 #define SOFT_RESET_CR_MAC1_OFFSET 0x2 437 #define SOFT_RESET_CR_MAC1_MASK (0x01 << 0x2) 438 /* */ 439 #define SOFT_RESET_CR_MMC_OFFSET 0x3 440 #define SOFT_RESET_CR_MMC_MASK (0x01 << 0x3) 441 /* */ 442 #define SOFT_RESET_CR_TIMER_OFFSET 0x4 443 #define SOFT_RESET_CR_TIMER_MASK (0x01 << 0x4) 444 /* */ 445 #define SOFT_RESET_CR_MMUART0_OFFSET 0x5 446 #define SOFT_RESET_CR_MMUART0_MASK (0x01 << 0x5) 447 /* */ 448 #define SOFT_RESET_CR_MMUART1_OFFSET 0x6 449 #define SOFT_RESET_CR_MMUART1_MASK (0x01 << 0x6) 450 /* */ 451 #define SOFT_RESET_CR_MMUART2_OFFSET 0x7 452 #define SOFT_RESET_CR_MMUART2_MASK (0x01 << 0x7) 453 /* */ 454 #define SOFT_RESET_CR_MMUART3_OFFSET 0x8 455 #define SOFT_RESET_CR_MMUART3_MASK (0x01 << 0x8) 456 /* */ 457 #define SOFT_RESET_CR_MMUART4_OFFSET 0x9 458 #define SOFT_RESET_CR_MMUART4_MASK (0x01 << 0x9) 459 /* */ 460 #define SOFT_RESET_CR_SPI0_OFFSET 0xA 461 #define SOFT_RESET_CR_SPI0_MASK (0x01 << 0xA) 462 /* */ 463 #define SOFT_RESET_CR_SPI1_OFFSET 0xB 464 #define SOFT_RESET_CR_SPI1_MASK (0x01 << 0xB) 465 /* */ 466 #define SOFT_RESET_CR_I2C0_OFFSET 0xC 467 #define SOFT_RESET_CR_I2C0_MASK (0x01 << 0xC) 468 /* */ 469 #define SOFT_RESET_CR_I2C1_OFFSET 0xD 470 #define SOFT_RESET_CR_I2C1_MASK (0x01 << 0xD) 471 /* */ 472 #define SOFT_RESET_CR_CAN0_OFFSET 0xE 473 #define SOFT_RESET_CR_CAN0_MASK (0x01 << 0xE) 474 /* */ 475 #define SOFT_RESET_CR_CAN1_OFFSET 0xF 476 #define SOFT_RESET_CR_CAN1_MASK (0x01 << 0xF) 477 /* */ 478 #define SOFT_RESET_CR_USB_OFFSET 0x10 479 #define SOFT_RESET_CR_USB_MASK (0x01 << 0x10) 480 /* */ 481 #define SOFT_RESET_CR_FPGA_OFFSET 0x11 482 #define SOFT_RESET_CR_FPGA_MASK (0x01 << 0x11) 483 /* */ 484 #define SOFT_RESET_CR_RTC_OFFSET 0x12 485 #define SOFT_RESET_CR_RTC_MASK (0x01 << 0x12) 486 /* */ 487 #define SOFT_RESET_CR_QSPI_OFFSET 0x13 488 #define SOFT_RESET_CR_QSPI_MASK (0x01 << 0x13) 489 /* */ 490 #define SOFT_RESET_CR_GPIO0_OFFSET 0x14 491 #define SOFT_RESET_CR_GPIO0_MASK (0x01 << 0x14) 492 /* */ 493 #define SOFT_RESET_CR_GPIO1_OFFSET 0x15 494 #define SOFT_RESET_CR_GPIO1_MASK (0x01 << 0x15) 495 /* */ 496 #define SOFT_RESET_CR_GPIO2_OFFSET 0x16 497 #define SOFT_RESET_CR_GPIO2_MASK (0x01 << 0x16) 498 /* */ 499 #define SOFT_RESET_CR_DDRC_OFFSET 0x17 500 #define SOFT_RESET_CR_DDRC_MASK (0x01 << 0x17) 501 /* */ 502 #define SOFT_RESET_CR_FIC0_OFFSET 0x18 503 #define SOFT_RESET_CR_FIC0_MASK (0x01 << 0x18) 504 /* */ 505 #define SOFT_RESET_CR_FIC1_OFFSET 0x19 506 #define SOFT_RESET_CR_FIC1_MASK (0x01 << 0x19) 507 /* */ 508 #define SOFT_RESET_CR_FIC2_OFFSET 0x1A 509 #define SOFT_RESET_CR_FIC2_MASK (0x01 << 0x1A) 510 /* */ 511 #define SOFT_RESET_CR_FIC3_OFFSET 0x1B 512 #define SOFT_RESET_CR_FIC3_MASK (0x01 << 0x1B) 513 /* */ 514 #define SOFT_RESET_CR_ATHENA_OFFSET 0x1C 515 #define SOFT_RESET_CR_ATHENA_MASK (0x01 << 0x1C) 516 /* */ 517 #define SOFT_RESET_CR_CFM_OFFSET 0x1D 518 #define SOFT_RESET_CR_CFM_MASK (0x01 << 0x1D) 519 /* Reset to Corner SGMII block*/ 520 #define SOFT_RESET_CR_SGMII_OFFSET 0x1E 521 #define SOFT_RESET_CR_SGMII_MASK (0x01 << 0x1E) 522 523 /*Configures how many outstanding transfers the AXI-AHB bridges in front of 524 f the USB and Crypto blocks should allow. (See Synopsys AXI-AHB bridge docu 525 mentation)*/ 526 #define AHBAXI_CR_OFFSET 0x8C 527 /* Number of outstanding write transactions to USB block*/ 528 #define AHBAXI_CR_USB_WBCNT_OFFSET 0x0 529 #define AHBAXI_CR_USB_WBCNT_MASK (0x0F << 0x0) 530 /* Number of outstanding read transactions to USB block*/ 531 #define AHBAXI_CR_USB_RBCNT_OFFSET 0x4 532 #define AHBAXI_CR_USB_RBCNT_MASK (0x0F << 0x4) 533 /* Number of outstanding write transactions to Athena block*/ 534 #define AHBAXI_CR_ATHENA_WBCNT_OFFSET 0x8 535 #define AHBAXI_CR_ATHENA_WBCNT_MASK (0x0F << 0x8) 536 /* Number of outstanding read transactions to Athena block*/ 537 #define AHBAXI_CR_ATHENA_RBCNT_OFFSET 0xC 538 #define AHBAXI_CR_ATHENA_RBCNT_MASK (0x0F << 0xC) 539 540 /*Configures the two AHB-APB bridges on S5 and S6*/ 541 #define AHBAPB_CR_OFFSET 0x90 542 /* Enables posted mode on the AHB-APB bridge when set the AHB write cyc 543 le will complete before the APB write cycle completes.*/ 544 #define AHBAPB_CR_APB0_POSTED_OFFSET 0x0 545 #define AHBAPB_CR_APB0_POSTED_MASK (0x01 << 0x0) 546 /* Enables posted mode on the AHB-APB bridge when set the AHB write cyc 547 le will complete before the APB write cycle completes.*/ 548 #define AHBAPB_CR_APB1_POSTED_OFFSET 0x1 549 #define AHBAPB_CR_APB1_POSTED_MASK (0x01 << 0x1) 550 551 /*MSS Corner APB interface controls*/ 552 #define DFIAPB_CR_OFFSET 0x98 553 /* Turns on the APB clock to the MSS Corner is off at reset. Once corne 554 r blocks is configured the firmware may turn off the clock but periodically 555 should turn back on to allow refresh of TMR registers inside the corner bl 556 ock. */ 557 #define DFIAPB_CR_CLOCKON_OFFSET 0x0 558 #define DFIAPB_CR_CLOCKON_MASK (0x01 << 0x0) 559 /* Asserts the APB reset to the MSS corner is asserted at MSS reset.*/ 560 #define DFIAPB_CR_RESET_OFFSET 0x1 561 #define DFIAPB_CR_RESET_MASK (0x01 << 0x1) 562 563 /*GPIO Blocks reset control*/ 564 #define GPIO_CR_OFFSET 0x9C 565 /* "This signal selects whether the associated byte is reset by soft re 566 set or the the MSS_GPIO_RESET_N signal from the FPGA fabric. The allowed va 567 lues are:* 0: Selects MSS_GPIO_RESET_N signal from the FPGA fabric.* 1 568 : Selects the GPIO to be reset by the GPIO block soft reset signal .Bit 0 569 controls GPIO0 [7:0] and bit 1 GPIO[15:8]The master MSS reset will also r 570 eset the GPIO register if not configured to use fabric reset."*/ 571 #define GPIO_CR_GPIO0_SOFT_RESET_SELECT_OFFSET 0x0 572 #define GPIO_CR_GPIO0_SOFT_RESET_SELECT_MASK (0x03 << 0x0) 573 /* "Sets the reset value off the GPIO0 per byteBit 0 controls GPIO0 [7: 574 0] and bit 1 GPIO[15:8]"*/ 575 #define GPIO_CR_GPIO0_DEFAULT_OFFSET 0x4 576 #define GPIO_CR_GPIO0_DEFAULT_MASK (0x03 << 0x4) 577 /* "This signal selects whether the associated byte is reset by soft re 578 set or the the MSS_GPIO_RESET_N signal from the FPGA fabric. The allowed va 579 lues are:* 0: Selects MSS_GPIO_RESET_N signal from the FPGA fabric.* 1 580 : Selects the GPIO to be reset by the GPIO block soft reset signal .Bit 0 581 controls GPIO0 [7:0] bit 1 GPIO[15:8] and bit 2 GPIO[23:16]The master MSS 582 reset will also reset the GPIO register if not configured to use fabric res 583 et."*/ 584 #define GPIO_CR_GPIO1_SOFT_RESET_SELECT_OFFSET 0x8 585 #define GPIO_CR_GPIO1_SOFT_RESET_SELECT_MASK (0x07 << 0x8) 586 /* "Sets the reset value off the GPIO0 per byteBit 0 controls GPIO0 [7: 587 0] bit 1 GPIO[15:8] and bit 2 GPIO[23:16]"*/ 588 #define GPIO_CR_GPIO1_DEFAULT_OFFSET 0xC 589 #define GPIO_CR_GPIO1_DEFAULT_MASK (0x07 << 0xC) 590 /* "This signal selects whether the associated byte is reset by soft re 591 set or the the MSS_GPIO_RESET_N signal from the FPGA fabric. The allowed va 592 lues are:* 0: Selects MSS_GPIO_RESET_N signal from the FPGA fabric.* 1 593 : Selects the GPIO to be reset by the GPIO block soft reset signal .Bit 0 594 controls GPIO0 [7:0] bit 1 GPIO[15:8] and bit 1 GPIO[23:16] and bit 3 GPIO 595 [31:24]The master MSS reset will also reset the GPIO register if not config 596 ured to use fabric reset."*/ 597 #define GPIO_CR_GPIO2_SOFT_RESET_SELECT_OFFSET 0x10 598 #define GPIO_CR_GPIO2_SOFT_RESET_SELECT_MASK (0x0F << 0x10) 599 /* "Sets the reset value off the GPIO0 per byteBit 0 controls GPIO0 [7: 600 0] bit 1 GPIO[15:8] and bit 1 GPIO[23:16] and bit 3 GPIO[31:24]"*/ 601 #define GPIO_CR_GPIO2_DEFAULT_OFFSET 0x14 602 #define GPIO_CR_GPIO2_DEFAULT_MASK (0x0F << 0x14) 603 604 /*MAC0 configuration register*/ 605 #define MAC0_CR_OFFSET 0xA4 606 /* Current speed mode on the MAC*/ 607 #define MAC0_CR_SPEED_MODE_OFFSET 0x0 608 #define MAC0_CR_SPEED_MODE_MASK (0x0F << 0x0) 609 610 /*MAC1 configuration register*/ 611 #define MAC1_CR_OFFSET 0xA8 612 /* Current speed mode on the MAC*/ 613 #define MAC1_CR_SPEED_MODE_OFFSET 0x0 614 #define MAC1_CR_SPEED_MODE_MASK (0x0F << 0x0) 615 616 /*USB Configuration register*/ 617 #define USB_CR_OFFSET 0xAC 618 /* "Configures USB for Single-Data Rate(SDR) mode or Double-Data Rate(D 619 DR) mode. 0 - SDR Mode is selected1 - DDR Mode is selected (Not supported i 620 n G5 or G5)"*/ 621 #define USB_CR_DDR_SELECT_OFFSET 0x0 622 #define USB_CR_DDR_SELECT_MASK (0x01 << 0x0) 623 /* When '1' will stops the clock to the USB core when the core asserts 624 its POWERDOWN output. For G4 compatibility this bit defaults to 0.*/ 625 #define USB_CR_POWERDOWN_ENABLE_OFFSET 0x1 626 #define USB_CR_POWERDOWN_ENABLE_MASK (0x01 << 0x1) 627 /* Indicates that the USB CLK may be stopped to save power. Derived fro 628 m combination of signals from CLK & XCLK flip-flops AVALID VBUSVALID and LI 629 NESTATE. When asserted the USB clock into the core is stopped.*/ 630 #define USB_CR_POWERDOWN_OFFSET 0x2 631 #define USB_CR_POWERDOWN_MASK (0x01 << 0x2) 632 /* Set when entry is made into CarKit mode and cleared on exit from Car 633 Kit mode.*/ 634 #define USB_CR_LPI_CARKIT_EN_OFFSET 0x3 635 #define USB_CR_LPI_CARKIT_EN_MASK (0x01 << 0x3) 636 637 /*Crypto Mesh control and status register*/ 638 #define MESH_CR_OFFSET 0xB0 639 /* Writing a 1 will start the Mesh System*/ 640 #define MESH_CR_START_OFFSET 0x0 641 #define MESH_CR_START_MASK (0x01 << 0x0) 642 /* "Sets the amount of time that the mesh is held active for actual hol 643 d time includes up to 256 us of random variation.Minimum Time = 1 + 256 * v 644 alue usMaximum Time = 1 + 256 * (1+value) usValue must be greater than 645 0"*/ 646 #define MESH_CR_HOLD_OFFSET 0x1 647 #define MESH_CR_HOLD_MASK (0xFFF << 0x1) 648 /* When set will inject an error in the mesh*/ 649 #define MESH_CR_INJECT_ERROR_OFFSET 0x10 650 #define MESH_CR_INJECT_ERROR_MASK (0x01 << 0x10) 651 /* Indicates that Mesh detected an error. Cleared by writing a '1'*/ 652 #define MESH_CR_MESH_ERROR_OFFSET 0x18 653 #define MESH_CR_MESH_ERROR_MASK (0x01 << 0x18) 654 /* Indicates that the Mesh is functioning correctly. Will be set approx 655 imately 520 clock cycles after mesh started and stay set as long as the me 656 sh is not detecting any errors.*/ 657 #define MESH_CR_OKAY_OFFSET 0x19 658 #define MESH_CR_OKAY_MASK (0x01 << 0x19) 659 660 /*Crypto mesh seed and update rate*/ 661 #define MESH_SEED_CR_OFFSET 0xB4 662 /* Sets the mesh seed value any value may be used zero should be avoide 663 d*/ 664 #define MESH_SEED_CR_SEED_OFFSET 0x0 665 #define MESH_SEED_CR_SEED_MASK (0x7FFFFF << 0x0) 666 /* Sets the rate that the mesh value is changed. Rate = AHBCLK/(clkrate 667 +1). Rate must be less than 1MHz setting slower will reduce power consumpti 668 on.*/ 669 #define MESH_SEED_CR_CLKRATE_OFFSET 0x18 670 #define MESH_SEED_CR_CLKRATE_MASK (0xFF << 0x18) 671 672 /*ENVM AHB Controller setup*/ 673 #define ENVM_CR_OFFSET 0xB8 674 /* "Sets the number of AHB cycles used to generate the PNVM clockClock 675 period = (Value+1) * (1000/AHBFREQMHZ) Value must be 1 to 63 (0 676 defaults to 15)e.g.11 will generate a 40ns period 25MHz clock if the AHB 677 clock is 250MHz15 will generate a 40ns period 25MHz clock if the AHB cloc 678 k is 400MHz"*/ 679 #define ENVM_CR_CLOCK_PERIOD_OFFSET 0x0 680 #define ENVM_CR_CLOCK_PERIOD_MASK (0x3F << 0x0) 681 /* Indicates the eNVM is running at the configured divider rate. */ 682 #define ENVM_CR_CLOCK_OKAY_OFFSET 0x6 683 #define ENVM_CR_CLOCK_OKAY_MASK (0x01 << 0x6) 684 /* When '1' the PNVM clock will be always generated and not stopped bet 685 ween access cycles. Setting this will increase access latency but mean that 686 the PNVM clock operates at a stable rate.*/ 687 #define ENVM_CR_CLOCK_CONTINUOUS_OFFSET 0x8 688 #define ENVM_CR_CLOCK_CONTINUOUS_MASK (0x01 << 0x8) 689 /* When set suppresses clock edge between C-Bus access cycles so that t 690 hey appear as consecutive access cycles.*/ 691 #define ENVM_CR_CLOCK_SUPPRESS_OFFSET 0x9 692 #define ENVM_CR_CLOCK_SUPPRESS_MASK (0x01 << 0x9) 693 /* "Enables ""read-ahead"" on the ENVM controller. The controller will 694 automatically read the next PNVM location as soon as possible ahead of the 695 AHB request. This will improve read performance when incrementing though 696 memory as the NVM reads and AHB cycles are pipelined. When set non incrementing 697 accesses will take longer as the controller may be in the process of reading 698 the next address and the PNVM cycle needs to complete prior to starting 699 the required read"*/ 700 #define ENVM_CR_READAHEAD_OFFSET 0x10 701 #define ENVM_CR_READAHEAD_MASK (0x01 << 0x10) 702 /* When '1' the controller will initiate separate ENVM reads for all reads. 703 No buffering or speculative operations will be carried out. When performing 704 word reads incrementing through PNVM each location will be read twice 705 (intended for test use)*/ 706 #define ENVM_CR_SLOWREAD_OFFSET 0x11 707 #define ENVM_CR_SLOWREAD_MASK (0x01 << 0x11) 708 /* Enable the ENVM interrupt*/ 709 #define ENVM_CR_INTERRUPT_ENABLE_OFFSET 0x12 710 #define ENVM_CR_INTERRUPT_ENABLE_MASK (0x01 << 0x12) 711 /* "Sets the duration of the timer used to detect a non response of slow 712 response from the PNVM on C and R bus accesses.Timer Duration = Value * 713 (1000/AHBFREQMHZ) 0x00: Timer disabled. If the timer expires the AHB cycle 714 is terminates using the HRESP protocol"*/ 715 #define ENVM_CR_TIMER_OFFSET 0x18 716 #define ENVM_CR_TIMER_MASK (0xFF << 0x18) 717 718 /*Reserved*/ 719 #define RESERVED_BC_OFFSET 0xBC 720 /* Reserved register address*/ 721 #define RESERVED_BC_RESERVED_OFFSET 0x0 722 #define RESERVED_BC_RESERVED_MASK (0x01 << 0x0) 723 724 /*QOS Athena USB & MMC Configuration*/ 725 #define QOS_PERIPHERAL_CR_OFFSET 0xC0 726 /* Sets the QOS value from the specified device into the switch*/ 727 #define QOS_PERIPHERAL_CR_ATHENA_READ_OFFSET 0x0 728 #define QOS_PERIPHERAL_CR_ATHENA_READ_MASK (0x0F << 0x0) 729 /* Sets the QOS value from the specified device into the switch*/ 730 #define QOS_PERIPHERAL_CR_ATHENA_WRITE_OFFSET 0x4 731 #define QOS_PERIPHERAL_CR_ATHENA_WRITE_MASK (0x0F << 0x4) 732 /* Sets the QOS value from the specified device into the switch*/ 733 #define QOS_PERIPHERAL_CR_USB_READ_OFFSET 0x8 734 #define QOS_PERIPHERAL_CR_USB_READ_MASK (0x0F << 0x8) 735 /* Sets the QOS value from the specified device into the switch*/ 736 #define QOS_PERIPHERAL_CR_USB_WRITE_OFFSET 0xC 737 #define QOS_PERIPHERAL_CR_USB_WRITE_MASK (0x0F << 0xC) 738 /* Sets the QOS value from the specified device into the switch*/ 739 #define QOS_PERIPHERAL_CR_MMC_READ_OFFSET 0x10 740 #define QOS_PERIPHERAL_CR_MMC_READ_MASK (0x0F << 0x10) 741 /* Sets the QOS value from the specified device into the switch*/ 742 #define QOS_PERIPHERAL_CR_MMC_WRITE_OFFSET 0x14 743 #define QOS_PERIPHERAL_CR_MMC_WRITE_MASK (0x0F << 0x14) 744 /* Sets the QOS value from the specified device into the switch*/ 745 #define QOS_PERIPHERAL_CR_TRACE_READ_OFFSET 0x18 746 #define QOS_PERIPHERAL_CR_TRACE_READ_MASK (0x0F << 0x18) 747 /* Sets the QOS value from the specified device into the switch*/ 748 #define QOS_PERIPHERAL_CR_TRACE_WRITE_OFFSET 0x1C 749 #define QOS_PERIPHERAL_CR_TRACE_WRITE_MASK (0x0F << 0x1C) 750 751 /*QOS Configuration Coreplex*/ 752 #define QOS_CPLEXIO_CR_OFFSET 0xC4 753 /* Sets the QOS value from the specified device into the switch*/ 754 #define QOS_CPLEXIO_CR_DEVICE0_READ_OFFSET 0x0 755 #define QOS_CPLEXIO_CR_DEVICE0_READ_MASK (0x0F << 0x0) 756 /* Sets the QOS value from the specified device into the switch*/ 757 #define QOS_CPLEXIO_CR_DEVICE0_WRITE_OFFSET 0x4 758 #define QOS_CPLEXIO_CR_DEVICE0_WRITE_MASK (0x0F << 0x4) 759 /* Sets the QOS value from the specified device into the switch*/ 760 #define QOS_CPLEXIO_CR_DEVICE1_READ_OFFSET 0x8 761 #define QOS_CPLEXIO_CR_DEVICE1_READ_MASK (0x0F << 0x8) 762 /* Sets the QOS value from the specified device into the switch*/ 763 #define QOS_CPLEXIO_CR_DEVICE1_WRITE_OFFSET 0xC 764 #define QOS_CPLEXIO_CR_DEVICE1_WRITE_MASK (0x0F << 0xC) 765 /* Sets the QOS value from the specified device into the switch*/ 766 #define QOS_CPLEXIO_CR_FABRIC0_READ_OFFSET 0x10 767 #define QOS_CPLEXIO_CR_FABRIC0_READ_MASK (0x0F << 0x10) 768 /* Sets the QOS value from the specified device into the switch*/ 769 #define QOS_CPLEXIO_CR_FABRIC0_WRITE_OFFSET 0x14 770 #define QOS_CPLEXIO_CR_FABRIC0_WRITE_MASK (0x0F << 0x14) 771 /* Sets the QOS value from the specified device into the switch*/ 772 #define QOS_CPLEXIO_CR_FABRIC1_READ_OFFSET 0x18 773 #define QOS_CPLEXIO_CR_FABRIC1_READ_MASK (0x0F << 0x18) 774 /* Sets the QOS value from the specified device into the switch*/ 775 #define QOS_CPLEXIO_CR_FABRIC1_WRITE_OFFSET 0x1C 776 #define QOS_CPLEXIO_CR_FABRIC1_WRITE_MASK (0x0F << 0x1C) 777 778 /*QOS configuration DDRC*/ 779 #define QOS_CPLEXDDR_CR_OFFSET 0xC8 780 /* Sets the QOS value from the specified device into the switch*/ 781 #define QOS_CPLEXDDR_CR_CACHE_READ_OFFSET 0x0 782 #define QOS_CPLEXDDR_CR_CACHE_READ_MASK (0x0F << 0x0) 783 /* Sets the QOS value from the specified device into the switch*/ 784 #define QOS_CPLEXDDR_CR_CACHE_WRITE_OFFSET 0x4 785 #define QOS_CPLEXDDR_CR_CACHE_WRITE_MASK (0x0F << 0x4) 786 /* Sets the QOS value from the specified device into the switch*/ 787 #define QOS_CPLEXDDR_CR_NCACHE_READ_OFFSET 0x8 788 #define QOS_CPLEXDDR_CR_NCACHE_READ_MASK (0x0F << 0x8) 789 /* Sets the QOS value from the specified device into the switch*/ 790 #define QOS_CPLEXDDR_CR_NCACHE_WRITE_OFFSET 0xC 791 #define QOS_CPLEXDDR_CR_NCACHE_WRITE_MASK (0x0F << 0xC) 792 793 /*Indicates that a master caused a MPU violation. Interrupts via maintenanc 794 e interrupt.*/ 795 #define MPU_VIOLATION_SR_OFFSET 0xF0 796 /* Bit is set on violation. Cleared by writing '1'*/ 797 #define MPU_VIOLATION_SR_FIC0_OFFSET 0x0 798 #define MPU_VIOLATION_SR_FIC0_MASK (0x01 << 0x0) 799 /* Bit is set on violation. Cleared by writing '1'*/ 800 #define MPU_VIOLATION_SR_FIC1_OFFSET 0x1 801 #define MPU_VIOLATION_SR_FIC1_MASK (0x01 << 0x1) 802 /* Bit is set on violation. Cleared by writing '1'*/ 803 #define MPU_VIOLATION_SR_FIC2_OFFSET 0x2 804 #define MPU_VIOLATION_SR_FIC2_MASK (0x01 << 0x2) 805 /* Bit is set on violation. Cleared by writing '1'*/ 806 #define MPU_VIOLATION_SR_ATHENA_OFFSET 0x3 807 #define MPU_VIOLATION_SR_ATHENA_MASK (0x01 << 0x3) 808 /* Bit is set on violation. Cleared by writing '1'*/ 809 #define MPU_VIOLATION_SR_GEM0_OFFSET 0x4 810 #define MPU_VIOLATION_SR_GEM0_MASK (0x01 << 0x4) 811 /* Bit is set on violation. Cleared by writing '1'*/ 812 #define MPU_VIOLATION_SR_GEM1_OFFSET 0x5 813 #define MPU_VIOLATION_SR_GEM1_MASK (0x01 << 0x5) 814 /* Bit is set on violation. Cleared by writing '1'*/ 815 #define MPU_VIOLATION_SR_USB_OFFSET 0x6 816 #define MPU_VIOLATION_SR_USB_MASK (0x01 << 0x6) 817 /* Bit is set on violation. Cleared by writing '1'*/ 818 #define MPU_VIOLATION_SR_MMC_OFFSET 0x7 819 #define MPU_VIOLATION_SR_MMC_MASK (0x01 << 0x7) 820 /* Bit is set on violation. Cleared by writing '1'*/ 821 #define MPU_VIOLATION_SR_SCB_OFFSET 0x8 822 #define MPU_VIOLATION_SR_SCB_MASK (0x01 << 0x8) 823 /* Bit is set on violation. Cleared by writing '1'*/ 824 #define MPU_VIOLATION_SR_TRACE_OFFSET 0x9 825 #define MPU_VIOLATION_SR_TRACE_MASK (0x01 << 0x9) 826 827 /*Enables interrupts on MPU violations*/ 828 #define MPU_VIOLATION_INTEN_CR_OFFSET 0xF4 829 /* Enables the interrupt*/ 830 #define MPU_VIOLATION_INTEN_CR_FIC0_OFFSET 0x0 831 #define MPU_VIOLATION_INTEN_CR_FIC0_MASK (0x01 << 0x0) 832 /* Enables the interrupt*/ 833 #define MPU_VIOLATION_INTEN_CR_FIC1_OFFSET 0x1 834 #define MPU_VIOLATION_INTEN_CR_FIC1_MASK (0x01 << 0x1) 835 /* Enables the interrupt*/ 836 #define MPU_VIOLATION_INTEN_CR_FIC2_OFFSET 0x2 837 #define MPU_VIOLATION_INTEN_CR_FIC2_MASK (0x01 << 0x2) 838 /* Enables the interrupt*/ 839 #define MPU_VIOLATION_INTEN_CR_ATHENA_OFFSET 0x3 840 #define MPU_VIOLATION_INTEN_CR_ATHENA_MASK (0x01 << 0x3) 841 /* Enables the interrupt*/ 842 #define MPU_VIOLATION_INTEN_CR_GEM0_OFFSET 0x4 843 #define MPU_VIOLATION_INTEN_CR_GEM0_MASK (0x01 << 0x4) 844 /* Enables the interrupt*/ 845 #define MPU_VIOLATION_INTEN_CR_GEM1_OFFSET 0x5 846 #define MPU_VIOLATION_INTEN_CR_GEM1_MASK (0x01 << 0x5) 847 /* Enables the interrupt*/ 848 #define MPU_VIOLATION_INTEN_CR_USB_OFFSET 0x6 849 #define MPU_VIOLATION_INTEN_CR_USB_MASK (0x01 << 0x6) 850 /* Enables the interrupt*/ 851 #define MPU_VIOLATION_INTEN_CR_MMC_OFFSET 0x7 852 #define MPU_VIOLATION_INTEN_CR_MMC_MASK (0x01 << 0x7) 853 /* Enables the interrupt*/ 854 #define MPU_VIOLATION_INTEN_CR_SCB_OFFSET 0x8 855 #define MPU_VIOLATION_INTEN_CR_SCB_MASK (0x01 << 0x8) 856 /* Enables the interrupt*/ 857 #define MPU_VIOLATION_INTEN_CR_TRACE_OFFSET 0x9 858 #define MPU_VIOLATION_INTEN_CR_TRACE_MASK (0x01 << 0x9) 859 860 /*AXI switch decode fail*/ 861 #define SW_FAIL_ADDR0_CR_OFFSET 0xF8 862 /* The address (bits 31:0) that failed. Reading this address as 64-bits 863 will return the 38-bit address in a single read combined with additional i 864 nformation in the next register*/ 865 #define SW_FAIL_ADDR0_CR_ADDR_OFFSET 0x0 866 #define SW_FAIL_ADDR0_CR_ADDR_MASK (0xFFFFFFFF << 0x0) 867 868 /*AXI switch decode fail*/ 869 #define SW_FAIL_ADDR1_CR_OFFSET 0xFC 870 /* Upper 6 bits off address [37:32]*/ 871 #define SW_FAIL_ADDR1_CR_ADDR_OFFSET 0x0 872 #define SW_FAIL_ADDR1_CR_ADDR_MASK (0x3F << 0x0) 873 /* AXI ID off failure*/ 874 #define SW_FAIL_ADDR1_CR_ID_OFFSET 0x8 875 #define SW_FAIL_ADDR1_CR_ID_MASK (0xFF << 0x8) 876 /* AXI write=1 or read=0*/ 877 #define SW_FAIL_ADDR1_CR_WRITE_OFFSET 0x10 878 #define SW_FAIL_ADDR1_CR_WRITE_MASK (0x01 << 0x10) 879 /* */ 880 #define SW_FAIL_ADDR1_CR_FAILED_OFFSET 0x11 881 #define SW_FAIL_ADDR1_CR_FAILED_MASK (0x01 << 0x11) 882 883 /*Set when an ECC event happens*/ 884 #define EDAC_SR_OFFSET 0x100 885 /* */ 886 #define EDAC_SR_MMC_1E_OFFSET 0x0 887 #define EDAC_SR_MMC_1E_MASK (0x01 << 0x0) 888 /* */ 889 #define EDAC_SR_MMC_2E_OFFSET 0x1 890 #define EDAC_SR_MMC_2E_MASK (0x01 << 0x1) 891 /* */ 892 #define EDAC_SR_DDRC_1E_OFFSET 0x2 893 #define EDAC_SR_DDRC_1E_MASK (0x01 << 0x2) 894 /* */ 895 #define EDAC_SR_DDRC_2E_OFFSET 0x3 896 #define EDAC_SR_DDRC_2E_MASK (0x01 << 0x3) 897 /* */ 898 #define EDAC_SR_MAC0_1E_OFFSET 0x4 899 #define EDAC_SR_MAC0_1E_MASK (0x01 << 0x4) 900 /* */ 901 #define EDAC_SR_MAC0_2E_OFFSET 0x5 902 #define EDAC_SR_MAC0_2E_MASK (0x01 << 0x5) 903 /* */ 904 #define EDAC_SR_MAC1_1E_OFFSET 0x6 905 #define EDAC_SR_MAC1_1E_MASK (0x01 << 0x6) 906 /* */ 907 #define EDAC_SR_MAC1_2E_OFFSET 0x7 908 #define EDAC_SR_MAC1_2E_MASK (0x01 << 0x7) 909 /* */ 910 #define EDAC_SR_USB_1E_OFFSET 0x8 911 #define EDAC_SR_USB_1E_MASK (0x01 << 0x8) 912 /* */ 913 #define EDAC_SR_USB_2E_OFFSET 0x9 914 #define EDAC_SR_USB_2E_MASK (0x01 << 0x9) 915 /* */ 916 #define EDAC_SR_CAN0_1E_OFFSET 0xA 917 #define EDAC_SR_CAN0_1E_MASK (0x01 << 0xA) 918 /* */ 919 #define EDAC_SR_CAN0_2E_OFFSET 0xB 920 #define EDAC_SR_CAN0_2E_MASK (0x01 << 0xB) 921 /* */ 922 #define EDAC_SR_CAN1_1E_OFFSET 0xC 923 #define EDAC_SR_CAN1_1E_MASK (0x01 << 0xC) 924 /* */ 925 #define EDAC_SR_CAN1_2E_OFFSET 0xD 926 #define EDAC_SR_CAN1_2E_MASK (0x01 << 0xD) 927 928 /*Enables ECC interrupt on event*/ 929 #define EDAC_INTEN_CR_OFFSET 0x104 930 /* */ 931 #define EDAC_INTEN_CR_MMC_1E_OFFSET 0x0 932 #define EDAC_INTEN_CR_MMC_1E_MASK (0x01 << 0x0) 933 /* */ 934 #define EDAC_INTEN_CR_MMC_2E_OFFSET 0x1 935 #define EDAC_INTEN_CR_MMC_2E_MASK (0x01 << 0x1) 936 /* */ 937 #define EDAC_INTEN_CR_DDRC_1E_OFFSET 0x2 938 #define EDAC_INTEN_CR_DDRC_1E_MASK (0x01 << 0x2) 939 /* */ 940 #define EDAC_INTEN_CR_DDRC_2E_OFFSET 0x3 941 #define EDAC_INTEN_CR_DDRC_2E_MASK (0x01 << 0x3) 942 /* */ 943 #define EDAC_INTEN_CR_MAC0_1E_OFFSET 0x4 944 #define EDAC_INTEN_CR_MAC0_1E_MASK (0x01 << 0x4) 945 /* */ 946 #define EDAC_INTEN_CR_MAC0_2E_OFFSET 0x5 947 #define EDAC_INTEN_CR_MAC0_2E_MASK (0x01 << 0x5) 948 /* */ 949 #define EDAC_INTEN_CR_MAC1_1E_OFFSET 0x6 950 #define EDAC_INTEN_CR_MAC1_1E_MASK (0x01 << 0x6) 951 /* */ 952 #define EDAC_INTEN_CR_MAC1_2E_OFFSET 0x7 953 #define EDAC_INTEN_CR_MAC1_2E_MASK (0x01 << 0x7) 954 /* */ 955 #define EDAC_INTEN_CR_USB_1E_OFFSET 0x8 956 #define EDAC_INTEN_CR_USB_1E_MASK (0x01 << 0x8) 957 /* */ 958 #define EDAC_INTEN_CR_USB_2E_OFFSET 0x9 959 #define EDAC_INTEN_CR_USB_2E_MASK (0x01 << 0x9) 960 /* */ 961 #define EDAC_INTEN_CR_CAN0_1E_OFFSET 0xA 962 #define EDAC_INTEN_CR_CAN0_1E_MASK (0x01 << 0xA) 963 /* */ 964 #define EDAC_INTEN_CR_CAN0_2E_OFFSET 0xB 965 #define EDAC_INTEN_CR_CAN0_2E_MASK (0x01 << 0xB) 966 /* */ 967 #define EDAC_INTEN_CR_CAN1_1E_OFFSET 0xC 968 #define EDAC_INTEN_CR_CAN1_1E_MASK (0x01 << 0xC) 969 /* */ 970 #define EDAC_INTEN_CR_CAN1_2E_OFFSET 0xD 971 #define EDAC_INTEN_CR_CAN1_2E_MASK (0x01 << 0xD) 972 973 /*Count off single bit errors*/ 974 #define EDAC_CNT_MMC_OFFSET 0x108 975 /* */ 976 #define EDAC_CNT_MMC_COUNT_OFFSET 0x0 977 #define EDAC_CNT_MMC_COUNT_MASK (0x3FF << 0x0) 978 979 /*Count off single bit errors*/ 980 #define EDAC_CNT_DDRC_OFFSET 0x10C 981 /* */ 982 #define EDAC_CNT_DDRC_COUNT_OFFSET 0x0 983 #define EDAC_CNT_DDRC_COUNT_MASK (0x3FF << 0x0) 984 985 /*Count off single bit errors*/ 986 #define EDAC_CNT_MAC0_OFFSET 0x110 987 /* */ 988 #define EDAC_CNT_MAC0_COUNT_OFFSET 0x0 989 #define EDAC_CNT_MAC0_COUNT_MASK (0x3FF << 0x0) 990 991 /*Count off single bit errors*/ 992 #define EDAC_CNT_MAC1_OFFSET 0x114 993 /* */ 994 #define EDAC_CNT_MAC1_COUNT_OFFSET 0x0 995 #define EDAC_CNT_MAC1_COUNT_MASK (0x3FF << 0x0) 996 997 /*Count off single bit errors*/ 998 #define EDAC_CNT_USB_OFFSET 0x118 999 /* */ 1000 #define EDAC_CNT_USB_COUNT_OFFSET 0x0 1001 #define EDAC_CNT_USB_COUNT_MASK (0x3FF << 0x0) 1002 1003 /*Count off single bit errors*/ 1004 #define EDAC_CNT_CAN0_OFFSET 0x11C 1005 /* */ 1006 #define EDAC_CNT_CAN0_COUNT_OFFSET 0x0 1007 #define EDAC_CNT_CAN0_COUNT_MASK (0x3FF << 0x0) 1008 1009 /*Count off single bit errors*/ 1010 #define EDAC_CNT_CAN1_OFFSET 0x120 1011 /* */ 1012 #define EDAC_CNT_CAN1_COUNT_OFFSET 0x0 1013 #define EDAC_CNT_CAN1_COUNT_MASK (0x3FF << 0x0) 1014 1015 /*"Will Corrupt write data to rams 1E corrupts bit 0 2E bits 1 and 2.Inject 1016 s Errors into all RAMS in the block as long as the bits are set. Setting 1E 1017 and 2E will inject a 3-bit error"*/ 1018 #define EDAC_INJECT_CR_OFFSET 0x124 1019 /* */ 1020 #define EDAC_INJECT_CR_MMC_1E_OFFSET 0x0 1021 #define EDAC_INJECT_CR_MMC_1E_MASK (0x01 << 0x0) 1022 /* */ 1023 #define EDAC_INJECT_CR_MMC_2E_OFFSET 0x1 1024 #define EDAC_INJECT_CR_MMC_2E_MASK (0x01 << 0x1) 1025 /* */ 1026 #define EDAC_INJECT_CR_DDRC_1E_OFFSET 0x2 1027 #define EDAC_INJECT_CR_DDRC_1E_MASK (0x01 << 0x2) 1028 /* */ 1029 #define EDAC_INJECT_CR_DDRC_2E_OFFSET 0x3 1030 #define EDAC_INJECT_CR_DDRC_2E_MASK (0x01 << 0x3) 1031 /* */ 1032 #define EDAC_INJECT_CR_MAC0_1E_OFFSET 0x4 1033 #define EDAC_INJECT_CR_MAC0_1E_MASK (0x01 << 0x4) 1034 /* */ 1035 #define EDAC_INJECT_CR_MAC0_2E_OFFSET 0x5 1036 #define EDAC_INJECT_CR_MAC0_2E_MASK (0x01 << 0x5) 1037 /* */ 1038 #define EDAC_INJECT_CR_MAC1_1E_OFFSET 0x6 1039 #define EDAC_INJECT_CR_MAC1_1E_MASK (0x01 << 0x6) 1040 /* */ 1041 #define EDAC_INJECT_CR_MAC1_2E_OFFSET 0x7 1042 #define EDAC_INJECT_CR_MAC1_2E_MASK (0x01 << 0x7) 1043 /* */ 1044 #define EDAC_INJECT_CR_USB_1E_OFFSET 0x8 1045 #define EDAC_INJECT_CR_USB_1E_MASK (0x01 << 0x8) 1046 /* */ 1047 #define EDAC_INJECT_CR_USB_2E_OFFSET 0x9 1048 #define EDAC_INJECT_CR_USB_2E_MASK (0x01 << 0x9) 1049 /* */ 1050 #define EDAC_INJECT_CR_CAN0_1E_OFFSET 0xA 1051 #define EDAC_INJECT_CR_CAN0_1E_MASK (0x01 << 0xA) 1052 /* */ 1053 #define EDAC_INJECT_CR_CAN0_2E_OFFSET 0xB 1054 #define EDAC_INJECT_CR_CAN0_2E_MASK (0x01 << 0xB) 1055 /* */ 1056 #define EDAC_INJECT_CR_CAN1_1E_OFFSET 0xC 1057 #define EDAC_INJECT_CR_CAN1_1E_MASK (0x01 << 0xC) 1058 /* */ 1059 #define EDAC_INJECT_CR_CAN1_2E_OFFSET 0xD 1060 #define EDAC_INJECT_CR_CAN1_2E_MASK (0x01 << 0xD) 1061 1062 /*Maintenance Interrupt Enable.*/ 1063 #define MAINTENANCE_INTEN_CR_OFFSET 0x140 1064 /* Enables interrupt on a PLL event PLL_STATUS_INTEN_CR should also be 1065 set*/ 1066 #define MAINTENANCE_INTEN_CR_PLL_OFFSET 0x0 1067 #define MAINTENANCE_INTEN_CR_PLL_MASK (0x01 << 0x0) 1068 /* Enables interrupt on a MPU access violation */ 1069 #define MAINTENANCE_INTEN_CR_MPU_OFFSET 0x1 1070 #define MAINTENANCE_INTEN_CR_MPU_MASK (0x01 << 0x1) 1071 /* Enables interrupt on a AXI switch decode error*/ 1072 #define MAINTENANCE_INTEN_CR_DECODE_OFFSET 0x2 1073 #define MAINTENANCE_INTEN_CR_DECODE_MASK (0x01 << 0x2) 1074 /* Enables interrupt as lp_state goes high*/ 1075 #define MAINTENANCE_INTEN_CR_LP_STATE_ENTER_OFFSET 0x3 1076 #define MAINTENANCE_INTEN_CR_LP_STATE_ENTER_MASK (0x01 << 0x3) 1077 /* Enables interrupt as lp_state goes low*/ 1078 #define MAINTENANCE_INTEN_CR_LP_STATE_EXIT_OFFSET 0x4 1079 #define MAINTENANCE_INTEN_CR_LP_STATE_EXIT_MASK (0x01 << 0x4) 1080 /* Enables interrupt as flash_freeze goes high*/ 1081 #define MAINTENANCE_INTEN_CR_FF_START_OFFSET 0x5 1082 #define MAINTENANCE_INTEN_CR_FF_START_MASK (0x01 << 0x5) 1083 /* Enables interrupt as flash_freeze goes low*/ 1084 #define MAINTENANCE_INTEN_CR_FF_END_OFFSET 0x6 1085 #define MAINTENANCE_INTEN_CR_FF_END_MASK (0x01 << 0x6) 1086 /* Enables interrupt when FPGA turned on*/ 1087 #define MAINTENANCE_INTEN_CR_FPGA_ON_OFFSET 0x7 1088 #define MAINTENANCE_INTEN_CR_FPGA_ON_MASK (0x01 << 0x7) 1089 /* Enables interrupt when FPGA turned off*/ 1090 #define MAINTENANCE_INTEN_CR_FPGA_OFF_OFFSET 0x8 1091 #define MAINTENANCE_INTEN_CR_FPGA_OFF_MASK (0x01 << 0x8) 1092 /* Enables interrupt on SCB error*/ 1093 #define MAINTENANCE_INTEN_CR_SCB_ERROR_OFFSET 0x9 1094 #define MAINTENANCE_INTEN_CR_SCB_ERROR_MASK (0x01 << 0x9) 1095 /* Enables interrupt on SCB failure*/ 1096 #define MAINTENANCE_INTEN_CR_SCB_FAULT_OFFSET 0xA 1097 #define MAINTENANCE_INTEN_CR_SCB_FAULT_MASK (0x01 << 0xA) 1098 /* Enables interrupt on Mesh violation detection */ 1099 #define MAINTENANCE_INTEN_CR_MESH_ERROR_OFFSET 0xB 1100 #define MAINTENANCE_INTEN_CR_MESH_ERROR_MASK (0x01 << 0xB) 1101 /* Enables interrupt on bank2 powered on*/ 1102 #define MAINTENANCE_INTEN_CR_IO_BANK_B2_ON_OFFSET 0xC 1103 #define MAINTENANCE_INTEN_CR_IO_BANK_B2_ON_MASK (0x01 << 0xC) 1104 /* Enables interrupt on bank4 powered on*/ 1105 #define MAINTENANCE_INTEN_CR_IO_BANK_B4_ON_OFFSET 0xD 1106 #define MAINTENANCE_INTEN_CR_IO_BANK_B4_ON_MASK (0x01 << 0xD) 1107 /* Enables interrupt on bank5 powered on*/ 1108 #define MAINTENANCE_INTEN_CR_IO_BANK_B5_ON_OFFSET 0xE 1109 #define MAINTENANCE_INTEN_CR_IO_BANK_B5_ON_MASK (0x01 << 0xE) 1110 /* Enables interrupt on bank6 powered on*/ 1111 #define MAINTENANCE_INTEN_CR_IO_BANK_B6_ON_OFFSET 0xF 1112 #define MAINTENANCE_INTEN_CR_IO_BANK_B6_ON_MASK (0x01 << 0xF) 1113 /* Enables interrupt on bank2 powered off*/ 1114 #define MAINTENANCE_INTEN_CR_IO_BANK_B2_OFF_OFFSET 0x10 1115 #define MAINTENANCE_INTEN_CR_IO_BANK_B2_OFF_MASK (0x01 << 0x10) 1116 /* Enables interrupt on bank4 powered off*/ 1117 #define MAINTENANCE_INTEN_CR_IO_BANK_B4_OFF_OFFSET 0x11 1118 #define MAINTENANCE_INTEN_CR_IO_BANK_B4_OFF_MASK (0x01 << 0x11) 1119 /* Enables interrupt on bank5 powered off*/ 1120 #define MAINTENANCE_INTEN_CR_IO_BANK_B5_OFF_OFFSET 0x12 1121 #define MAINTENANCE_INTEN_CR_IO_BANK_B5_OFF_MASK (0x01 << 0x12) 1122 /* Enables interrupt on bank6 powered off*/ 1123 #define MAINTENANCE_INTEN_CR_IO_BANK_B6_OFF_OFFSET 0x13 1124 #define MAINTENANCE_INTEN_CR_IO_BANK_B6_OFF_MASK (0x01 << 0x13) 1125 /* Enables interrupt on a DLL event DLL_STATUS_INTEN_CR should also be 1126 set*/ 1127 #define MAINTENANCE_INTEN_CR_DLL_OFFSET 0x14 1128 #define MAINTENANCE_INTEN_CR_DLL_MASK (0x01 << 0x14) 1129 1130 /*PLL Status interrupt enables*/ 1131 #define PLL_STATUS_INTEN_CR_OFFSET 0x144 1132 /* Enables interrupt on CPU PLL locking*/ 1133 #define PLL_STATUS_INTEN_CR_CPU_LOCK_OFFSET 0x0 1134 #define PLL_STATUS_INTEN_CR_CPU_LOCK_MASK (0x01 << 0x0) 1135 /* Enables interrupt on DFT PLL locking*/ 1136 #define PLL_STATUS_INTEN_CR_DFI_LOCK_OFFSET 0x1 1137 #define PLL_STATUS_INTEN_CR_DFI_LOCK_MASK (0x01 << 0x1) 1138 /* Enables interrupt on SGMII PLL locking*/ 1139 #define PLL_STATUS_INTEN_CR_SGMII_LOCK_OFFSET 0x2 1140 #define PLL_STATUS_INTEN_CR_SGMII_LOCK_MASK (0x01 << 0x2) 1141 /* Enables interrupt on CPU PLL unlocking*/ 1142 #define PLL_STATUS_INTEN_CR_CPU_UNLOCK_OFFSET 0x4 1143 #define PLL_STATUS_INTEN_CR_CPU_UNLOCK_MASK (0x01 << 0x4) 1144 /* Enables interrupt on DFT PLL unlocking*/ 1145 #define PLL_STATUS_INTEN_CR_DFI_UNLOCK_OFFSET 0x5 1146 #define PLL_STATUS_INTEN_CR_DFI_UNLOCK_MASK (0x01 << 0x5) 1147 /* Enables interrupt on SGMII PLL unlocking*/ 1148 #define PLL_STATUS_INTEN_CR_SGMII_UNLOCK_OFFSET 0x6 1149 #define PLL_STATUS_INTEN_CR_SGMII_UNLOCK_MASK (0x01 << 0x6) 1150 1151 /*Maintenance interrupt indicates fault and status events.*/ 1152 #define MAINTENANCE_INT_SR_OFFSET 0x148 1153 /* Indicates that one off the PLLs whent into the lock or unlock state. 1154 Cleared via PLL status register*/ 1155 #define MAINTENANCE_INT_SR_PLL_OFFSET 0x0 1156 #define MAINTENANCE_INT_SR_PLL_MASK (0x01 << 0x0) 1157 /* Indicates that one off the MPUS signaled a MPU violation. Cleared vi 1158 a MPU Violation Register*/ 1159 #define MAINTENANCE_INT_SR_MPU_OFFSET 0x1 1160 #define MAINTENANCE_INT_SR_MPU_MASK (0x01 << 0x1) 1161 /* Indicates that the AXI switch detected an illegal address. Cleared w 1162 hen SREG.SW_FAIL.ADDR1_CR_FAILED is cleared.*/ 1163 #define MAINTENANCE_INT_SR_DECODE_OFFSET 0x2 1164 #define MAINTENANCE_INT_SR_DECODE_MASK (0x01 << 0x2) 1165 /* Indicates the device has entered the lower power state cleared by wr 1166 iting '1'*/ 1167 #define MAINTENANCE_INT_SR_LP_STATE_ENTER_OFFSET 0x3 1168 #define MAINTENANCE_INT_SR_LP_STATE_ENTER_MASK (0x01 << 0x3) 1169 /* Indicates the device has exited the lower power state cleared by wri 1170 ting '1'*/ 1171 #define MAINTENANCE_INT_SR_LP_STATE_EXIT_OFFSET 0x4 1172 #define MAINTENANCE_INT_SR_LP_STATE_EXIT_MASK (0x01 << 0x4) 1173 /* Indicates the device has entered the flash freezer state cleared by 1174 writing '1'*/ 1175 #define MAINTENANCE_INT_SR_FF_START_OFFSET 0x5 1176 #define MAINTENANCE_INT_SR_FF_START_MASK (0x01 << 0x5) 1177 /* Indicates the device has exited the flash freezer state cleared by w 1178 riting '1'*/ 1179 #define MAINTENANCE_INT_SR_FF_END_OFFSET 0x6 1180 #define MAINTENANCE_INT_SR_FF_END_MASK (0x01 << 0x6) 1181 /* Indicates that the FPGA array has been turned on cleared by writing 1182 a '1'*/ 1183 #define MAINTENANCE_INT_SR_FPGA_ON_OFFSET 0x7 1184 #define MAINTENANCE_INT_SR_FPGA_ON_MASK (0x01 << 0x7) 1185 /* Indicates that the FPGA array has been turned off cleared by writing 1186 a '1'*/ 1187 #define MAINTENANCE_INT_SR_FPGA_OFF_OFFSET 0x8 1188 #define MAINTENANCE_INT_SR_FPGA_OFF_MASK (0x01 << 0x8) 1189 /* Indicates that the SCB slave reported an error cleared via SCB contr 1190 oller*/ 1191 #define MAINTENANCE_INT_SR_SCB_ERROR_OFFSET 0x9 1192 #define MAINTENANCE_INT_SR_SCB_ERROR_MASK (0x01 << 0x9) 1193 /* Indicates that the SCB bus fault occurred cleared via SCB controller 1194 */ 1195 #define MAINTENANCE_INT_SR_SCB_FAULT_OFFSET 0xA 1196 #define MAINTENANCE_INT_SR_SCB_FAULT_MASK (0x01 << 0xA) 1197 /* Indicates that the mesh over the Crypto triggered cleared via Mesh s 1198 ystem error*/ 1199 #define MAINTENANCE_INT_SR_MESH_ERROR_OFFSET 0xB 1200 #define MAINTENANCE_INT_SR_MESH_ERROR_MASK (0x01 << 0xB) 1201 /* Indicates that IO bank 2 has turned on cleared by writing a '1'*/ 1202 #define MAINTENANCE_INT_SR_IO_BANK_B2_ON_OFFSET 0xC 1203 #define MAINTENANCE_INT_SR_IO_BANK_B2_ON_MASK (0x01 << 0xC) 1204 /* Indicates that IO bank 4 has turned on cleared by writing a '1'*/ 1205 #define MAINTENANCE_INT_SR_IO_BANK_B4_ON_OFFSET 0xD 1206 #define MAINTENANCE_INT_SR_IO_BANK_B4_ON_MASK (0x01 << 0xD) 1207 /* Indicates that IO bank 5 has turned on cleared by writing a '1'*/ 1208 #define MAINTENANCE_INT_SR_IO_BANK_B5_ON_OFFSET 0xE 1209 #define MAINTENANCE_INT_SR_IO_BANK_B5_ON_MASK (0x01 << 0xE) 1210 /* Indicates that IO bank 6 has turned on cleared by writing a '1'*/ 1211 #define MAINTENANCE_INT_SR_IO_BANK_B6_ON_OFFSET 0xF 1212 #define MAINTENANCE_INT_SR_IO_BANK_B6_ON_MASK (0x01 << 0xF) 1213 /* Indicates that IO bank 2 has turned off cleared by writing a '1'*/ 1214 #define MAINTENANCE_INT_SR_IO_BANK_B2_OFF_OFFSET 0x10 1215 #define MAINTENANCE_INT_SR_IO_BANK_B2_OFF_MASK (0x01 << 0x10) 1216 /* Indicates that IO bank 4 has turned off cleared by writing a '1'*/ 1217 #define MAINTENANCE_INT_SR_IO_BANK_B4_OFF_OFFSET 0x11 1218 #define MAINTENANCE_INT_SR_IO_BANK_B4_OFF_MASK (0x01 << 0x11) 1219 /* Indicates that IO bank 5 has turned off cleared by writing a '1'*/ 1220 #define MAINTENANCE_INT_SR_IO_BANK_B5_OFF_OFFSET 0x12 1221 #define MAINTENANCE_INT_SR_IO_BANK_B5_OFF_MASK (0x01 << 0x12) 1222 /* Indicates that one off the DLLs when into the lock or unlock state. 1223 Cleared via DLL status register*/ 1224 #define MAINTENANCE_INT_SR_IO_BANK_B6_OFF_OFFSET 0x13 1225 #define MAINTENANCE_INT_SR_IO_BANK_B6_OFF_MASK (0x01 << 0x13) 1226 /* Indicates that IO bank 6 has turned off cleared by writing a '1'*/ 1227 #define MAINTENANCE_INT_SR_DLL_OFFSET 0x14 1228 #define MAINTENANCE_INT_SR_DLL_MASK (0x01 << 0x14) 1229 1230 /*PLL interrupt register*/ 1231 #define PLL_STATUS_SR_OFFSET 0x14C 1232 /* Indicates that the CPU PLL has locked cleared by writing a '1'*/ 1233 #define PLL_STATUS_SR_CPU_LOCK_OFFSET 0x0 1234 #define PLL_STATUS_SR_CPU_LOCK_MASK (0x01 << 0x0) 1235 /* Indicates that the DFI PLL has locked cleared by writing a '1'*/ 1236 #define PLL_STATUS_SR_DFI_LOCK_OFFSET 0x1 1237 #define PLL_STATUS_SR_DFI_LOCK_MASK (0x01 << 0x1) 1238 /* Indicates that the SGMII PLL has locked cleared by writing a '1'*/ 1239 #define PLL_STATUS_SR_SGMII_LOCK_OFFSET 0x2 1240 #define PLL_STATUS_SR_SGMII_LOCK_MASK (0x01 << 0x2) 1241 /* Indicates that the CPU PLL has unlocked cleared by writing a '1'*/ 1242 #define PLL_STATUS_SR_CPU_UNLOCK_OFFSET 0x4 1243 #define PLL_STATUS_SR_CPU_UNLOCK_MASK (0x01 << 0x4) 1244 /* Indicates that the DFI PLL has unlocked cleared by writing a '1'*/ 1245 #define PLL_STATUS_SR_DFI_UNLOCK_OFFSET 0x5 1246 #define PLL_STATUS_SR_DFI_UNLOCK_MASK (0x01 << 0x5) 1247 /* Indicates that the SGMII PLL has unlocked cleared by writing a '1'*/ 1248 #define PLL_STATUS_SR_SGMII_UNLOCK_OFFSET 0x6 1249 #define PLL_STATUS_SR_SGMII_UNLOCK_MASK (0x01 << 0x6) 1250 /* Current state off CPU PLL locked signal*/ 1251 #define PLL_STATUS_SR_CPU_LOCK_NOW_OFFSET 0x8 1252 #define PLL_STATUS_SR_CPU_LOCK_NOW_MASK (0x01 << 0x8) 1253 /* Current state off DFI PLL locked signal*/ 1254 #define PLL_STATUS_SR_DFI_LOCK_NOW_OFFSET 0x9 1255 #define PLL_STATUS_SR_DFI_LOCK_NOW_MASK (0x01 << 0x9) 1256 /* Current state off SGMII PLL locked signal*/ 1257 #define PLL_STATUS_SR_SGMII_LOCK_NOW_OFFSET 0xA 1258 #define PLL_STATUS_SR_SGMII_LOCK_NOW_MASK (0x01 << 0xA) 1259 1260 /*Enable to CFM Timer */ 1261 #define CFM_TIMER_CR_OFFSET 0x150 1262 /* When set and the CFM channel is in timer mode and CFM channel is set 1263 to 2 (Group C) this register allows the timet to count. Allows software to 1264 start and stop the timers.*/ 1265 #define CFM_TIMER_CR_ENABLE_OFFSET 0x0 1266 #define CFM_TIMER_CR_ENABLE_MASK (0x1F << 0x0) 1267 1268 /*Miscellaneous Register*/ 1269 #define MISC_SR_OFFSET 0x154 1270 /* Indicates that Interrupt from the G5C MSS SCB SPI controller is acti 1271 ve*/ 1272 #define MISC_SR_CONT_SPI_INTERRUPT_OFFSET 0x0 1273 #define MISC_SR_CONT_SPI_INTERRUPT_MASK (0x01 << 0x0) 1274 /* Indicates that the user voltage or temperature detectors are signali 1275 ng an alarm condition.*/ 1276 #define MISC_SR_VOLT_TEMP_ALARM_OFFSET 0x1 1277 #define MISC_SR_VOLT_TEMP_ALARM_MASK (0x01 << 0x1) 1278 1279 /*DLL Interrupt enables*/ 1280 #define DLL_STATUS_CR_OFFSET 0x158 1281 /* Enables the DLL0 lock interrupt*/ 1282 #define DLL_STATUS_CR_FIC0_LOCK_OFFSET 0x0 1283 #define DLL_STATUS_CR_FIC0_LOCK_MASK (0x01 << 0x0) 1284 /* Enables the DLL1 lock interrupt*/ 1285 #define DLL_STATUS_CR_FIC1_LOCK_OFFSET 0x1 1286 #define DLL_STATUS_CR_FIC1_LOCK_MASK (0x01 << 0x1) 1287 /* Enables the DLL2 lock interrupt*/ 1288 #define DLL_STATUS_CR_FIC2_LOCK_OFFSET 0x2 1289 #define DLL_STATUS_CR_FIC2_LOCK_MASK (0x01 << 0x2) 1290 /* Enables the DLL3 lock interrupt*/ 1291 #define DLL_STATUS_CR_FIC3_LOCK_OFFSET 0x4 1292 #define DLL_STATUS_CR_FIC3_LOCK_MASK (0x01 << 0x4) 1293 /* Enables the DLL4 (Crypto) lock interrupt*/ 1294 #define DLL_STATUS_CR_FIC4_LOCK_OFFSET 0x5 1295 #define DLL_STATUS_CR_FIC4_LOCK_MASK (0x01 << 0x5) 1296 /* Enables the DLL0 unlock interrupt*/ 1297 #define DLL_STATUS_CR_FIC0_UNLOCK_OFFSET 0x8 1298 #define DLL_STATUS_CR_FIC0_UNLOCK_MASK (0x01 << 0x8) 1299 /* Enables the DLL1 unlock interrupt*/ 1300 #define DLL_STATUS_CR_FIC1_UNLOCK_OFFSET 0x9 1301 #define DLL_STATUS_CR_FIC1_UNLOCK_MASK (0x01 << 0x9) 1302 /* Enables the DLL2 unlock interrupt*/ 1303 #define DLL_STATUS_CR_FIC2_UNLOCK_OFFSET 0xA 1304 #define DLL_STATUS_CR_FIC2_UNLOCK_MASK (0x01 << 0xA) 1305 /* Enables the DLL3 unlock interrupt*/ 1306 #define DLL_STATUS_CR_FIC3_UNLOCK_OFFSET 0xB 1307 #define DLL_STATUS_CR_FIC3_UNLOCK_MASK (0x01 << 0xB) 1308 /* Enables the DLL4 (crypto) unlock interrupt*/ 1309 #define DLL_STATUS_CR_FIC4_UNLOCK_OFFSET 0xC 1310 #define DLL_STATUS_CR_FIC4_UNLOCK_MASK (0x01 << 0xC) 1311 1312 /*DLL interrupt register*/ 1313 #define DLL_STATUS_SR_OFFSET 0x15C 1314 /* Indicates that the FIC0 DLL has locked cleared by writing a '1'*/ 1315 #define DLL_STATUS_SR_FIC0_LOCK_OFFSET 0x0 1316 #define DLL_STATUS_SR_FIC0_LOCK_MASK (0x01 << 0x0) 1317 /* Indicates that the FIC1 DLL has locked cleared by writing a '1'*/ 1318 #define DLL_STATUS_SR_FIC1_LOCK_OFFSET 0x1 1319 #define DLL_STATUS_SR_FIC1_LOCK_MASK (0x01 << 0x1) 1320 /* Indicates that the FIC2 DLL has locked cleared by writing a '1'*/ 1321 #define DLL_STATUS_SR_FIC2_LOCK_OFFSET 0x2 1322 #define DLL_STATUS_SR_FIC2_LOCK_MASK (0x01 << 0x2) 1323 /* Indicates that the FIC3 DLL has locked cleared by writing a '1'*/ 1324 #define DLL_STATUS_SR_FIC3_LOCK_OFFSET 0x4 1325 #define DLL_STATUS_SR_FIC3_LOCK_MASK (0x01 << 0x4) 1326 /* Indicates that the FIC4 (Crypto) DLL has locked cleared by writing a 1327 '1'*/ 1328 #define DLL_STATUS_SR_FIC4_LOCK_OFFSET 0x5 1329 #define DLL_STATUS_SR_FIC4_LOCK_MASK (0x01 << 0x5) 1330 /* Indicates that the FIC0 DLL has unlocked cleared by writing a '1'*/ 1331 #define DLL_STATUS_SR_FIC0_UNLOCK_OFFSET 0x8 1332 #define DLL_STATUS_SR_FIC0_UNLOCK_MASK (0x01 << 0x8) 1333 /* Indicates that the FIC1 DLL has unlocked cleared by writing a '1'*/ 1334 #define DLL_STATUS_SR_FIC1_UNLOCK_OFFSET 0x9 1335 #define DLL_STATUS_SR_FIC1_UNLOCK_MASK (0x01 << 0x9) 1336 /* Indicates that the FIC2 DLL has unlocked cleared by writing a '1'*/ 1337 #define DLL_STATUS_SR_FIC2_UNLOCK_OFFSET 0xA 1338 #define DLL_STATUS_SR_FIC2_UNLOCK_MASK (0x01 << 0xA) 1339 /* Indicates that the FIC3 DLL has unlocked cleared by writing a '1'*/ 1340 #define DLL_STATUS_SR_FIC3_UNLOCK_OFFSET 0xB 1341 #define DLL_STATUS_SR_FIC3_UNLOCK_MASK (0x01 << 0xB) 1342 /* Indicates that the FIC4 (Crypto) DLL has unlocked cleared by writing 1343 a '1'*/ 1344 #define DLL_STATUS_SR_FIC4_UNLOCK_OFFSET 0xC 1345 #define DLL_STATUS_SR_FIC4_UNLOCK_MASK (0x01 << 0xC) 1346 /* Current state off FIC0 DLL locked signal*/ 1347 #define DLL_STATUS_SR_FIC0_LOCK_NOW_OFFSET 0x10 1348 #define DLL_STATUS_SR_FIC0_LOCK_NOW_MASK (0x01 << 0x10) 1349 /* Current state off FIC1 DLL locked signal*/ 1350 #define DLL_STATUS_SR_FIC1_LOCK_NOW_OFFSET 0x11 1351 #define DLL_STATUS_SR_FIC1_LOCK_NOW_MASK (0x01 << 0x11) 1352 /* Current state off FIC2 DLL locked signal*/ 1353 #define DLL_STATUS_SR_FIC2_LOCK_NOW_OFFSET 0x12 1354 #define DLL_STATUS_SR_FIC2_LOCK_NOW_MASK (0x01 << 0x12) 1355 /* Current state off FIC3 DLL locked signal*/ 1356 #define DLL_STATUS_SR_FIC3_LOCK_NOW_OFFSET 0x13 1357 #define DLL_STATUS_SR_FIC3_LOCK_NOW_MASK (0x01 << 0x13) 1358 /* Current state off FIC4 DLL locked signal*/ 1359 #define DLL_STATUS_SR_FIC4_LOCK_NOW_OFFSET 0x14 1360 #define DLL_STATUS_SR_FIC4_LOCK_NOW_MASK (0x01 << 0x14) 1361 1362 /*Puts all the RAMS in that block into low leakage mode. RAM contents and Q 1363 value preserved.*/ 1364 #define RAM_LIGHTSLEEP_CR_OFFSET 0x168 1365 /* */ 1366 #define RAM_LIGHTSLEEP_CR_CAN0_OFFSET 0x0 1367 #define RAM_LIGHTSLEEP_CR_CAN0_MASK (0x01 << 0x0) 1368 /* */ 1369 #define RAM_LIGHTSLEEP_CR_CAN1_OFFSET 0x1 1370 #define RAM_LIGHTSLEEP_CR_CAN1_MASK (0x01 << 0x1) 1371 /* */ 1372 #define RAM_LIGHTSLEEP_CR_USB_OFFSET 0x2 1373 #define RAM_LIGHTSLEEP_CR_USB_MASK (0x01 << 0x2) 1374 /* */ 1375 #define RAM_LIGHTSLEEP_CR_GEM0_OFFSET 0x3 1376 #define RAM_LIGHTSLEEP_CR_GEM0_MASK (0x01 << 0x3) 1377 /* */ 1378 #define RAM_LIGHTSLEEP_CR_GEM1_OFFSET 0x4 1379 #define RAM_LIGHTSLEEP_CR_GEM1_MASK (0x01 << 0x4) 1380 /* */ 1381 #define RAM_LIGHTSLEEP_CR_MMC_OFFSET 0x5 1382 #define RAM_LIGHTSLEEP_CR_MMC_MASK (0x01 << 0x5) 1383 /* */ 1384 #define RAM_LIGHTSLEEP_CR_ATHENA_OFFSET 0x6 1385 #define RAM_LIGHTSLEEP_CR_ATHENA_MASK (0x01 << 0x6) 1386 /* */ 1387 #define RAM_LIGHTSLEEP_CR_DDRC_OFFSET 0x7 1388 #define RAM_LIGHTSLEEP_CR_DDRC_MASK (0x01 << 0x7) 1389 /* */ 1390 #define RAM_LIGHTSLEEP_CR_E51_OFFSET 0x8 1391 #define RAM_LIGHTSLEEP_CR_E51_MASK (0x01 << 0x8) 1392 /* */ 1393 #define RAM_LIGHTSLEEP_CR_U54_1_OFFSET 0x9 1394 #define RAM_LIGHTSLEEP_CR_U54_1_MASK (0x01 << 0x9) 1395 /* */ 1396 #define RAM_LIGHTSLEEP_CR_U54_2_OFFSET 0xA 1397 #define RAM_LIGHTSLEEP_CR_U54_2_MASK (0x01 << 0xA) 1398 /* */ 1399 #define RAM_LIGHTSLEEP_CR_U54_3_OFFSET 0xB 1400 #define RAM_LIGHTSLEEP_CR_U54_3_MASK (0x01 << 0xB) 1401 /* */ 1402 #define RAM_LIGHTSLEEP_CR_U54_4_OFFSET 0xC 1403 #define RAM_LIGHTSLEEP_CR_U54_4_MASK (0x01 << 0xC) 1404 /* */ 1405 #define RAM_LIGHTSLEEP_CR_L2_OFFSET 0xD 1406 #define RAM_LIGHTSLEEP_CR_L2_MASK (0x01 << 0xD) 1407 1408 /*Puts all the RAMS in that block into deep sleep mode. RAM contents preser 1409 ved. Powers down the periphery circuits.*/ 1410 #define RAM_DEEPSLEEP_CR_OFFSET 0x16C 1411 /* */ 1412 #define RAM_DEEPSLEEP_CR_CAN0_OFFSET 0x0 1413 #define RAM_DEEPSLEEP_CR_CAN0_MASK (0x01 << 0x0) 1414 /* */ 1415 #define RAM_DEEPSLEEP_CR_CAN1_OFFSET 0x1 1416 #define RAM_DEEPSLEEP_CR_CAN1_MASK (0x01 << 0x1) 1417 /* */ 1418 #define RAM_DEEPSLEEP_CR_USB_OFFSET 0x2 1419 #define RAM_DEEPSLEEP_CR_USB_MASK (0x01 << 0x2) 1420 /* */ 1421 #define RAM_DEEPSLEEP_CR_GEM0_OFFSET 0x3 1422 #define RAM_DEEPSLEEP_CR_GEM0_MASK (0x01 << 0x3) 1423 /* */ 1424 #define RAM_DEEPSLEEP_CR_GEM1_OFFSET 0x4 1425 #define RAM_DEEPSLEEP_CR_GEM1_MASK (0x01 << 0x4) 1426 /* */ 1427 #define RAM_DEEPSLEEP_CR_MMC_OFFSET 0x5 1428 #define RAM_DEEPSLEEP_CR_MMC_MASK (0x01 << 0x5) 1429 /* */ 1430 #define RAM_DEEPSLEEP_CR_ATHENA_OFFSET 0x6 1431 #define RAM_DEEPSLEEP_CR_ATHENA_MASK (0x01 << 0x6) 1432 /* */ 1433 #define RAM_DEEPSLEEP_CR_DDRC_OFFSET 0x7 1434 #define RAM_DEEPSLEEP_CR_DDRC_MASK (0x01 << 0x7) 1435 /* */ 1436 #define RAM_DEEPSLEEP_CR_E51_OFFSET 0x8 1437 #define RAM_DEEPSLEEP_CR_E51_MASK (0x01 << 0x8) 1438 /* */ 1439 #define RAM_DEEPSLEEP_CR_U54_1_OFFSET 0x9 1440 #define RAM_DEEPSLEEP_CR_U54_1_MASK (0x01 << 0x9) 1441 /* */ 1442 #define RAM_DEEPSLEEP_CR_U54_2_OFFSET 0xA 1443 #define RAM_DEEPSLEEP_CR_U54_2_MASK (0x01 << 0xA) 1444 /* */ 1445 #define RAM_DEEPSLEEP_CR_U54_3_OFFSET 0xB 1446 #define RAM_DEEPSLEEP_CR_U54_3_MASK (0x01 << 0xB) 1447 /* */ 1448 #define RAM_DEEPSLEEP_CR_U54_4_OFFSET 0xC 1449 #define RAM_DEEPSLEEP_CR_U54_4_MASK (0x01 << 0xC) 1450 /* */ 1451 #define RAM_DEEPSLEEP_CR_L2_OFFSET 0xD 1452 #define RAM_DEEPSLEEP_CR_L2_MASK (0x01 << 0xD) 1453 1454 /*Puts all the RAMS in that block into shut down mode. RAM contents not pre 1455 served. Powers down the RAM and periphery circuits.*/ 1456 #define RAM_SHUTDOWN_CR_OFFSET 0x170 1457 /* */ 1458 #define RAM_SHUTDOWN_CR_CAN0_OFFSET 0x0 1459 #define RAM_SHUTDOWN_CR_CAN0_MASK (0x01 << 0x0) 1460 /* */ 1461 #define RAM_SHUTDOWN_CR_CAN1_OFFSET 0x1 1462 #define RAM_SHUTDOWN_CR_CAN1_MASK (0x01 << 0x1) 1463 /* */ 1464 #define RAM_SHUTDOWN_CR_USB_OFFSET 0x2 1465 #define RAM_SHUTDOWN_CR_USB_MASK (0x01 << 0x2) 1466 /* */ 1467 #define RAM_SHUTDOWN_CR_GEM0_OFFSET 0x3 1468 #define RAM_SHUTDOWN_CR_GEM0_MASK (0x01 << 0x3) 1469 /* */ 1470 #define RAM_SHUTDOWN_CR_GEM1_OFFSET 0x4 1471 #define RAM_SHUTDOWN_CR_GEM1_MASK (0x01 << 0x4) 1472 /* */ 1473 #define RAM_SHUTDOWN_CR_MMC_OFFSET 0x5 1474 #define RAM_SHUTDOWN_CR_MMC_MASK (0x01 << 0x5) 1475 /* */ 1476 #define RAM_SHUTDOWN_CR_ATHENA_OFFSET 0x6 1477 #define RAM_SHUTDOWN_CR_ATHENA_MASK (0x01 << 0x6) 1478 /* */ 1479 #define RAM_SHUTDOWN_CR_DDRC_OFFSET 0x7 1480 #define RAM_SHUTDOWN_CR_DDRC_MASK (0x01 << 0x7) 1481 /* */ 1482 #define RAM_SHUTDOWN_CR_E51_OFFSET 0x8 1483 #define RAM_SHUTDOWN_CR_E51_MASK (0x01 << 0x8) 1484 /* */ 1485 #define RAM_SHUTDOWN_CR_U54_1_OFFSET 0x9 1486 #define RAM_SHUTDOWN_CR_U54_1_MASK (0x01 << 0x9) 1487 /* */ 1488 #define RAM_SHUTDOWN_CR_U54_2_OFFSET 0xA 1489 #define RAM_SHUTDOWN_CR_U54_2_MASK (0x01 << 0xA) 1490 /* */ 1491 #define RAM_SHUTDOWN_CR_U54_3_OFFSET 0xB 1492 #define RAM_SHUTDOWN_CR_U54_3_MASK (0x01 << 0xB) 1493 /* */ 1494 #define RAM_SHUTDOWN_CR_U54_4_OFFSET 0xC 1495 #define RAM_SHUTDOWN_CR_U54_4_MASK (0x01 << 0xC) 1496 /* */ 1497 #define RAM_SHUTDOWN_CR_L2_OFFSET 0xD 1498 #define RAM_SHUTDOWN_CR_L2_MASK (0x01 << 0xD) 1499 1500 /*Allows each bank of the L2 Cache to be powered down ORed with global shut 1501 down */ 1502 #define L2_SHUTDOWN_CR_OFFSET 0x174 1503 /* */ 1504 #define L2_SHUTDOWN_CR_L2_RAMS_OFFSET 0x0 1505 #define L2_SHUTDOWN_CR_L2_RAMS_MASK (0x0F << 0x0) 1506 1507 /*Selects whether the peripheral is connected to the Fabric or IOMUX struct 1508 ure.*/ 1509 #define IOMUX0_CR_OFFSET 0x200 1510 /* */ 1511 #define IOMUX0_CR_SPI0_FABRIC_OFFSET 0x0 1512 #define IOMUX0_CR_SPI0_FABRIC_MASK (0x01 << 0x0) 1513 /* */ 1514 #define IOMUX0_CR_SPI1_FABRIC_OFFSET 0x1 1515 #define IOMUX0_CR_SPI1_FABRIC_MASK (0x01 << 0x1) 1516 /* */ 1517 #define IOMUX0_CR_I2C0_FABRIC_OFFSET 0x2 1518 #define IOMUX0_CR_I2C0_FABRIC_MASK (0x01 << 0x2) 1519 /* */ 1520 #define IOMUX0_CR_I2C1_FABRIC_OFFSET 0x3 1521 #define IOMUX0_CR_I2C1_FABRIC_MASK (0x01 << 0x3) 1522 /* */ 1523 #define IOMUX0_CR_CAN0_FABRIC_OFFSET 0x4 1524 #define IOMUX0_CR_CAN0_FABRIC_MASK (0x01 << 0x4) 1525 /* */ 1526 #define IOMUX0_CR_CAN1_FABRIC_OFFSET 0x5 1527 #define IOMUX0_CR_CAN1_FABRIC_MASK (0x01 << 0x5) 1528 /* */ 1529 #define IOMUX0_CR_QSPI_FABRIC_OFFSET 0x6 1530 #define IOMUX0_CR_QSPI_FABRIC_MASK (0x01 << 0x6) 1531 /* */ 1532 #define IOMUX0_CR_MMUART0_FABRIC_OFFSET 0x7 1533 #define IOMUX0_CR_MMUART0_FABRIC_MASK (0x01 << 0x7) 1534 /* */ 1535 #define IOMUX0_CR_MMUART1_FABRIC_OFFSET 0x8 1536 #define IOMUX0_CR_MMUART1_FABRIC_MASK (0x01 << 0x8) 1537 /* */ 1538 #define IOMUX0_CR_MMUART2_FABRIC_OFFSET 0x9 1539 #define IOMUX0_CR_MMUART2_FABRIC_MASK (0x01 << 0x9) 1540 /* */ 1541 #define IOMUX0_CR_MMUART3_FABRIC_OFFSET 0xA 1542 #define IOMUX0_CR_MMUART3_FABRIC_MASK (0x01 << 0xA) 1543 /* */ 1544 #define IOMUX0_CR_MMUART4_FABRIC_OFFSET 0xB 1545 #define IOMUX0_CR_MMUART4_FABRIC_MASK (0x01 << 0xB) 1546 /* */ 1547 #define IOMUX0_CR_MDIO0_FABRIC_OFFSET 0xC 1548 #define IOMUX0_CR_MDIO0_FABRIC_MASK (0x01 << 0xC) 1549 /* */ 1550 #define IOMUX0_CR_MDIO1_FABRIC_OFFSET 0xD 1551 #define IOMUX0_CR_MDIO1_FABRIC_MASK (0x01 << 0xD) 1552 1553 /*Configures the IO Mux structure for each IO pad. See the MSS MAS specific 1554 ation for for description.*/ 1555 #define IOMUX1_CR_OFFSET 0x204 1556 /* */ 1557 #define IOMUX1_CR_PAD0_OFFSET 0x0 1558 #define IOMUX1_CR_PAD0_MASK (0x0F << 0x0) 1559 /* */ 1560 #define IOMUX1_CR_PAD1_OFFSET 0x4 1561 #define IOMUX1_CR_PAD1_MASK (0x0F << 0x4) 1562 /* */ 1563 #define IOMUX1_CR_PAD2_OFFSET 0x8 1564 #define IOMUX1_CR_PAD2_MASK (0x0F << 0x8) 1565 /* */ 1566 #define IOMUX1_CR_PAD3_OFFSET 0xC 1567 #define IOMUX1_CR_PAD3_MASK (0x0F << 0xC) 1568 /* */ 1569 #define IOMUX1_CR_PAD4_OFFSET 0x10 1570 #define IOMUX1_CR_PAD4_MASK (0x0F << 0x10) 1571 /* */ 1572 #define IOMUX1_CR_PAD5_OFFSET 0x14 1573 #define IOMUX1_CR_PAD5_MASK (0x0F << 0x14) 1574 /* */ 1575 #define IOMUX1_CR_PAD6_OFFSET 0x18 1576 #define IOMUX1_CR_PAD6_MASK (0x0F << 0x18) 1577 /* */ 1578 #define IOMUX1_CR_PAD7_OFFSET 0x1C 1579 #define IOMUX1_CR_PAD7_MASK (0x0F << 0x1C) 1580 1581 /*Configures the IO Mux structure for each IO pad. See the MSS MAS specific 1582 ation for for description.*/ 1583 #define IOMUX2_CR_OFFSET 0x208 1584 /* */ 1585 #define IOMUX2_CR_PAD8_OFFSET 0x0 1586 #define IOMUX2_CR_PAD8_MASK (0x0F << 0x0) 1587 /* */ 1588 #define IOMUX2_CR_PAD9_OFFSET 0x4 1589 #define IOMUX2_CR_PAD9_MASK (0x0F << 0x4) 1590 /* */ 1591 #define IOMUX2_CR_PAD10_OFFSET 0x8 1592 #define IOMUX2_CR_PAD10_MASK (0x0F << 0x8) 1593 /* */ 1594 #define IOMUX2_CR_PAD11_OFFSET 0xC 1595 #define IOMUX2_CR_PAD11_MASK (0x0F << 0xC) 1596 /* */ 1597 #define IOMUX2_CR_PAD12_OFFSET 0x10 1598 #define IOMUX2_CR_PAD12_MASK (0x0F << 0x10) 1599 /* */ 1600 #define IOMUX2_CR_PAD13_OFFSET 0x14 1601 #define IOMUX2_CR_PAD13_MASK (0x0F << 0x14) 1602 1603 /*Configures the IO Mux structure for each IO pad. See the MSS MAS specific 1604 ation for for description.*/ 1605 #define IOMUX3_CR_OFFSET 0x20C 1606 /* */ 1607 #define IOMUX3_CR_PAD14_OFFSET 0x0 1608 #define IOMUX3_CR_PAD14_MASK (0x0F << 0x0) 1609 /* */ 1610 #define IOMUX3_CR_PAD15_OFFSET 0x4 1611 #define IOMUX3_CR_PAD15_MASK (0x0F << 0x4) 1612 /* */ 1613 #define IOMUX3_CR_PAD16_OFFSET 0x8 1614 #define IOMUX3_CR_PAD16_MASK (0x0F << 0x8) 1615 /* */ 1616 #define IOMUX3_CR_PAD17_OFFSET 0xC 1617 #define IOMUX3_CR_PAD17_MASK (0x0F << 0xC) 1618 /* */ 1619 #define IOMUX3_CR_PAD18_OFFSET 0x10 1620 #define IOMUX3_CR_PAD18_MASK (0x0F << 0x10) 1621 /* */ 1622 #define IOMUX3_CR_PAD19_OFFSET 0x14 1623 #define IOMUX3_CR_PAD19_MASK (0x0F << 0x14) 1624 /* */ 1625 #define IOMUX3_CR_PAD20_OFFSET 0x18 1626 #define IOMUX3_CR_PAD20_MASK (0x0F << 0x18) 1627 /* */ 1628 #define IOMUX3_CR_PAD21_OFFSET 0x1C 1629 #define IOMUX3_CR_PAD21_MASK (0x0F << 0x1C) 1630 1631 /*Configures the IO Mux structure for each IO pad. See the MSS MAS specific 1632 ation for for description.*/ 1633 #define IOMUX4_CR_OFFSET 0x210 1634 /* */ 1635 #define IOMUX4_CR_PAD22_OFFSET 0x0 1636 #define IOMUX4_CR_PAD22_MASK (0x0F << 0x0) 1637 /* */ 1638 #define IOMUX4_CR_PAD23_OFFSET 0x4 1639 #define IOMUX4_CR_PAD23_MASK (0x0F << 0x4) 1640 /* */ 1641 #define IOMUX4_CR_PAD24_OFFSET 0x8 1642 #define IOMUX4_CR_PAD24_MASK (0x0F << 0x8) 1643 /* */ 1644 #define IOMUX4_CR_PAD25_OFFSET 0xC 1645 #define IOMUX4_CR_PAD25_MASK (0x0F << 0xC) 1646 /* */ 1647 #define IOMUX4_CR_PAD26_OFFSET 0x10 1648 #define IOMUX4_CR_PAD26_MASK (0x0F << 0x10) 1649 /* */ 1650 #define IOMUX4_CR_PAD27_OFFSET 0x14 1651 #define IOMUX4_CR_PAD27_MASK (0x0F << 0x14) 1652 /* */ 1653 #define IOMUX4_CR_PAD28_OFFSET 0x18 1654 #define IOMUX4_CR_PAD28_MASK (0x0F << 0x18) 1655 /* */ 1656 #define IOMUX4_CR_PAD29_OFFSET 0x1C 1657 #define IOMUX4_CR_PAD29_MASK (0x0F << 0x1C) 1658 1659 /*Configures the IO Mux structure for each IO pad. See the MSS MAS specific 1660 ation for for description.*/ 1661 #define IOMUX5_CR_OFFSET 0x214 1662 /* */ 1663 #define IOMUX5_CR_PAD30_OFFSET 0x0 1664 #define IOMUX5_CR_PAD30_MASK (0x0F << 0x0) 1665 /* */ 1666 #define IOMUX5_CR_PAD31_OFFSET 0x4 1667 #define IOMUX5_CR_PAD31_MASK (0x0F << 0x4) 1668 /* */ 1669 #define IOMUX5_CR_PAD32_OFFSET 0x8 1670 #define IOMUX5_CR_PAD32_MASK (0x0F << 0x8) 1671 /* */ 1672 #define IOMUX5_CR_PAD33_OFFSET 0xC 1673 #define IOMUX5_CR_PAD33_MASK (0x0F << 0xC) 1674 /* */ 1675 #define IOMUX5_CR_PAD34_OFFSET 0x10 1676 #define IOMUX5_CR_PAD34_MASK (0x0F << 0x10) 1677 /* */ 1678 #define IOMUX5_CR_PAD35_OFFSET 0x14 1679 #define IOMUX5_CR_PAD35_MASK (0x0F << 0x14) 1680 /* */ 1681 #define IOMUX5_CR_PAD36_OFFSET 0x18 1682 #define IOMUX5_CR_PAD36_MASK (0x0F << 0x18) 1683 /* */ 1684 #define IOMUX5_CR_PAD37_OFFSET 0x1C 1685 #define IOMUX5_CR_PAD37_MASK (0x0F << 0x1C) 1686 1687 /*Sets whether the MMC/SD Voltage select lines are inverted on entry to the 1688 IOMUX structure*/ 1689 #define IOMUX6_CR_OFFSET 0x218 1690 /* */ 1691 #define IOMUX6_CR_VLT_SEL_OFFSET 0x0 1692 #define IOMUX6_CR_VLT_SEL_MASK (0x01 << 0x0) 1693 /* */ 1694 #define IOMUX6_CR_VLT_EN_OFFSET 0x1 1695 #define IOMUX6_CR_VLT_EN_MASK (0x01 << 0x1) 1696 /* */ 1697 #define IOMUX6_CR_VLT_CMD_DIR_OFFSET 0x2 1698 #define IOMUX6_CR_VLT_CMD_DIR_MASK (0x01 << 0x2) 1699 /* */ 1700 #define IOMUX6_CR_VLT_DIR_0_OFFSET 0x3 1701 #define IOMUX6_CR_VLT_DIR_0_MASK (0x01 << 0x3) 1702 /* */ 1703 #define IOMUX6_CR_VLT_DIR_1_3_OFFSET 0x4 1704 #define IOMUX6_CR_VLT_DIR_1_3_MASK (0x01 << 0x4) 1705 /* */ 1706 #define IOMUX6_CR_SD_LED_OFFSET 0x5 1707 #define IOMUX6_CR_SD_LED_MASK (0x01 << 0x5) 1708 /* */ 1709 #define IOMUX6_CR_SD_VOLT_0_OFFSET 0x6 1710 #define IOMUX6_CR_SD_VOLT_0_MASK (0x01 << 0x6) 1711 /* */ 1712 #define IOMUX6_CR_SD_VOLT_1_OFFSET 0x7 1713 #define IOMUX6_CR_SD_VOLT_1_MASK (0x01 << 0x7) 1714 /* */ 1715 #define IOMUX6_CR_SD_VOLT_2_OFFSET 0x8 1716 #define IOMUX6_CR_SD_VOLT_2_MASK (0x01 << 0x8) 1717 1718 /*Configures the MSSIO block*/ 1719 #define MSSIO_BANK4_CFG_CR_OFFSET 0x230 1720 /* Sets the PCODE value*/ 1721 #define MSSIO_BANK4_CFG_CR_BANK_PCODE_OFFSET 0x0 1722 #define MSSIO_BANK4_CFG_CR_BANK_PCODE_MASK (0x3F << 0x0) 1723 /* Sets the NCODE value*/ 1724 #define MSSIO_BANK4_CFG_CR_BANK_NCODE_OFFSET 0x6 1725 #define MSSIO_BANK4_CFG_CR_BANK_NCODE_MASK (0x3F << 0x6) 1726 /* Sets the voltage controls.*/ 1727 #define MSSIO_BANK4_CFG_CR_VS_OFFSET 0xC 1728 #define MSSIO_BANK4_CFG_CR_VS_MASK (0x0F << 0xC) 1729 1730 /*IO electrical configuration for MSSIO pad*/ 1731 #define MSSIO_BANK4_IO_CFG_0_1_CR_OFFSET 0x234 1732 /* */ 1733 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_0_OFFSET 0x0 1734 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_0_MASK (0x01 << 0x0) 1735 /* */ 1736 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_1_OFFSET 0x1 1737 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_1_MASK (0x01 << 0x1) 1738 /* */ 1739 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_2_OFFSET 0x2 1740 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_2_MASK (0x01 << 0x2) 1741 /* */ 1742 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_0_OFFSET 0x3 1743 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_0_MASK (0x01 << 0x3) 1744 /* */ 1745 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_1_OFFSET 0x4 1746 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_1_MASK (0x01 << 0x4) 1747 /* */ 1748 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_2_OFFSET 0x5 1749 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_2_MASK (0x01 << 0x5) 1750 /* */ 1751 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_3_OFFSET 0x6 1752 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_3_MASK (0x01 << 0x6) 1753 /* */ 1754 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_CLAMP_OFFSET 0x7 1755 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_CLAMP_MASK (0x01 << 0x7) 1756 /* */ 1757 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_ENHYST_OFFSET 0x8 1758 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_ENHYST_MASK (0x01 << 0x8) 1759 /* */ 1760 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LOCKDN_EN_OFFSET 0x9 1761 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LOCKDN_EN_MASK (0x01 << 0x9) 1762 /* */ 1763 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPD_OFFSET 0xA 1764 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPD_MASK (0x01 << 0xA) 1765 /* */ 1766 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPU_OFFSET 0xB 1767 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPU_MASK (0x01 << 0xB) 1768 /* */ 1769 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_ATP_EN_OFFSET 0xC 1770 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_ATP_EN_MASK (0x01 << 0xC) 1771 /* */ 1772 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_PERSIST_EN_OFFSET 0xD 1773 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_PERSIST_EN_MASK (0x01 << 0xD) 1774 /* */ 1775 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_BYPASS_EN_OFFSET 0xE 1776 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_BYPASS_EN_MASK (0x01 << 0xE) 1777 /* */ 1778 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_0_OFFSET 0x10 1779 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_0_MASK (0x01 << 0x10) 1780 /* */ 1781 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_1_OFFSET 0x11 1782 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_1_MASK (0x01 << 0x11) 1783 /* */ 1784 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_2_OFFSET 0x12 1785 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_2_MASK (0x01 << 0x12) 1786 /* */ 1787 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_0_OFFSET 0x13 1788 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_0_MASK (0x01 << 0x13) 1789 /* */ 1790 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_1_OFFSET 0x14 1791 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_1_MASK (0x01 << 0x14) 1792 /* */ 1793 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_2_OFFSET 0x15 1794 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_2_MASK (0x01 << 0x15) 1795 /* */ 1796 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_3_OFFSET 0x16 1797 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_3_MASK (0x01 << 0x16) 1798 /* */ 1799 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_CLAMP_OFFSET 0x17 1800 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_CLAMP_MASK (0x01 << 0x17) 1801 /* */ 1802 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_ENHYST_OFFSET 0x18 1803 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_ENHYST_MASK (0x01 << 0x18) 1804 /* */ 1805 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LOCKDN_EN_OFFSET 0x19 1806 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LOCKDN_EN_MASK (0x01 << 0x19) 1807 /* */ 1808 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPD_OFFSET 0x1A 1809 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPD_MASK (0x01 << 0x1A) 1810 /* */ 1811 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPU_OFFSET 0x1B 1812 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPU_MASK (0x01 << 0x1B) 1813 /* */ 1814 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_ATP_EN_OFFSET 0x1C 1815 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_ATP_EN_MASK (0x01 << 0x1C) 1816 /* */ 1817 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_PERSIST_EN_OFFSET 0x1D 1818 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_PERSIST_EN_MASK (0x01 << 0x1D) 1819 /* */ 1820 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_BYPASS_EN_OFFSET 0x1E 1821 #define MSSIO_BANK4_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_BYPASS_EN_MASK (0x01 << 0x1E) 1822 1823 /*IO electrical configuration for MSSIO pad*/ 1824 #define MSSIO_BANK4_IO_CFG_2_3_CR_OFFSET 0x238 1825 /* */ 1826 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_0_OFFSET 0x0 1827 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_0_MASK (0x01 << 0x0) 1828 /* */ 1829 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_1_OFFSET 0x1 1830 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_1_MASK (0x01 << 0x1) 1831 /* */ 1832 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_2_OFFSET 0x2 1833 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_2_MASK (0x01 << 0x2) 1834 /* */ 1835 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_0_OFFSET 0x3 1836 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_0_MASK (0x01 << 0x3) 1837 /* */ 1838 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_1_OFFSET 0x4 1839 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_1_MASK (0x01 << 0x4) 1840 /* */ 1841 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_2_OFFSET 0x5 1842 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_2_MASK (0x01 << 0x5) 1843 /* */ 1844 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_3_OFFSET 0x6 1845 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_3_MASK (0x01 << 0x6) 1846 /* */ 1847 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_CLAMP_OFFSET 0x7 1848 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_CLAMP_MASK (0x01 << 0x7) 1849 /* */ 1850 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_ENHYST_OFFSET 0x8 1851 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_ENHYST_MASK (0x01 << 0x8) 1852 /* */ 1853 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LOCKDN_EN_OFFSET 0x9 1854 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LOCKDN_EN_MASK (0x01 << 0x9) 1855 /* */ 1856 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPD_OFFSET 0xA 1857 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPD_MASK (0x01 << 0xA) 1858 /* */ 1859 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPU_OFFSET 0xB 1860 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPU_MASK (0x01 << 0xB) 1861 /* */ 1862 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_ATP_EN_OFFSET 0xC 1863 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_ATP_EN_MASK (0x01 << 0xC) 1864 /* */ 1865 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_PERSIST_EN_OFFSET 0xD 1866 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_PERSIST_EN_MASK (0x01 << 0xD) 1867 /* */ 1868 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_BYPASS_EN_OFFSET 0xE 1869 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_BYPASS_EN_MASK (0x01 << 0xE) 1870 /* */ 1871 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_0_OFFSET 0x10 1872 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_0_MASK (0x01 << 0x10) 1873 /* */ 1874 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_1_OFFSET 0x11 1875 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_1_MASK (0x01 << 0x11) 1876 /* */ 1877 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_2_OFFSET 0x12 1878 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_2_MASK (0x01 << 0x12) 1879 /* */ 1880 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_0_OFFSET 0x13 1881 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_0_MASK (0x01 << 0x13) 1882 /* */ 1883 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_1_OFFSET 0x14 1884 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_1_MASK (0x01 << 0x14) 1885 /* */ 1886 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_2_OFFSET 0x15 1887 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_2_MASK (0x01 << 0x15) 1888 /* */ 1889 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_3_OFFSET 0x16 1890 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_3_MASK (0x01 << 0x16) 1891 /* */ 1892 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_CLAMP_OFFSET 0x17 1893 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_CLAMP_MASK (0x01 << 0x17) 1894 /* */ 1895 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_ENHYST_OFFSET 0x18 1896 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_ENHYST_MASK (0x01 << 0x18) 1897 /* */ 1898 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LOCKDN_EN_OFFSET 0x19 1899 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LOCKDN_EN_MASK (0x01 << 0x19) 1900 /* */ 1901 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPD_OFFSET 0x1A 1902 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPD_MASK (0x01 << 0x1A) 1903 /* */ 1904 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPU_OFFSET 0x1B 1905 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPU_MASK (0x01 << 0x1B) 1906 /* */ 1907 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_ATP_EN_OFFSET 0x1C 1908 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_ATP_EN_MASK (0x01 << 0x1C) 1909 /* */ 1910 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_PERSIST_EN_OFFSET 0x1D 1911 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_PERSIST_EN_MASK (0x01 << 0x1D) 1912 /* */ 1913 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_BYPASS_EN_OFFSET 0x1E 1914 #define MSSIO_BANK4_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_BYPASS_EN_MASK (0x01 << 0x1E) 1915 1916 /*IO electrical configuration for MSSIO pad*/ 1917 #define MSSIO_BANK4_IO_CFG_4_5_CR_OFFSET 0x23C 1918 /* */ 1919 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_0_OFFSET 0x0 1920 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_0_MASK (0x01 << 0x0) 1921 /* */ 1922 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_1_OFFSET 0x1 1923 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_1_MASK (0x01 << 0x1) 1924 /* */ 1925 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_2_OFFSET 0x2 1926 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_2_MASK (0x01 << 0x2) 1927 /* */ 1928 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_0_OFFSET 0x3 1929 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_0_MASK (0x01 << 0x3) 1930 /* */ 1931 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_1_OFFSET 0x4 1932 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_1_MASK (0x01 << 0x4) 1933 /* */ 1934 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_2_OFFSET 0x5 1935 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_2_MASK (0x01 << 0x5) 1936 /* */ 1937 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_3_OFFSET 0x6 1938 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_3_MASK (0x01 << 0x6) 1939 /* */ 1940 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_CLAMP_OFFSET 0x7 1941 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_CLAMP_MASK (0x01 << 0x7) 1942 /* */ 1943 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_ENHYST_OFFSET 0x8 1944 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_ENHYST_MASK (0x01 << 0x8) 1945 /* */ 1946 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LOCKDN_EN_OFFSET 0x9 1947 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LOCKDN_EN_MASK (0x01 << 0x9) 1948 /* */ 1949 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPD_OFFSET 0xA 1950 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPD_MASK (0x01 << 0xA) 1951 /* */ 1952 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPU_OFFSET 0xB 1953 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPU_MASK (0x01 << 0xB) 1954 /* */ 1955 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_ATP_EN_OFFSET 0xC 1956 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_ATP_EN_MASK (0x01 << 0xC) 1957 /* */ 1958 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_PERSIST_EN_OFFSET 0xD 1959 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_PERSIST_EN_MASK (0x01 << 0xD) 1960 /* */ 1961 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_BYPASS_EN_OFFSET 0xE 1962 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_BYPASS_EN_MASK (0x01 << 0xE) 1963 /* */ 1964 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_0_OFFSET 0x10 1965 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_0_MASK (0x01 << 0x10) 1966 /* */ 1967 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_1_OFFSET 0x11 1968 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_1_MASK (0x01 << 0x11) 1969 /* */ 1970 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_2_OFFSET 0x12 1971 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_2_MASK (0x01 << 0x12) 1972 /* */ 1973 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_0_OFFSET 0x13 1974 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_0_MASK (0x01 << 0x13) 1975 /* */ 1976 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_1_OFFSET 0x14 1977 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_1_MASK (0x01 << 0x14) 1978 /* */ 1979 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_2_OFFSET 0x15 1980 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_2_MASK (0x01 << 0x15) 1981 /* */ 1982 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_3_OFFSET 0x16 1983 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_3_MASK (0x01 << 0x16) 1984 /* */ 1985 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_CLAMP_OFFSET 0x17 1986 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_CLAMP_MASK (0x01 << 0x17) 1987 /* */ 1988 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_ENHYST_OFFSET 0x18 1989 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_ENHYST_MASK (0x01 << 0x18) 1990 /* */ 1991 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LOCKDN_EN_OFFSET 0x19 1992 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LOCKDN_EN_MASK (0x01 << 0x19) 1993 /* */ 1994 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPD_OFFSET 0x1A 1995 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPD_MASK (0x01 << 0x1A) 1996 /* */ 1997 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPU_OFFSET 0x1B 1998 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPU_MASK (0x01 << 0x1B) 1999 /* */ 2000 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_ATP_EN_OFFSET 0x1C 2001 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_ATP_EN_MASK (0x01 << 0x1C) 2002 /* */ 2003 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_PERSIST_EN_OFFSET 0x1D 2004 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2005 /* */ 2006 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_BYPASS_EN_OFFSET 0x1E 2007 #define MSSIO_BANK4_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2008 2009 /*IO electrical configuration for MSSIO pad*/ 2010 #define MSSIO_BANK4_IO_CFG_6_7_CR_OFFSET 0x240 2011 /* */ 2012 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_0_OFFSET 0x0 2013 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_0_MASK (0x01 << 0x0) 2014 /* */ 2015 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_1_OFFSET 0x1 2016 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_1_MASK (0x01 << 0x1) 2017 /* */ 2018 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_2_OFFSET 0x2 2019 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_2_MASK (0x01 << 0x2) 2020 /* */ 2021 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_0_OFFSET 0x3 2022 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_0_MASK (0x01 << 0x3) 2023 /* */ 2024 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_1_OFFSET 0x4 2025 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_1_MASK (0x01 << 0x4) 2026 /* */ 2027 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_2_OFFSET 0x5 2028 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_2_MASK (0x01 << 0x5) 2029 /* */ 2030 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_3_OFFSET 0x6 2031 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_3_MASK (0x01 << 0x6) 2032 /* */ 2033 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_CLAMP_OFFSET 0x7 2034 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_CLAMP_MASK (0x01 << 0x7) 2035 /* */ 2036 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_ENHYST_OFFSET 0x8 2037 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_ENHYST_MASK (0x01 << 0x8) 2038 /* */ 2039 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LOCKDN_EN_OFFSET 0x9 2040 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LOCKDN_EN_MASK (0x01 << 0x9) 2041 /* */ 2042 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPD_OFFSET 0xA 2043 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPD_MASK (0x01 << 0xA) 2044 /* */ 2045 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPU_OFFSET 0xB 2046 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPU_MASK (0x01 << 0xB) 2047 /* */ 2048 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_ATP_EN_OFFSET 0xC 2049 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_ATP_EN_MASK (0x01 << 0xC) 2050 /* */ 2051 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_PERSIST_EN_OFFSET 0xD 2052 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_PERSIST_EN_MASK (0x01 << 0xD) 2053 /* */ 2054 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_BYPASS_EN_OFFSET 0xE 2055 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_BYPASS_EN_MASK (0x01 << 0xE) 2056 /* */ 2057 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_0_OFFSET 0x10 2058 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_0_MASK (0x01 << 0x10) 2059 /* */ 2060 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_1_OFFSET 0x11 2061 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_1_MASK (0x01 << 0x11) 2062 /* */ 2063 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_2_OFFSET 0x12 2064 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_2_MASK (0x01 << 0x12) 2065 /* */ 2066 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_0_OFFSET 0x13 2067 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_0_MASK (0x01 << 0x13) 2068 /* */ 2069 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_1_OFFSET 0x14 2070 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_1_MASK (0x01 << 0x14) 2071 /* */ 2072 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_2_OFFSET 0x15 2073 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_2_MASK (0x01 << 0x15) 2074 /* */ 2075 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_3_OFFSET 0x16 2076 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_3_MASK (0x01 << 0x16) 2077 /* */ 2078 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_CLAMP_OFFSET 0x17 2079 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_CLAMP_MASK (0x01 << 0x17) 2080 /* */ 2081 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_ENHYST_OFFSET 0x18 2082 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_ENHYST_MASK (0x01 << 0x18) 2083 /* */ 2084 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LOCKDN_EN_OFFSET 0x19 2085 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LOCKDN_EN_MASK (0x01 << 0x19) 2086 /* */ 2087 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPD_OFFSET 0x1A 2088 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPD_MASK (0x01 << 0x1A) 2089 /* */ 2090 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPU_OFFSET 0x1B 2091 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPU_MASK (0x01 << 0x1B) 2092 /* */ 2093 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_ATP_EN_OFFSET 0x1C 2094 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_ATP_EN_MASK (0x01 << 0x1C) 2095 /* */ 2096 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_PERSIST_EN_OFFSET 0x1D 2097 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2098 /* */ 2099 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_BYPASS_EN_OFFSET 0x1E 2100 #define MSSIO_BANK4_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2101 2102 /*IO electrical configuration for MSSIO pad*/ 2103 #define MSSIO_BANK4_IO_CFG_8_9_CR_OFFSET 0x244 2104 /* */ 2105 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_0_OFFSET 0x0 2106 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_0_MASK (0x01 << 0x0) 2107 /* */ 2108 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_1_OFFSET 0x1 2109 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_1_MASK (0x01 << 0x1) 2110 /* */ 2111 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_2_OFFSET 0x2 2112 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_2_MASK (0x01 << 0x2) 2113 /* */ 2114 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_0_OFFSET 0x3 2115 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_0_MASK (0x01 << 0x3) 2116 /* */ 2117 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_1_OFFSET 0x4 2118 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_1_MASK (0x01 << 0x4) 2119 /* */ 2120 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_2_OFFSET 0x5 2121 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_2_MASK (0x01 << 0x5) 2122 /* */ 2123 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_3_OFFSET 0x6 2124 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_3_MASK (0x01 << 0x6) 2125 /* */ 2126 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_CLAMP_OFFSET 0x7 2127 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_CLAMP_MASK (0x01 << 0x7) 2128 /* */ 2129 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_ENHYST_OFFSET 0x8 2130 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_ENHYST_MASK (0x01 << 0x8) 2131 /* */ 2132 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LOCKDN_EN_OFFSET 0x9 2133 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LOCKDN_EN_MASK (0x01 << 0x9) 2134 /* */ 2135 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPD_OFFSET 0xA 2136 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPD_MASK (0x01 << 0xA) 2137 /* */ 2138 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPU_OFFSET 0xB 2139 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPU_MASK (0x01 << 0xB) 2140 /* */ 2141 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_ATP_EN_OFFSET 0xC 2142 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_ATP_EN_MASK (0x01 << 0xC) 2143 /* */ 2144 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_PERSIST_EN_OFFSET 0xD 2145 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_PERSIST_EN_MASK (0x01 << 0xD) 2146 /* */ 2147 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_BYPASS_EN_OFFSET 0xE 2148 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_BYPASS_EN_MASK (0x01 << 0xE) 2149 /* */ 2150 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_0_OFFSET 0x10 2151 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_0_MASK (0x01 << 0x10) 2152 /* */ 2153 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_1_OFFSET 0x11 2154 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_1_MASK (0x01 << 0x11) 2155 /* */ 2156 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_2_OFFSET 0x12 2157 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_2_MASK (0x01 << 0x12) 2158 /* */ 2159 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_0_OFFSET 0x13 2160 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_0_MASK (0x01 << 0x13) 2161 /* */ 2162 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_1_OFFSET 0x14 2163 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_1_MASK (0x01 << 0x14) 2164 /* */ 2165 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_2_OFFSET 0x15 2166 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_2_MASK (0x01 << 0x15) 2167 /* */ 2168 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_3_OFFSET 0x16 2169 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_3_MASK (0x01 << 0x16) 2170 /* */ 2171 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_CLAMP_OFFSET 0x17 2172 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_CLAMP_MASK (0x01 << 0x17) 2173 /* */ 2174 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_ENHYST_OFFSET 0x18 2175 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_ENHYST_MASK (0x01 << 0x18) 2176 /* */ 2177 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LOCKDN_EN_OFFSET 0x19 2178 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LOCKDN_EN_MASK (0x01 << 0x19) 2179 /* */ 2180 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPD_OFFSET 0x1A 2181 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPD_MASK (0x01 << 0x1A) 2182 /* */ 2183 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPU_OFFSET 0x1B 2184 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPU_MASK (0x01 << 0x1B) 2185 /* */ 2186 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_ATP_EN_OFFSET 0x1C 2187 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_ATP_EN_MASK (0x01 << 0x1C) 2188 /* */ 2189 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_PERSIST_EN_OFFSET 0x1D 2190 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2191 /* */ 2192 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_BYPASS_EN_OFFSET 0x1E 2193 #define MSSIO_BANK4_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2194 2195 /*IO electrical configuration for MSSIO pad*/ 2196 #define MSSIO_BANK4_IO_CFG_10_11_CR_OFFSET 0x248 2197 /* */ 2198 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_0_OFFSET 0x0 2199 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_0_MASK (0x01 << 0x0) 2200 /* */ 2201 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_1_OFFSET 0x1 2202 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_1_MASK (0x01 << 0x1) 2203 /* */ 2204 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_2_OFFSET 0x2 2205 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_2_MASK (0x01 << 0x2) 2206 /* */ 2207 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_0_OFFSET 0x3 2208 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_0_MASK (0x01 << 0x3) 2209 /* */ 2210 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_1_OFFSET 0x4 2211 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_1_MASK (0x01 << 0x4) 2212 /* */ 2213 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_2_OFFSET 0x5 2214 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_2_MASK (0x01 << 0x5) 2215 /* */ 2216 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_3_OFFSET 0x6 2217 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_3_MASK (0x01 << 0x6) 2218 /* */ 2219 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_CLAMP_OFFSET 0x7 2220 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_CLAMP_MASK (0x01 << 0x7) 2221 /* */ 2222 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_ENHYST_OFFSET 0x8 2223 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_ENHYST_MASK (0x01 << 0x8) 2224 /* */ 2225 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LOCKDN_EN_OFFSET 0x9 2226 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LOCKDN_EN_MASK (0x01 << 0x9) 2227 /* */ 2228 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPD_OFFSET 0xA 2229 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPD_MASK (0x01 << 0xA) 2230 /* */ 2231 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPU_OFFSET 0xB 2232 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPU_MASK (0x01 << 0xB) 2233 /* */ 2234 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_ATP_EN_OFFSET 0xC 2235 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_ATP_EN_MASK (0x01 << 0xC) 2236 /* */ 2237 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_PERSIST_EN_OFFSET 0xD 2238 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_PERSIST_EN_MASK (0x01 << 0xD) 2239 /* */ 2240 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_BYPASS_EN_OFFSET 0xE 2241 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_BYPASS_EN_MASK (0x01 << 0xE) 2242 /* */ 2243 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_0_OFFSET 0x10 2244 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_0_MASK (0x01 << 0x10) 2245 /* */ 2246 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_1_OFFSET 0x11 2247 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_1_MASK (0x01 << 0x11) 2248 /* */ 2249 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_2_OFFSET 0x12 2250 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_2_MASK (0x01 << 0x12) 2251 /* */ 2252 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_0_OFFSET 0x13 2253 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_0_MASK (0x01 << 0x13) 2254 /* */ 2255 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_1_OFFSET 0x14 2256 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_1_MASK (0x01 << 0x14) 2257 /* */ 2258 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_2_OFFSET 0x15 2259 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_2_MASK (0x01 << 0x15) 2260 /* */ 2261 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_3_OFFSET 0x16 2262 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_3_MASK (0x01 << 0x16) 2263 /* */ 2264 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_CLAMP_OFFSET 0x17 2265 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_CLAMP_MASK (0x01 << 0x17) 2266 /* */ 2267 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_ENHYST_OFFSET 0x18 2268 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_ENHYST_MASK (0x01 << 0x18) 2269 /* */ 2270 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LOCKDN_EN_OFFSET 0x19 2271 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LOCKDN_EN_MASK (0x01 << 0x19) 2272 /* */ 2273 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPD_OFFSET 0x1A 2274 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPD_MASK (0x01 << 0x1A) 2275 /* */ 2276 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPU_OFFSET 0x1B 2277 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPU_MASK (0x01 << 0x1B) 2278 /* */ 2279 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_ATP_EN_OFFSET 0x1C 2280 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_ATP_EN_MASK (0x01 << 0x1C) 2281 /* */ 2282 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_PERSIST_EN_OFFSET 0x1D 2283 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2284 /* */ 2285 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_BYPASS_EN_OFFSET 0x1E 2286 #define MSSIO_BANK4_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2287 2288 /*IO electrical configuration for MSSIO pad*/ 2289 #define MSSIO_BANK4_IO_CFG_12_13_CR_OFFSET 0x24C 2290 /* */ 2291 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_0_OFFSET 0x0 2292 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_0_MASK (0x01 << 0x0) 2293 /* */ 2294 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_1_OFFSET 0x1 2295 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_1_MASK (0x01 << 0x1) 2296 /* */ 2297 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_2_OFFSET 0x2 2298 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_2_MASK (0x01 << 0x2) 2299 /* */ 2300 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_0_OFFSET 0x3 2301 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_0_MASK (0x01 << 0x3) 2302 /* */ 2303 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_1_OFFSET 0x4 2304 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_1_MASK (0x01 << 0x4) 2305 /* */ 2306 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_2_OFFSET 0x5 2307 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_2_MASK (0x01 << 0x5) 2308 /* */ 2309 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_3_OFFSET 0x6 2310 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_3_MASK (0x01 << 0x6) 2311 /* */ 2312 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_CLAMP_OFFSET 0x7 2313 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_CLAMP_MASK (0x01 << 0x7) 2314 /* */ 2315 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_ENHYST_OFFSET 0x8 2316 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_ENHYST_MASK (0x01 << 0x8) 2317 /* */ 2318 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LOCKDN_EN_OFFSET 0x9 2319 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LOCKDN_EN_MASK (0x01 << 0x9) 2320 /* */ 2321 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPD_OFFSET 0xA 2322 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPD_MASK (0x01 << 0xA) 2323 /* */ 2324 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPU_OFFSET 0xB 2325 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPU_MASK (0x01 << 0xB) 2326 /* */ 2327 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_ATP_EN_OFFSET 0xC 2328 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_ATP_EN_MASK (0x01 << 0xC) 2329 /* */ 2330 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_PERSIST_EN_OFFSET 0xD 2331 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_PERSIST_EN_MASK (0x01 << 0xD) 2332 /* */ 2333 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_BYPASS_EN_OFFSET 0xE 2334 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_BYPASS_EN_MASK (0x01 << 0xE) 2335 /* */ 2336 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_0_OFFSET 0x10 2337 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_0_MASK (0x01 << 0x10) 2338 /* */ 2339 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_1_OFFSET 0x11 2340 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_1_MASK (0x01 << 0x11) 2341 /* */ 2342 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_2_OFFSET 0x12 2343 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_2_MASK (0x01 << 0x12) 2344 /* */ 2345 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_0_OFFSET 0x13 2346 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_0_MASK (0x01 << 0x13) 2347 /* */ 2348 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_1_OFFSET 0x14 2349 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_1_MASK (0x01 << 0x14) 2350 /* */ 2351 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_2_OFFSET 0x15 2352 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_2_MASK (0x01 << 0x15) 2353 /* */ 2354 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_3_OFFSET 0x16 2355 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_3_MASK (0x01 << 0x16) 2356 /* */ 2357 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_CLAMP_OFFSET 0x17 2358 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_CLAMP_MASK (0x01 << 0x17) 2359 /* */ 2360 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_ENHYST_OFFSET 0x18 2361 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_ENHYST_MASK (0x01 << 0x18) 2362 /* */ 2363 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LOCKDN_EN_OFFSET 0x19 2364 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LOCKDN_EN_MASK (0x01 << 0x19) 2365 /* */ 2366 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPD_OFFSET 0x1A 2367 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPD_MASK (0x01 << 0x1A) 2368 /* */ 2369 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPU_OFFSET 0x1B 2370 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPU_MASK (0x01 << 0x1B) 2371 /* */ 2372 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_ATP_EN_OFFSET 0x1C 2373 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_ATP_EN_MASK (0x01 << 0x1C) 2374 /* */ 2375 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_PERSIST_EN_OFFSET 0x1D 2376 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2377 /* */ 2378 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_BYPASS_EN_OFFSET 0x1E 2379 #define MSSIO_BANK4_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2380 2381 /*Configures the MSSIO block*/ 2382 #define MSSIO_BANK2_CFG_CR_OFFSET 0x250 2383 /* Sets the PCODE value*/ 2384 #define MSSIO_BANK2_CFG_CR_BANK_PCODE_OFFSET 0x0 2385 #define MSSIO_BANK2_CFG_CR_BANK_PCODE_MASK (0x3F << 0x0) 2386 /* Sets the NCODE value*/ 2387 #define MSSIO_BANK2_CFG_CR_BANK_NCODE_OFFSET 0x6 2388 #define MSSIO_BANK2_CFG_CR_BANK_NCODE_MASK (0x3F << 0x6) 2389 /* Sets the voltage controls.*/ 2390 #define MSSIO_BANK2_CFG_CR_VS_OFFSET 0xC 2391 #define MSSIO_BANK2_CFG_CR_VS_MASK (0x0F << 0xC) 2392 2393 /*IO electrical configuration for MSSIO pad*/ 2394 #define MSSIO_BANK2_IO_CFG_0_1_CR_OFFSET 0x254 2395 /* */ 2396 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_0_OFFSET 0x0 2397 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_0_MASK (0x01 << 0x0) 2398 /* */ 2399 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_1_OFFSET 0x1 2400 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_1_MASK (0x01 << 0x1) 2401 /* */ 2402 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_2_OFFSET 0x2 2403 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_IBUFMD_2_MASK (0x01 << 0x2) 2404 /* */ 2405 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_0_OFFSET 0x3 2406 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_0_MASK (0x01 << 0x3) 2407 /* */ 2408 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_1_OFFSET 0x4 2409 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_1_MASK (0x01 << 0x4) 2410 /* */ 2411 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_2_OFFSET 0x5 2412 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_2_MASK (0x01 << 0x5) 2413 /* */ 2414 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_3_OFFSET 0x6 2415 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_DRV_3_MASK (0x01 << 0x6) 2416 /* */ 2417 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_CLAMP_OFFSET 0x7 2418 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_CLAMP_MASK (0x01 << 0x7) 2419 /* */ 2420 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_ENHYST_OFFSET 0x8 2421 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_ENHYST_MASK (0x01 << 0x8) 2422 /* */ 2423 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LOCKDN_EN_OFFSET 0x9 2424 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LOCKDN_EN_MASK (0x01 << 0x9) 2425 /* */ 2426 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPD_OFFSET 0xA 2427 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPD_MASK (0x01 << 0xA) 2428 /* */ 2429 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPU_OFFSET 0xB 2430 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_WPU_MASK (0x01 << 0xB) 2431 /* */ 2432 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_ATP_EN_OFFSET 0xC 2433 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_ATP_EN_MASK (0x01 << 0xC) 2434 /* */ 2435 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_PERSIST_EN_OFFSET 0xD 2436 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_PERSIST_EN_MASK (0x01 << 0xD) 2437 /* */ 2438 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_BYPASS_EN_OFFSET 0xE 2439 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_0_LP_BYPASS_EN_MASK (0x01 << 0xE) 2440 /* */ 2441 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_0_OFFSET 0x10 2442 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_0_MASK (0x01 << 0x10) 2443 /* */ 2444 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_1_OFFSET 0x11 2445 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_1_MASK (0x01 << 0x11) 2446 /* */ 2447 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_2_OFFSET 0x12 2448 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_IBUFMD_2_MASK (0x01 << 0x12) 2449 /* */ 2450 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_0_OFFSET 0x13 2451 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_0_MASK (0x01 << 0x13) 2452 /* */ 2453 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_1_OFFSET 0x14 2454 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_1_MASK (0x01 << 0x14) 2455 /* */ 2456 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_2_OFFSET 0x15 2457 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_2_MASK (0x01 << 0x15) 2458 /* */ 2459 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_3_OFFSET 0x16 2460 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_DRV_3_MASK (0x01 << 0x16) 2461 /* */ 2462 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_CLAMP_OFFSET 0x17 2463 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_CLAMP_MASK (0x01 << 0x17) 2464 /* */ 2465 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_ENHYST_OFFSET 0x18 2466 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_ENHYST_MASK (0x01 << 0x18) 2467 /* */ 2468 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LOCKDN_EN_OFFSET 0x19 2469 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LOCKDN_EN_MASK (0x01 << 0x19) 2470 /* */ 2471 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPD_OFFSET 0x1A 2472 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPD_MASK (0x01 << 0x1A) 2473 /* */ 2474 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPU_OFFSET 0x1B 2475 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_WPU_MASK (0x01 << 0x1B) 2476 /* */ 2477 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_ATP_EN_OFFSET 0x1C 2478 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_ATP_EN_MASK (0x01 << 0x1C) 2479 /* */ 2480 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_PERSIST_EN_OFFSET 0x1D 2481 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2482 /* */ 2483 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_BYPASS_EN_OFFSET 0x1E 2484 #define MSSIO_BANK2_IO_CFG_0_1_CR_RPC_IO_CFG_1_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2485 2486 /*IO electrical configuration for MSSIO pad*/ 2487 #define MSSIO_BANK2_IO_CFG_2_3_CR_OFFSET 0x258 2488 /* */ 2489 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_0_OFFSET 0x0 2490 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_0_MASK (0x01 << 0x0) 2491 /* */ 2492 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_1_OFFSET 0x1 2493 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_1_MASK (0x01 << 0x1) 2494 /* */ 2495 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_2_OFFSET 0x2 2496 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_IBUFMD_2_MASK (0x01 << 0x2) 2497 /* */ 2498 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_0_OFFSET 0x3 2499 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_0_MASK (0x01 << 0x3) 2500 /* */ 2501 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_1_OFFSET 0x4 2502 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_1_MASK (0x01 << 0x4) 2503 /* */ 2504 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_2_OFFSET 0x5 2505 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_2_MASK (0x01 << 0x5) 2506 /* */ 2507 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_3_OFFSET 0x6 2508 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_DRV_3_MASK (0x01 << 0x6) 2509 /* */ 2510 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_CLAMP_OFFSET 0x7 2511 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_CLAMP_MASK (0x01 << 0x7) 2512 /* */ 2513 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_ENHYST_OFFSET 0x8 2514 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_ENHYST_MASK (0x01 << 0x8) 2515 /* */ 2516 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LOCKDN_EN_OFFSET 0x9 2517 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LOCKDN_EN_MASK (0x01 << 0x9) 2518 /* */ 2519 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPD_OFFSET 0xA 2520 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPD_MASK (0x01 << 0xA) 2521 /* */ 2522 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPU_OFFSET 0xB 2523 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_WPU_MASK (0x01 << 0xB) 2524 /* */ 2525 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_ATP_EN_OFFSET 0xC 2526 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_ATP_EN_MASK (0x01 << 0xC) 2527 /* */ 2528 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_PERSIST_EN_OFFSET 0xD 2529 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_PERSIST_EN_MASK (0x01 << 0xD) 2530 /* */ 2531 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_BYPASS_EN_OFFSET 0xE 2532 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_2_LP_BYPASS_EN_MASK (0x01 << 0xE) 2533 /* */ 2534 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_0_OFFSET 0x10 2535 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_0_MASK (0x01 << 0x10) 2536 /* */ 2537 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_1_OFFSET 0x11 2538 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_1_MASK (0x01 << 0x11) 2539 /* */ 2540 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_2_OFFSET 0x12 2541 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_IBUFMD_2_MASK (0x01 << 0x12) 2542 /* */ 2543 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_0_OFFSET 0x13 2544 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_0_MASK (0x01 << 0x13) 2545 /* */ 2546 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_1_OFFSET 0x14 2547 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_1_MASK (0x01 << 0x14) 2548 /* */ 2549 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_2_OFFSET 0x15 2550 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_2_MASK (0x01 << 0x15) 2551 /* */ 2552 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_3_OFFSET 0x16 2553 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_DRV_3_MASK (0x01 << 0x16) 2554 /* */ 2555 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_CLAMP_OFFSET 0x17 2556 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_CLAMP_MASK (0x01 << 0x17) 2557 /* */ 2558 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_ENHYST_OFFSET 0x18 2559 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_ENHYST_MASK (0x01 << 0x18) 2560 /* */ 2561 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LOCKDN_EN_OFFSET 0x19 2562 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LOCKDN_EN_MASK (0x01 << 0x19) 2563 /* */ 2564 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPD_OFFSET 0x1A 2565 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPD_MASK (0x01 << 0x1A) 2566 /* */ 2567 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPU_OFFSET 0x1B 2568 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_WPU_MASK (0x01 << 0x1B) 2569 /* */ 2570 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_ATP_EN_OFFSET 0x1C 2571 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_ATP_EN_MASK (0x01 << 0x1C) 2572 /* */ 2573 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_PERSIST_EN_OFFSET 0x1D 2574 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2575 /* */ 2576 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_BYPASS_EN_OFFSET 0x1E 2577 #define MSSIO_BANK2_IO_CFG_2_3_CR_RPC_IO_CFG_3_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2578 2579 /*IO electrical configuration for MSSIO pad*/ 2580 #define MSSIO_BANK2_IO_CFG_4_5_CR_OFFSET 0x25C 2581 /* */ 2582 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_0_OFFSET 0x0 2583 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_0_MASK (0x01 << 0x0) 2584 /* */ 2585 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_1_OFFSET 0x1 2586 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_1_MASK (0x01 << 0x1) 2587 /* */ 2588 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_2_OFFSET 0x2 2589 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_IBUFMD_2_MASK (0x01 << 0x2) 2590 /* */ 2591 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_0_OFFSET 0x3 2592 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_0_MASK (0x01 << 0x3) 2593 /* */ 2594 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_1_OFFSET 0x4 2595 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_1_MASK (0x01 << 0x4) 2596 /* */ 2597 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_2_OFFSET 0x5 2598 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_2_MASK (0x01 << 0x5) 2599 /* */ 2600 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_3_OFFSET 0x6 2601 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_DRV_3_MASK (0x01 << 0x6) 2602 /* */ 2603 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_CLAMP_OFFSET 0x7 2604 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_CLAMP_MASK (0x01 << 0x7) 2605 /* */ 2606 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_ENHYST_OFFSET 0x8 2607 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_ENHYST_MASK (0x01 << 0x8) 2608 /* */ 2609 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LOCKDN_EN_OFFSET 0x9 2610 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LOCKDN_EN_MASK (0x01 << 0x9) 2611 /* */ 2612 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPD_OFFSET 0xA 2613 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPD_MASK (0x01 << 0xA) 2614 /* */ 2615 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPU_OFFSET 0xB 2616 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_WPU_MASK (0x01 << 0xB) 2617 /* */ 2618 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_ATP_EN_OFFSET 0xC 2619 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_ATP_EN_MASK (0x01 << 0xC) 2620 /* */ 2621 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_PERSIST_EN_OFFSET 0xD 2622 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_PERSIST_EN_MASK (0x01 << 0xD) 2623 /* */ 2624 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_BYPASS_EN_OFFSET 0xE 2625 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_4_LP_BYPASS_EN_MASK (0x01 << 0xE) 2626 /* */ 2627 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_0_OFFSET 0x10 2628 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_0_MASK (0x01 << 0x10) 2629 /* */ 2630 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_1_OFFSET 0x11 2631 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_1_MASK (0x01 << 0x11) 2632 /* */ 2633 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_2_OFFSET 0x12 2634 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_IBUFMD_2_MASK (0x01 << 0x12) 2635 /* */ 2636 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_0_OFFSET 0x13 2637 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_0_MASK (0x01 << 0x13) 2638 /* */ 2639 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_1_OFFSET 0x14 2640 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_1_MASK (0x01 << 0x14) 2641 /* */ 2642 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_2_OFFSET 0x15 2643 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_2_MASK (0x01 << 0x15) 2644 /* */ 2645 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_3_OFFSET 0x16 2646 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_DRV_3_MASK (0x01 << 0x16) 2647 /* */ 2648 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_CLAMP_OFFSET 0x17 2649 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_CLAMP_MASK (0x01 << 0x17) 2650 /* */ 2651 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_ENHYST_OFFSET 0x18 2652 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_ENHYST_MASK (0x01 << 0x18) 2653 /* */ 2654 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LOCKDN_EN_OFFSET 0x19 2655 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LOCKDN_EN_MASK (0x01 << 0x19) 2656 /* */ 2657 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPD_OFFSET 0x1A 2658 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPD_MASK (0x01 << 0x1A) 2659 /* */ 2660 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPU_OFFSET 0x1B 2661 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_WPU_MASK (0x01 << 0x1B) 2662 /* */ 2663 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_ATP_EN_OFFSET 0x1C 2664 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_ATP_EN_MASK (0x01 << 0x1C) 2665 /* */ 2666 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_PERSIST_EN_OFFSET 0x1D 2667 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2668 /* */ 2669 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_BYPASS_EN_OFFSET 0x1E 2670 #define MSSIO_BANK2_IO_CFG_4_5_CR_RPC_IO_CFG_5_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2671 2672 /*IO electrical configuration for MSSIO pad*/ 2673 #define MSSIO_BANK2_IO_CFG_6_7_CR_OFFSET 0x260 2674 /* */ 2675 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_0_OFFSET 0x0 2676 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_0_MASK (0x01 << 0x0) 2677 /* */ 2678 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_1_OFFSET 0x1 2679 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_1_MASK (0x01 << 0x1) 2680 /* */ 2681 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_2_OFFSET 0x2 2682 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_IBUFMD_2_MASK (0x01 << 0x2) 2683 /* */ 2684 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_0_OFFSET 0x3 2685 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_0_MASK (0x01 << 0x3) 2686 /* */ 2687 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_1_OFFSET 0x4 2688 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_1_MASK (0x01 << 0x4) 2689 /* */ 2690 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_2_OFFSET 0x5 2691 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_2_MASK (0x01 << 0x5) 2692 /* */ 2693 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_3_OFFSET 0x6 2694 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_DRV_3_MASK (0x01 << 0x6) 2695 /* */ 2696 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_CLAMP_OFFSET 0x7 2697 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_CLAMP_MASK (0x01 << 0x7) 2698 /* */ 2699 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_ENHYST_OFFSET 0x8 2700 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_ENHYST_MASK (0x01 << 0x8) 2701 /* */ 2702 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LOCKDN_EN_OFFSET 0x9 2703 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LOCKDN_EN_MASK (0x01 << 0x9) 2704 /* */ 2705 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPD_OFFSET 0xA 2706 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPD_MASK (0x01 << 0xA) 2707 /* */ 2708 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPU_OFFSET 0xB 2709 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_WPU_MASK (0x01 << 0xB) 2710 /* */ 2711 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_ATP_EN_OFFSET 0xC 2712 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_ATP_EN_MASK (0x01 << 0xC) 2713 /* */ 2714 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_PERSIST_EN_OFFSET 0xD 2715 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_PERSIST_EN_MASK (0x01 << 0xD) 2716 /* */ 2717 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_BYPASS_EN_OFFSET 0xE 2718 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_6_LP_BYPASS_EN_MASK (0x01 << 0xE) 2719 /* */ 2720 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_0_OFFSET 0x10 2721 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_0_MASK (0x01 << 0x10) 2722 /* */ 2723 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_1_OFFSET 0x11 2724 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_1_MASK (0x01 << 0x11) 2725 /* */ 2726 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_2_OFFSET 0x12 2727 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_IBUFMD_2_MASK (0x01 << 0x12) 2728 /* */ 2729 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_0_OFFSET 0x13 2730 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_0_MASK (0x01 << 0x13) 2731 /* */ 2732 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_1_OFFSET 0x14 2733 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_1_MASK (0x01 << 0x14) 2734 /* */ 2735 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_2_OFFSET 0x15 2736 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_2_MASK (0x01 << 0x15) 2737 /* */ 2738 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_3_OFFSET 0x16 2739 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_DRV_3_MASK (0x01 << 0x16) 2740 /* */ 2741 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_CLAMP_OFFSET 0x17 2742 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_CLAMP_MASK (0x01 << 0x17) 2743 /* */ 2744 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_ENHYST_OFFSET 0x18 2745 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_ENHYST_MASK (0x01 << 0x18) 2746 /* */ 2747 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LOCKDN_EN_OFFSET 0x19 2748 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LOCKDN_EN_MASK (0x01 << 0x19) 2749 /* */ 2750 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPD_OFFSET 0x1A 2751 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPD_MASK (0x01 << 0x1A) 2752 /* */ 2753 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPU_OFFSET 0x1B 2754 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_WPU_MASK (0x01 << 0x1B) 2755 /* */ 2756 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_ATP_EN_OFFSET 0x1C 2757 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_ATP_EN_MASK (0x01 << 0x1C) 2758 /* */ 2759 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_PERSIST_EN_OFFSET 0x1D 2760 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2761 /* */ 2762 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_BYPASS_EN_OFFSET 0x1E 2763 #define MSSIO_BANK2_IO_CFG_6_7_CR_RPC_IO_CFG_7_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2764 2765 /*IO electrical configuration for MSSIO pad*/ 2766 #define MSSIO_BANK2_IO_CFG_8_9_CR_OFFSET 0x264 2767 /* */ 2768 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_0_OFFSET 0x0 2769 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_0_MASK (0x01 << 0x0) 2770 /* */ 2771 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_1_OFFSET 0x1 2772 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_1_MASK (0x01 << 0x1) 2773 /* */ 2774 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_2_OFFSET 0x2 2775 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_IBUFMD_2_MASK (0x01 << 0x2) 2776 /* */ 2777 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_0_OFFSET 0x3 2778 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_0_MASK (0x01 << 0x3) 2779 /* */ 2780 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_1_OFFSET 0x4 2781 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_1_MASK (0x01 << 0x4) 2782 /* */ 2783 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_2_OFFSET 0x5 2784 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_2_MASK (0x01 << 0x5) 2785 /* */ 2786 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_3_OFFSET 0x6 2787 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_DRV_3_MASK (0x01 << 0x6) 2788 /* */ 2789 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_CLAMP_OFFSET 0x7 2790 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_CLAMP_MASK (0x01 << 0x7) 2791 /* */ 2792 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_ENHYST_OFFSET 0x8 2793 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_ENHYST_MASK (0x01 << 0x8) 2794 /* */ 2795 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LOCKDN_EN_OFFSET 0x9 2796 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LOCKDN_EN_MASK (0x01 << 0x9) 2797 /* */ 2798 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPD_OFFSET 0xA 2799 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPD_MASK (0x01 << 0xA) 2800 /* */ 2801 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPU_OFFSET 0xB 2802 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_WPU_MASK (0x01 << 0xB) 2803 /* */ 2804 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_ATP_EN_OFFSET 0xC 2805 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_ATP_EN_MASK (0x01 << 0xC) 2806 /* */ 2807 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_PERSIST_EN_OFFSET 0xD 2808 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_PERSIST_EN_MASK (0x01 << 0xD) 2809 /* */ 2810 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_BYPASS_EN_OFFSET 0xE 2811 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_8_LP_BYPASS_EN_MASK (0x01 << 0xE) 2812 /* */ 2813 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_0_OFFSET 0x10 2814 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_0_MASK (0x01 << 0x10) 2815 /* */ 2816 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_1_OFFSET 0x11 2817 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_1_MASK (0x01 << 0x11) 2818 /* */ 2819 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_2_OFFSET 0x12 2820 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_IBUFMD_2_MASK (0x01 << 0x12) 2821 /* */ 2822 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_0_OFFSET 0x13 2823 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_0_MASK (0x01 << 0x13) 2824 /* */ 2825 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_1_OFFSET 0x14 2826 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_1_MASK (0x01 << 0x14) 2827 /* */ 2828 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_2_OFFSET 0x15 2829 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_2_MASK (0x01 << 0x15) 2830 /* */ 2831 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_3_OFFSET 0x16 2832 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_DRV_3_MASK (0x01 << 0x16) 2833 /* */ 2834 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_CLAMP_OFFSET 0x17 2835 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_CLAMP_MASK (0x01 << 0x17) 2836 /* */ 2837 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_ENHYST_OFFSET 0x18 2838 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_ENHYST_MASK (0x01 << 0x18) 2839 /* */ 2840 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LOCKDN_EN_OFFSET 0x19 2841 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LOCKDN_EN_MASK (0x01 << 0x19) 2842 /* */ 2843 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPD_OFFSET 0x1A 2844 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPD_MASK (0x01 << 0x1A) 2845 /* */ 2846 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPU_OFFSET 0x1B 2847 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_WPU_MASK (0x01 << 0x1B) 2848 /* */ 2849 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_ATP_EN_OFFSET 0x1C 2850 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_ATP_EN_MASK (0x01 << 0x1C) 2851 /* */ 2852 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_PERSIST_EN_OFFSET 0x1D 2853 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2854 /* */ 2855 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_BYPASS_EN_OFFSET 0x1E 2856 #define MSSIO_BANK2_IO_CFG_8_9_CR_RPC_IO_CFG_9_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2857 2858 /*IO electrical configuration for MSSIO pad*/ 2859 #define MSSIO_BANK2_IO_CFG_10_11_CR_OFFSET 0x268 2860 /* */ 2861 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_0_OFFSET 0x0 2862 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_0_MASK (0x01 << 0x0) 2863 /* */ 2864 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_1_OFFSET 0x1 2865 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_1_MASK (0x01 << 0x1) 2866 /* */ 2867 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_2_OFFSET 0x2 2868 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_IBUFMD_2_MASK (0x01 << 0x2) 2869 /* */ 2870 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_0_OFFSET 0x3 2871 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_0_MASK (0x01 << 0x3) 2872 /* */ 2873 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_1_OFFSET 0x4 2874 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_1_MASK (0x01 << 0x4) 2875 /* */ 2876 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_2_OFFSET 0x5 2877 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_2_MASK (0x01 << 0x5) 2878 /* */ 2879 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_3_OFFSET 0x6 2880 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_DRV_3_MASK (0x01 << 0x6) 2881 /* */ 2882 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_CLAMP_OFFSET 0x7 2883 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_CLAMP_MASK (0x01 << 0x7) 2884 /* */ 2885 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_ENHYST_OFFSET 0x8 2886 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_ENHYST_MASK (0x01 << 0x8) 2887 /* */ 2888 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LOCKDN_EN_OFFSET 0x9 2889 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LOCKDN_EN_MASK (0x01 << 0x9) 2890 /* */ 2891 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPD_OFFSET 0xA 2892 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPD_MASK (0x01 << 0xA) 2893 /* */ 2894 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPU_OFFSET 0xB 2895 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_WPU_MASK (0x01 << 0xB) 2896 /* */ 2897 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_ATP_EN_OFFSET 0xC 2898 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_ATP_EN_MASK (0x01 << 0xC) 2899 /* */ 2900 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_PERSIST_EN_OFFSET 0xD 2901 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_PERSIST_EN_MASK (0x01 << 0xD) 2902 /* */ 2903 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_BYPASS_EN_OFFSET 0xE 2904 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_10_LP_BYPASS_EN_MASK (0x01 << 0xE) 2905 /* */ 2906 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_0_OFFSET 0x10 2907 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_0_MASK (0x01 << 0x10) 2908 /* */ 2909 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_1_OFFSET 0x11 2910 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_1_MASK (0x01 << 0x11) 2911 /* */ 2912 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_2_OFFSET 0x12 2913 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_IBUFMD_2_MASK (0x01 << 0x12) 2914 /* */ 2915 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_0_OFFSET 0x13 2916 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_0_MASK (0x01 << 0x13) 2917 /* */ 2918 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_1_OFFSET 0x14 2919 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_1_MASK (0x01 << 0x14) 2920 /* */ 2921 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_2_OFFSET 0x15 2922 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_2_MASK (0x01 << 0x15) 2923 /* */ 2924 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_3_OFFSET 0x16 2925 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_DRV_3_MASK (0x01 << 0x16) 2926 /* */ 2927 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_CLAMP_OFFSET 0x17 2928 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_CLAMP_MASK (0x01 << 0x17) 2929 /* */ 2930 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_ENHYST_OFFSET 0x18 2931 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_ENHYST_MASK (0x01 << 0x18) 2932 /* */ 2933 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LOCKDN_EN_OFFSET 0x19 2934 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LOCKDN_EN_MASK (0x01 << 0x19) 2935 /* */ 2936 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPD_OFFSET 0x1A 2937 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPD_MASK (0x01 << 0x1A) 2938 /* */ 2939 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPU_OFFSET 0x1B 2940 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_WPU_MASK (0x01 << 0x1B) 2941 /* */ 2942 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_ATP_EN_OFFSET 0x1C 2943 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_ATP_EN_MASK (0x01 << 0x1C) 2944 /* */ 2945 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_PERSIST_EN_OFFSET 0x1D 2946 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_PERSIST_EN_MASK (0x01 << 0x1D) 2947 /* */ 2948 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_BYPASS_EN_OFFSET 0x1E 2949 #define MSSIO_BANK2_IO_CFG_10_11_CR_RPC_IO_CFG_11_LP_BYPASS_EN_MASK (0x01 << 0x1E) 2950 2951 /*IO electrical configuration for MSSIO pad*/ 2952 #define MSSIO_BANK2_IO_CFG_12_13_CR_OFFSET 0x26C 2953 /* */ 2954 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_0_OFFSET 0x0 2955 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_0_MASK (0x01 << 0x0) 2956 /* */ 2957 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_1_OFFSET 0x1 2958 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_1_MASK (0x01 << 0x1) 2959 /* */ 2960 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_2_OFFSET 0x2 2961 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_IBUFMD_2_MASK (0x01 << 0x2) 2962 /* */ 2963 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_0_OFFSET 0x3 2964 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_0_MASK (0x01 << 0x3) 2965 /* */ 2966 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_1_OFFSET 0x4 2967 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_1_MASK (0x01 << 0x4) 2968 /* */ 2969 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_2_OFFSET 0x5 2970 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_2_MASK (0x01 << 0x5) 2971 /* */ 2972 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_3_OFFSET 0x6 2973 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_DRV_3_MASK (0x01 << 0x6) 2974 /* */ 2975 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_CLAMP_OFFSET 0x7 2976 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_CLAMP_MASK (0x01 << 0x7) 2977 /* */ 2978 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_ENHYST_OFFSET 0x8 2979 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_ENHYST_MASK (0x01 << 0x8) 2980 /* */ 2981 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LOCKDN_EN_OFFSET 0x9 2982 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LOCKDN_EN_MASK (0x01 << 0x9) 2983 /* */ 2984 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPD_OFFSET 0xA 2985 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPD_MASK (0x01 << 0xA) 2986 /* */ 2987 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPU_OFFSET 0xB 2988 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_WPU_MASK (0x01 << 0xB) 2989 /* */ 2990 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_ATP_EN_OFFSET 0xC 2991 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_ATP_EN_MASK (0x01 << 0xC) 2992 /* */ 2993 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_PERSIST_EN_OFFSET 0xD 2994 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_PERSIST_EN_MASK (0x01 << 0xD) 2995 /* */ 2996 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_BYPASS_EN_OFFSET 0xE 2997 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_12_LP_BYPASS_EN_MASK (0x01 << 0xE) 2998 /* */ 2999 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_0_OFFSET 0x10 3000 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_0_MASK (0x01 << 0x10) 3001 /* */ 3002 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_1_OFFSET 0x11 3003 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_1_MASK (0x01 << 0x11) 3004 /* */ 3005 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_2_OFFSET 0x12 3006 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_IBUFMD_2_MASK (0x01 << 0x12) 3007 /* */ 3008 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_0_OFFSET 0x13 3009 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_0_MASK (0x01 << 0x13) 3010 /* */ 3011 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_1_OFFSET 0x14 3012 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_1_MASK (0x01 << 0x14) 3013 /* */ 3014 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_2_OFFSET 0x15 3015 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_2_MASK (0x01 << 0x15) 3016 /* */ 3017 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_3_OFFSET 0x16 3018 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_DRV_3_MASK (0x01 << 0x16) 3019 /* */ 3020 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_CLAMP_OFFSET 0x17 3021 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_CLAMP_MASK (0x01 << 0x17) 3022 /* */ 3023 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_ENHYST_OFFSET 0x18 3024 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_ENHYST_MASK (0x01 << 0x18) 3025 /* */ 3026 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LOCKDN_EN_OFFSET 0x19 3027 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LOCKDN_EN_MASK (0x01 << 0x19) 3028 /* */ 3029 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPD_OFFSET 0x1A 3030 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPD_MASK (0x01 << 0x1A) 3031 /* */ 3032 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPU_OFFSET 0x1B 3033 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_WPU_MASK (0x01 << 0x1B) 3034 /* */ 3035 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_ATP_EN_OFFSET 0x1C 3036 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_ATP_EN_MASK (0x01 << 0x1C) 3037 /* */ 3038 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_PERSIST_EN_OFFSET 0x1D 3039 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_PERSIST_EN_MASK (0x01 << 0x1D) 3040 /* */ 3041 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_BYPASS_EN_OFFSET 0x1E 3042 #define MSSIO_BANK2_IO_CFG_12_13_CR_RPC_IO_CFG_13_LP_BYPASS_EN_MASK (0x01 << 0x1E) 3043 3044 /*IO electrical configuration for MSSIO pad*/ 3045 #define MSSIO_BANK2_IO_CFG_14_15_CR_OFFSET 0x270 3046 /* */ 3047 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_0_OFFSET 0x0 3048 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_0_MASK (0x01 << 0x0) 3049 /* */ 3050 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_1_OFFSET 0x1 3051 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_1_MASK (0x01 << 0x1) 3052 /* */ 3053 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_2_OFFSET 0x2 3054 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_IBUFMD_2_MASK (0x01 << 0x2) 3055 /* */ 3056 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_0_OFFSET 0x3 3057 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_0_MASK (0x01 << 0x3) 3058 /* */ 3059 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_1_OFFSET 0x4 3060 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_1_MASK (0x01 << 0x4) 3061 /* */ 3062 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_2_OFFSET 0x5 3063 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_2_MASK (0x01 << 0x5) 3064 /* */ 3065 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_3_OFFSET 0x6 3066 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_DRV_3_MASK (0x01 << 0x6) 3067 /* */ 3068 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_CLAMP_OFFSET 0x7 3069 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_CLAMP_MASK (0x01 << 0x7) 3070 /* */ 3071 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_ENHYST_OFFSET 0x8 3072 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_ENHYST_MASK (0x01 << 0x8) 3073 /* */ 3074 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LOCKDN_EN_OFFSET 0x9 3075 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LOCKDN_EN_MASK (0x01 << 0x9) 3076 /* */ 3077 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_WPD_OFFSET 0xA 3078 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_WPD_MASK (0x01 << 0xA) 3079 /* */ 3080 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_WPU_OFFSET 0xB 3081 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_WPU_MASK (0x01 << 0xB) 3082 /* */ 3083 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_ATP_EN_OFFSET 0xC 3084 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_ATP_EN_MASK (0x01 << 0xC) 3085 /* */ 3086 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LP_PERSIST_EN_OFFSET 0xD 3087 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LP_PERSIST_EN_MASK (0x01 << 0xD) 3088 /* */ 3089 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LP_BYPASS_EN_OFFSET 0xE 3090 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_14_LP_BYPASS_EN_MASK (0x01 << 0xE) 3091 /* */ 3092 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_0_OFFSET 0x10 3093 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_0_MASK (0x01 << 0x10) 3094 /* */ 3095 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_1_OFFSET 0x11 3096 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_1_MASK (0x01 << 0x11) 3097 /* */ 3098 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_2_OFFSET 0x12 3099 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_IBUFMD_2_MASK (0x01 << 0x12) 3100 /* */ 3101 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_0_OFFSET 0x13 3102 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_0_MASK (0x01 << 0x13) 3103 /* */ 3104 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_1_OFFSET 0x14 3105 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_1_MASK (0x01 << 0x14) 3106 /* */ 3107 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_2_OFFSET 0x15 3108 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_2_MASK (0x01 << 0x15) 3109 /* */ 3110 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_3_OFFSET 0x16 3111 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_DRV_3_MASK (0x01 << 0x16) 3112 /* */ 3113 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_CLAMP_OFFSET 0x17 3114 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_CLAMP_MASK (0x01 << 0x17) 3115 /* */ 3116 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_ENHYST_OFFSET 0x18 3117 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_ENHYST_MASK (0x01 << 0x18) 3118 /* */ 3119 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LOCKDN_EN_OFFSET 0x19 3120 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LOCKDN_EN_MASK (0x01 << 0x19) 3121 /* */ 3122 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_WPD_OFFSET 0x1A 3123 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_WPD_MASK (0x01 << 0x1A) 3124 /* */ 3125 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_WPU_OFFSET 0x1B 3126 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_WPU_MASK (0x01 << 0x1B) 3127 /* */ 3128 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_ATP_EN_OFFSET 0x1C 3129 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_ATP_EN_MASK (0x01 << 0x1C) 3130 /* */ 3131 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LP_PERSIST_EN_OFFSET 0x1D 3132 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LP_PERSIST_EN_MASK (0x01 << 0x1D) 3133 /* */ 3134 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LP_BYPASS_EN_OFFSET 0x1E 3135 #define MSSIO_BANK2_IO_CFG_14_15_CR_RPC_IO_CFG_15_LP_BYPASS_EN_MASK (0x01 << 0x1E) 3136 3137 /*IO electrical configuration for MSSIO pad*/ 3138 #define MSSIO_BANK2_IO_CFG_16_17_CR_OFFSET 0x274 3139 /* */ 3140 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_0_OFFSET 0x0 3141 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_0_MASK (0x01 << 0x0) 3142 /* */ 3143 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_1_OFFSET 0x1 3144 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_1_MASK (0x01 << 0x1) 3145 /* */ 3146 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_2_OFFSET 0x2 3147 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_IBUFMD_2_MASK (0x01 << 0x2) 3148 /* */ 3149 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_0_OFFSET 0x3 3150 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_0_MASK (0x01 << 0x3) 3151 /* */ 3152 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_1_OFFSET 0x4 3153 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_1_MASK (0x01 << 0x4) 3154 /* */ 3155 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_2_OFFSET 0x5 3156 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_2_MASK (0x01 << 0x5) 3157 /* */ 3158 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_3_OFFSET 0x6 3159 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_DRV_3_MASK (0x01 << 0x6) 3160 /* */ 3161 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_CLAMP_OFFSET 0x7 3162 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_CLAMP_MASK (0x01 << 0x7) 3163 /* */ 3164 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_ENHYST_OFFSET 0x8 3165 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_ENHYST_MASK (0x01 << 0x8) 3166 /* */ 3167 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LOCKDN_EN_OFFSET 0x9 3168 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LOCKDN_EN_MASK (0x01 << 0x9) 3169 /* */ 3170 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_WPD_OFFSET 0xA 3171 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_WPD_MASK (0x01 << 0xA) 3172 /* */ 3173 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_WPU_OFFSET 0xB 3174 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_WPU_MASK (0x01 << 0xB) 3175 /* */ 3176 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_ATP_EN_OFFSET 0xC 3177 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_ATP_EN_MASK (0x01 << 0xC) 3178 /* */ 3179 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LP_PERSIST_EN_OFFSET 0xD 3180 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LP_PERSIST_EN_MASK (0x01 << 0xD) 3181 /* */ 3182 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LP_BYPASS_EN_OFFSET 0xE 3183 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_16_LP_BYPASS_EN_MASK (0x01 << 0xE) 3184 /* */ 3185 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_0_OFFSET 0x10 3186 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_0_MASK (0x01 << 0x10) 3187 /* */ 3188 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_1_OFFSET 0x11 3189 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_1_MASK (0x01 << 0x11) 3190 /* */ 3191 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_2_OFFSET 0x12 3192 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_IBUFMD_2_MASK (0x01 << 0x12) 3193 /* */ 3194 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_0_OFFSET 0x13 3195 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_0_MASK (0x01 << 0x13) 3196 /* */ 3197 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_1_OFFSET 0x14 3198 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_1_MASK (0x01 << 0x14) 3199 /* */ 3200 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_2_OFFSET 0x15 3201 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_2_MASK (0x01 << 0x15) 3202 /* */ 3203 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_3_OFFSET 0x16 3204 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_DRV_3_MASK (0x01 << 0x16) 3205 /* */ 3206 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_CLAMP_OFFSET 0x17 3207 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_CLAMP_MASK (0x01 << 0x17) 3208 /* */ 3209 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_ENHYST_OFFSET 0x18 3210 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_ENHYST_MASK (0x01 << 0x18) 3211 /* */ 3212 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LOCKDN_EN_OFFSET 0x19 3213 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LOCKDN_EN_MASK (0x01 << 0x19) 3214 /* */ 3215 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_WPD_OFFSET 0x1A 3216 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_WPD_MASK (0x01 << 0x1A) 3217 /* */ 3218 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_WPU_OFFSET 0x1B 3219 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_WPU_MASK (0x01 << 0x1B) 3220 /* */ 3221 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_ATP_EN_OFFSET 0x1C 3222 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_ATP_EN_MASK (0x01 << 0x1C) 3223 /* */ 3224 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LP_PERSIST_EN_OFFSET 0x1D 3225 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LP_PERSIST_EN_MASK (0x01 << 0x1D) 3226 /* */ 3227 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LP_BYPASS_EN_OFFSET 0x1E 3228 #define MSSIO_BANK2_IO_CFG_16_17_CR_RPC_IO_CFG_17_LP_BYPASS_EN_MASK (0x01 << 0x1E) 3229 3230 /*IO electrical configuration for MSSIO pad*/ 3231 #define MSSIO_BANK2_IO_CFG_18_19_CR_OFFSET 0x278 3232 /* */ 3233 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_0_OFFSET 0x0 3234 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_0_MASK (0x01 << 0x0) 3235 /* */ 3236 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_1_OFFSET 0x1 3237 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_1_MASK (0x01 << 0x1) 3238 /* */ 3239 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_2_OFFSET 0x2 3240 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_IBUFMD_2_MASK (0x01 << 0x2) 3241 /* */ 3242 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_0_OFFSET 0x3 3243 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_0_MASK (0x01 << 0x3) 3244 /* */ 3245 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_1_OFFSET 0x4 3246 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_1_MASK (0x01 << 0x4) 3247 /* */ 3248 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_2_OFFSET 0x5 3249 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_2_MASK (0x01 << 0x5) 3250 /* */ 3251 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_3_OFFSET 0x6 3252 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_DRV_3_MASK (0x01 << 0x6) 3253 /* */ 3254 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_CLAMP_OFFSET 0x7 3255 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_CLAMP_MASK (0x01 << 0x7) 3256 /* */ 3257 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_ENHYST_OFFSET 0x8 3258 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_ENHYST_MASK (0x01 << 0x8) 3259 /* */ 3260 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LOCKDN_EN_OFFSET 0x9 3261 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LOCKDN_EN_MASK (0x01 << 0x9) 3262 /* */ 3263 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_WPD_OFFSET 0xA 3264 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_WPD_MASK (0x01 << 0xA) 3265 /* */ 3266 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_WPU_OFFSET 0xB 3267 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_WPU_MASK (0x01 << 0xB) 3268 /* */ 3269 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_ATP_EN_OFFSET 0xC 3270 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_ATP_EN_MASK (0x01 << 0xC) 3271 /* */ 3272 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LP_PERSIST_EN_OFFSET 0xD 3273 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LP_PERSIST_EN_MASK (0x01 << 0xD) 3274 /* */ 3275 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LP_BYPASS_EN_OFFSET 0xE 3276 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_18_LP_BYPASS_EN_MASK (0x01 << 0xE) 3277 /* */ 3278 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_0_OFFSET 0x10 3279 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_0_MASK (0x01 << 0x10) 3280 /* */ 3281 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_1_OFFSET 0x11 3282 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_1_MASK (0x01 << 0x11) 3283 /* */ 3284 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_2_OFFSET 0x12 3285 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_IBUFMD_2_MASK (0x01 << 0x12) 3286 /* */ 3287 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_0_OFFSET 0x13 3288 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_0_MASK (0x01 << 0x13) 3289 /* */ 3290 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_1_OFFSET 0x14 3291 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_1_MASK (0x01 << 0x14) 3292 /* */ 3293 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_2_OFFSET 0x15 3294 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_2_MASK (0x01 << 0x15) 3295 /* */ 3296 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_3_OFFSET 0x16 3297 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_DRV_3_MASK (0x01 << 0x16) 3298 /* */ 3299 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_CLAMP_OFFSET 0x17 3300 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_CLAMP_MASK (0x01 << 0x17) 3301 /* */ 3302 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_ENHYST_OFFSET 0x18 3303 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_ENHYST_MASK (0x01 << 0x18) 3304 /* */ 3305 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LOCKDN_EN_OFFSET 0x19 3306 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LOCKDN_EN_MASK (0x01 << 0x19) 3307 /* */ 3308 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_WPD_OFFSET 0x1A 3309 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_WPD_MASK (0x01 << 0x1A) 3310 /* */ 3311 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_WPU_OFFSET 0x1B 3312 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_WPU_MASK (0x01 << 0x1B) 3313 /* */ 3314 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_ATP_EN_OFFSET 0x1C 3315 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_ATP_EN_MASK (0x01 << 0x1C) 3316 /* */ 3317 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LP_PERSIST_EN_OFFSET 0x1D 3318 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LP_PERSIST_EN_MASK (0x01 << 0x1D) 3319 /* */ 3320 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LP_BYPASS_EN_OFFSET 0x1E 3321 #define MSSIO_BANK2_IO_CFG_18_19_CR_RPC_IO_CFG_19_LP_BYPASS_EN_MASK (0x01 << 0x1E) 3322 3323 /*IO electrical configuration for MSSIO pad*/ 3324 #define MSSIO_BANK2_IO_CFG_20_21_CR_OFFSET 0x27C 3325 /* */ 3326 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_0_OFFSET 0x0 3327 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_0_MASK (0x01 << 0x0) 3328 /* */ 3329 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_1_OFFSET 0x1 3330 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_1_MASK (0x01 << 0x1) 3331 /* */ 3332 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_2_OFFSET 0x2 3333 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_IBUFMD_2_MASK (0x01 << 0x2) 3334 /* */ 3335 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_0_OFFSET 0x3 3336 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_0_MASK (0x01 << 0x3) 3337 /* */ 3338 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_1_OFFSET 0x4 3339 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_1_MASK (0x01 << 0x4) 3340 /* */ 3341 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_2_OFFSET 0x5 3342 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_2_MASK (0x01 << 0x5) 3343 /* */ 3344 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_3_OFFSET 0x6 3345 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_DRV_3_MASK (0x01 << 0x6) 3346 /* */ 3347 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_CLAMP_OFFSET 0x7 3348 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_CLAMP_MASK (0x01 << 0x7) 3349 /* */ 3350 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_ENHYST_OFFSET 0x8 3351 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_ENHYST_MASK (0x01 << 0x8) 3352 /* */ 3353 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LOCKDN_EN_OFFSET 0x9 3354 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LOCKDN_EN_MASK (0x01 << 0x9) 3355 /* */ 3356 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_WPD_OFFSET 0xA 3357 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_WPD_MASK (0x01 << 0xA) 3358 /* */ 3359 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_WPU_OFFSET 0xB 3360 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_WPU_MASK (0x01 << 0xB) 3361 /* */ 3362 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_ATP_EN_OFFSET 0xC 3363 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_ATP_EN_MASK (0x01 << 0xC) 3364 /* */ 3365 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LP_PERSIST_EN_OFFSET 0xD 3366 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LP_PERSIST_EN_MASK (0x01 << 0xD) 3367 /* */ 3368 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LP_BYPASS_EN_OFFSET 0xE 3369 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_20_LP_BYPASS_EN_MASK (0x01 << 0xE) 3370 /* */ 3371 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_0_OFFSET 0x10 3372 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_0_MASK (0x01 << 0x10) 3373 /* */ 3374 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_1_OFFSET 0x11 3375 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_1_MASK (0x01 << 0x11) 3376 /* */ 3377 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_2_OFFSET 0x12 3378 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_IBUFMD_2_MASK (0x01 << 0x12) 3379 /* */ 3380 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_0_OFFSET 0x13 3381 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_0_MASK (0x01 << 0x13) 3382 /* */ 3383 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_1_OFFSET 0x14 3384 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_1_MASK (0x01 << 0x14) 3385 /* */ 3386 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_2_OFFSET 0x15 3387 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_2_MASK (0x01 << 0x15) 3388 /* */ 3389 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_3_OFFSET 0x16 3390 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_DRV_3_MASK (0x01 << 0x16) 3391 /* */ 3392 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_CLAMP_OFFSET 0x17 3393 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_CLAMP_MASK (0x01 << 0x17) 3394 /* */ 3395 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_ENHYST_OFFSET 0x18 3396 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_ENHYST_MASK (0x01 << 0x18) 3397 /* */ 3398 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LOCKDN_EN_OFFSET 0x19 3399 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LOCKDN_EN_MASK (0x01 << 0x19) 3400 /* */ 3401 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_WPD_OFFSET 0x1A 3402 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_WPD_MASK (0x01 << 0x1A) 3403 /* */ 3404 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_WPU_OFFSET 0x1B 3405 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_WPU_MASK (0x01 << 0x1B) 3406 /* */ 3407 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_ATP_EN_OFFSET 0x1C 3408 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_ATP_EN_MASK (0x01 << 0x1C) 3409 /* */ 3410 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LP_PERSIST_EN_OFFSET 0x1D 3411 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LP_PERSIST_EN_MASK (0x01 << 0x1D) 3412 /* */ 3413 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LP_BYPASS_EN_OFFSET 0x1E 3414 #define MSSIO_BANK2_IO_CFG_20_21_CR_RPC_IO_CFG_21_LP_BYPASS_EN_MASK (0x01 << 0x1E) 3415 3416 /*IO electrical configuration for MSSIO pad*/ 3417 #define MSSIO_BANK2_IO_CFG_22_23_CR_OFFSET 0x280 3418 /* */ 3419 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_0_OFFSET 0x0 3420 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_0_MASK (0x01 << 0x0) 3421 /* */ 3422 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_1_OFFSET 0x1 3423 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_1_MASK (0x01 << 0x1) 3424 /* */ 3425 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_2_OFFSET 0x2 3426 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_IBUFMD_2_MASK (0x01 << 0x2) 3427 /* */ 3428 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_0_OFFSET 0x3 3429 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_0_MASK (0x01 << 0x3) 3430 /* */ 3431 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_1_OFFSET 0x4 3432 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_1_MASK (0x01 << 0x4) 3433 /* */ 3434 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_2_OFFSET 0x5 3435 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_2_MASK (0x01 << 0x5) 3436 /* */ 3437 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_3_OFFSET 0x6 3438 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_DRV_3_MASK (0x01 << 0x6) 3439 /* */ 3440 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_CLAMP_OFFSET 0x7 3441 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_CLAMP_MASK (0x01 << 0x7) 3442 /* */ 3443 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_ENHYST_OFFSET 0x8 3444 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_ENHYST_MASK (0x01 << 0x8) 3445 /* */ 3446 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LOCKDN_EN_OFFSET 0x9 3447 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LOCKDN_EN_MASK (0x01 << 0x9) 3448 /* */ 3449 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_WPD_OFFSET 0xA 3450 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_WPD_MASK (0x01 << 0xA) 3451 /* */ 3452 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_WPU_OFFSET 0xB 3453 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_WPU_MASK (0x01 << 0xB) 3454 /* */ 3455 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_ATP_EN_OFFSET 0xC 3456 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_ATP_EN_MASK (0x01 << 0xC) 3457 /* */ 3458 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LP_PERSIST_EN_OFFSET 0xD 3459 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LP_PERSIST_EN_MASK (0x01 << 0xD) 3460 /* */ 3461 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LP_BYPASS_EN_OFFSET 0xE 3462 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_22_LP_BYPASS_EN_MASK (0x01 << 0xE) 3463 /* */ 3464 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_0_OFFSET 0x10 3465 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_0_MASK (0x01 << 0x10) 3466 /* */ 3467 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_1_OFFSET 0x11 3468 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_1_MASK (0x01 << 0x11) 3469 /* */ 3470 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_2_OFFSET 0x12 3471 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_IBUFMD_2_MASK (0x01 << 0x12) 3472 /* */ 3473 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_0_OFFSET 0x13 3474 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_0_MASK (0x01 << 0x13) 3475 /* */ 3476 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_1_OFFSET 0x14 3477 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_1_MASK (0x01 << 0x14) 3478 /* */ 3479 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_2_OFFSET 0x15 3480 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_2_MASK (0x01 << 0x15) 3481 /* */ 3482 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_3_OFFSET 0x16 3483 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_DRV_3_MASK (0x01 << 0x16) 3484 /* */ 3485 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_CLAMP_OFFSET 0x17 3486 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_CLAMP_MASK (0x01 << 0x17) 3487 /* */ 3488 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_ENHYST_OFFSET 0x18 3489 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_ENHYST_MASK (0x01 << 0x18) 3490 /* */ 3491 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LOCKDN_EN_OFFSET 0x19 3492 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LOCKDN_EN_MASK (0x01 << 0x19) 3493 /* */ 3494 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_WPD_OFFSET 0x1A 3495 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_WPD_MASK (0x01 << 0x1A) 3496 /* */ 3497 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_WPU_OFFSET 0x1B 3498 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_WPU_MASK (0x01 << 0x1B) 3499 /* */ 3500 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_ATP_EN_OFFSET 0x1C 3501 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_ATP_EN_MASK (0x01 << 0x1C) 3502 /* */ 3503 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_PERSIST_EN_OFFSET 0x1D 3504 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_PERSIST_EN_MASK (0x01 << 0x1D) 3505 /* */ 3506 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_BYPASS_EN_OFFSET 0x1E 3507 #define MSSIO_BANK2_IO_CFG_22_23_CR_RPC_IO_CFG_23_LP_BYPASS_EN_MASK (0x01 << 0x1E) 3508 3509 /*Sets H2F [31:0] Spares out signals*/ 3510 #define MSS_SPARE0_CR_OFFSET 0x2A8 3511 /* See MSS MAS specification for full description*/ 3512 #define MSS_SPARE0_CR_DATA_OFFSET 0x0 3513 #define MSS_SPARE0_CR_DATA_MASK (0xFFFFFFFF << 0x0) 3514 3515 /*Sets H2F [37:32] Spares out signals*/ 3516 #define MSS_SPARE1_CR_OFFSET 0x2AC 3517 /* See MSS MAS specification for full description*/ 3518 #define MSS_SPARE1_CR_DATA_OFFSET 0x0 3519 #define MSS_SPARE1_CR_DATA_MASK (0x3F << 0x0) 3520 3521 /*Read H2F [31:0] Spares out signals*/ 3522 #define MSS_SPARE0_SR_OFFSET 0x2B0 3523 /* See MSS MAS specification for full description*/ 3524 #define MSS_SPARE0_SR_DATA_OFFSET 0x0 3525 #define MSS_SPARE0_SR_DATA_MASK (0xFFFFFFFF << 0x0) 3526 3527 /*Read H2F [37:32] Spares out signals*/ 3528 #define MSS_SPARE1_SR_OFFSET 0x2B4 3529 /* See MSS MAS specification for full description*/ 3530 #define MSS_SPARE1_SR_DATA_OFFSET 0x0 3531 #define MSS_SPARE1_SR_DATA_MASK (0x3F << 0x0) 3532 3533 /*Read F2H [31:0] Spares in1 signals*/ 3534 #define MSS_SPARE2_SR_OFFSET 0x2B8 3535 /* See MSS MAS specification for full description*/ 3536 #define MSS_SPARE2_SR_DATA_OFFSET 0x0 3537 #define MSS_SPARE2_SR_DATA_MASK (0xFFFFFFFF << 0x0) 3538 3539 /*Read F2H [37:32] Spares in1 signals*/ 3540 #define MSS_SPARE3_SR_OFFSET 0x2BC 3541 /* See MSS MAS specification for full description*/ 3542 #define MSS_SPARE3_SR_DATA_OFFSET 0x0 3543 #define MSS_SPARE3_SR_DATA_MASK (0x3F << 0x0) 3544 3545 /*Read F2H [31:0] Spares in2 signals*/ 3546 #define MSS_SPARE4_SR_OFFSET 0x2C0 3547 /* See MSS MAS specification for full description*/ 3548 #define MSS_SPARE4_SR_DATA_OFFSET 0x0 3549 #define MSS_SPARE4_SR_DATA_MASK (0xFFFFFFFF << 0x0) 3550 3551 /*Read F2H [37:32] Spares in2 signals*/ 3552 #define MSS_SPARE5_SR_OFFSET 0x2C4 3553 /* See MSS MAS specification for full description*/ 3554 #define MSS_SPARE5_SR_DATA_OFFSET 0x0 3555 #define MSS_SPARE5_SR_DATA_MASK (0x3F << 0x0) 3556 3557 /*Register for ECO usage*/ 3558 #define SPARE_REGISTER_RW_OFFSET 0x2D0 3559 /* No function provided for future ECO use*/ 3560 #define SPARE_REGISTER_RW_DATA_OFFSET 0x0 3561 #define SPARE_REGISTER_RW_DATA_MASK (0xFF << 0x0) 3562 3563 /*Register for ECO usage*/ 3564 #define SPARE_REGISTER_W1P_OFFSET 0x2D4 3565 /* No function provided for future ECO use*/ 3566 #define SPARE_REGISTER_W1P_DATA_OFFSET 0x0 3567 #define SPARE_REGISTER_W1P_DATA_MASK (0xFF << 0x0) 3568 3569 /*Register for ECO usage*/ 3570 #define SPARE_REGISTER_RO_OFFSET 0x2D8 3571 /* Provides read-back of { W1P RW } registers. No function provided for 3572 future ECO use.*/ 3573 #define SPARE_REGISTER_RO_DATA_OFFSET 0x0 3574 #define SPARE_REGISTER_RO_DATA_MASK (0xFFFF << 0x0) 3575 3576 /*Spare signal back to G5C*/ 3577 #define SPARE_PERIM_RW_OFFSET 0x2DC 3578 /* Allows the MSS to control the perim_spare_out bits [2] & [6]. No fun 3579 ction provided for future ECO use.*/ 3580 #define SPARE_PERIM_RW_DATA_OFFSET 0x0 3581 #define SPARE_PERIM_RW_DATA_MASK (0x03 << 0x0) 3582 3583 /*Unused FIC resets*/ 3584 #define SPARE_FIC_OFFSET 0x2E0 3585 /* Connected to spare FIC 0-3 Reset inputs to provide simple RO bits. N 3586 o defined use*/ 3587 #define SPARE_FIC_RESET_OFFSET 0x0 3588 #define SPARE_FIC_RESET_MASK (0x0F << 0x0) 3589 /************************************************************************** 3590 ******* 3591 ********************TOP LEVEL REGISTER STRUCTURE*************************** 3592 ******* 3593 *************************************************************************** 3594 *******/ 3595 3596 typedef struct _mss_sysreg 3597 { 3598 /*Register for software use*/ 3599 __IO uint32_t TEMP0; 3600 3601 /*Register for software use*/ 3602 __IO uint32_t TEMP1; 3603 3604 /*Master clock configuration*/ 3605 __IO uint32_t CLOCK_CONFIG_CR; 3606 3607 /*RTC clock divider*/ 3608 __IO uint32_t RTC_CLOCK_CR; 3609 3610 /*Fabric Reset mask*/ 3611 __IO uint32_t FABRIC_RESET_CR; 3612 3613 /**/ 3614 __IO uint32_t BOOT_FAIL_CR; 3615 3616 /* Allows the CPU to fully reset the MSS. 3617 When written to 16'hDEAD will cause a full MSS reset. The Reset wil clear 3618 this register. The register may be writtent to any value but only a value 3619 off 16'hDEAD will cause the reset to happen */ 3620 __IO uint32_t MSS_RESET_CR; 3621 3622 /*Configuration lock*/ 3623 __IO uint32_t CONFIG_LOCK_CR; 3624 3625 /*Indicates which reset caused the last reset. After a reset occurs reg 3626 ister should be read and then zero written to allow the next reset event to 3627 be correctly captured.*/ 3628 __IO uint32_t RESET_SR; 3629 3630 /*Indicates the device status in particular the state of the FPGA fabri 3631 c and the MSS IO banks*/ 3632 __IO uint32_t DEVICE_STATUS ; 3633 3634 /*MSS Build Info*/ 3635 __I uint32_t MSS_BUILD; 3636 3637 /* Padding reserved 32-bit registers.*/ 3638 __I uint32_t RESERVEDREG32B_1; 3639 __I uint32_t RESERVEDREG32B_2; 3640 __I uint32_t RESERVEDREG32B_3; 3641 __I uint32_t RESERVEDREG32B_4; 3642 __I uint32_t RESERVEDREG32B_5; 3643 3644 /*U54-1 Fabric interrupt enable*/ 3645 __IO uint32_t FAB_INTEN_U54_1; 3646 3647 /*U54-2 Fabric interrupt enable*/ 3648 __IO uint32_t FAB_INTEN_U54_2; 3649 3650 /*U54-3 Fabric interrupt enable*/ 3651 __IO uint32_t FAB_INTEN_U54_3; 3652 3653 /*U54-4 Fabric interrupt enable*/ 3654 __IO uint32_t FAB_INTEN_U54_4; 3655 3656 /*Allows the Ethernet interrupts to be directly routed to the U54 CPUS. 3657 */ 3658 __IO uint32_t FAB_INTEN_MISC; 3659 /* Enables the Ethernet MAC0 to interrupt U54_1 directly */ 3660 #define FAB_INTEN_MAC0_U54_1_EN_OFFSET 0x01U 3661 /* Enables the Ethernet MAC0 to interrupt U54_2 directly */ 3662 #define FAB_INTEN_MAC0_U54_2_EN_OFFSET 0x02U 3663 /* Enables the Ethernet MAC1 to interrupt U54_3 directly */ 3664 #define FAB_INTEN_MAC1_U54_3_EN_OFFSET 0x03U 3665 /* Enables the Ethernet MAC1 to interrupt U54_4 directly */ 3666 #define FAB_INTEN_MAC1_U54_4_EN_OFFSET 0x04U 3667 #define FAB_INTEN_MAC0_U54_1_EN_MASK 0x01U 3668 #define FAB_INTEN_MAC0_U54_2_EN_MASK 0x02U 3669 #define FAB_INTEN_MAC1_U54_3_EN_MASK 0x04U 3670 #define FAB_INTEN_MAC1_U54_4_EN_MASK 0x08U 3671 3672 /*Switches GPIO interrupt from PAD to Fabric GPIO*/ 3673 __IO uint32_t GPIO_INTERRUPT_FAB_CR; 3674 3675 /* Padding reserved 32-bit registers.*/ 3676 __I uint32_t RESERVEDREG32B_6; 3677 __I uint32_t RESERVEDREG32B_7; 3678 __I uint32_t RESERVEDREG32B_8; 3679 __I uint32_t RESERVEDREG32B_9; 3680 __I uint32_t RESERVEDREG32B_10; 3681 __I uint32_t RESERVEDREG32B_11; 3682 __I uint32_t RESERVEDREG32B_12; 3683 __I uint32_t RESERVEDREG32B_13; 3684 __I uint32_t RESERVEDREG32B_14; 3685 __I uint32_t RESERVEDREG32B_15; 3686 3687 /*"AMP Mode peripheral mapping register. When the register bit is '0' t 3688 he peripheral is mapped into the 0x2000000 address range using AXI bus 5 fr 3689 om the Coreplex. When the register bit is '1' the peripheral is mapped into 3690 the 0x28000000 address range using AXI bus 6 from the Coreplex."*/ 3691 __IO uint32_t APBBUS_CR; 3692 3693 /*"Enables the clock to the MSS peripheral. By turning clocks off dynam 3694 ic power can be saved. When the clock is off the peripheral should not be 3695 accessed*/ 3696 __IO uint32_t SUBBLK_CLOCK_CR; 3697 3698 /*"Holds the MSS peripherals in reset. When in reset the peripheral sho 3699 uld not be accessed*/ 3700 __IO uint32_t SOFT_RESET_CR; 3701 3702 /*Configures how many outstanding transfers the AXI-AHB bridges in fron 3703 t off the USB and Crypto blocks should allow. (See Synopsys AXI-AHB bridge 3704 documentation)*/ 3705 __IO uint32_t AHBAXI_CR; 3706 3707 /*Configures the two AHB-APB bridges on S5 and S6*/ 3708 __IO uint32_t AHBAPB_CR; 3709 3710 /* Padding reserved 32-bit registers.*/ 3711 uint32_t reservedReg32b_16; 3712 3713 /*MSS Corner APB interface controls*/ 3714 __IO uint32_t DFIAPB_CR; 3715 3716 /*GPIO Blocks reset control*/ 3717 __IO uint32_t GPIO_CR; 3718 3719 /* Padding reserved 32-bit registers.*/ 3720 uint32_t reservedReg32b_17; 3721 3722 /*MAC0 configuration register*/ 3723 __IO uint32_t MAC0_CR; 3724 3725 /*MAC1 configuration register*/ 3726 __IO uint32_t MAC1_CR; 3727 3728 /*USB Configuration register*/ 3729 __IO uint32_t USB_CR; 3730 3731 /*Crypto Mesh control and status register*/ 3732 __IO uint32_t MESH_CR; 3733 3734 /*Crypto mesh seed and update rate*/ 3735 __IO uint32_t MESH_SEED_CR; 3736 3737 /*ENVM AHB Controller setup*/ 3738 __IO uint32_t ENVM_CR; 3739 3740 /*Reserved*/ 3741 __I uint32_t RESERVED_BC; 3742 3743 /*QOS Athena USB & MMC Configuration*/ 3744 __IO uint32_t QOS_PERIPHERAL_CR; 3745 3746 /*QOS Configuration Coreplex*/ 3747 __IO uint32_t QOS_CPLEXIO_CR; 3748 3749 /*QOS configuration DDRC*/ 3750 __IO uint32_t QOS_CPLEXDDR_CR; 3751 3752 /* Padding reserved 32-bit registers.*/ 3753 __I uint32_t RESERVEDREG32B_18; 3754 __I uint32_t RESERVEDREG32B_19; 3755 __I uint32_t RESERVEDREG32B_20; 3756 __I uint32_t RESERVEDREG32B_21; 3757 __I uint32_t RESERVEDREG32B_22; 3758 __I uint32_t RESERVEDREG32B_23; 3759 __I uint32_t RESERVEDREG32B_24; 3760 __I uint32_t RESERVEDREG32B_25; 3761 __I uint32_t RESERVEDREG32B_26; 3762 3763 /*Indicates that a master caused a MPU violation. Interrupts via mainte 3764 nance interrupt.*/ 3765 __IO uint32_t MPU_VIOLATION_SR; 3766 3767 /*Enables interrupts on MPU violations*/ 3768 __IO uint32_t MPU_VIOLATION_INTEN_CR; 3769 3770 /*AXI switch decode fail*/ 3771 __IO uint32_t SW_FAIL_ADDR0_CR; 3772 3773 /*AXI switch decode fail*/ 3774 __IO uint32_t SW_FAIL_ADDR1_CR; 3775 3776 /*Set when an ECC event happens*/ 3777 __IO uint32_t EDAC_SR; 3778 3779 /*Enables ECC interrupt on event*/ 3780 __IO uint32_t EDAC_INTEN_CR; 3781 3782 /*Count off single bit errors*/ 3783 __IO uint32_t EDAC_CNT_MMC; 3784 3785 /*Count off single bit errors*/ 3786 __IO uint32_t EDAC_CNT_DDRC; 3787 3788 /*Count off single bit errors*/ 3789 __IO uint32_t EDAC_CNT_MAC0; 3790 3791 /*Count off single bit errors*/ 3792 __IO uint32_t EDAC_CNT_MAC1; 3793 3794 /*Count off single bit errors*/ 3795 __IO uint32_t EDAC_CNT_USB; 3796 3797 /*Count off single bit errors*/ 3798 __IO uint32_t EDAC_CNT_CAN0; 3799 3800 /*Count off single bit errors*/ 3801 __IO uint32_t EDAC_CNT_CAN1; 3802 3803 /*"Will Corrupt write data to rams 1E corrupts bit 0 2E bits 1 and 2.In 3804 jects Errors into all RAMS in the block as long as the bits are set. Settin 3805 g 1E and 2E will inject a 3-bit error"*/ 3806 __IO uint32_t EDAC_INJECT_CR; 3807 3808 /* Padding reserved 32-bit registers.*/ 3809 __I uint32_t RESERVEDREG32B_27; 3810 __I uint32_t RESERVEDREG32B_28; 3811 __I uint32_t RESERVEDREG32B_29; 3812 __I uint32_t RESERVEDREG32B_30; 3813 __I uint32_t RESERVEDREG32B_31; 3814 __I uint32_t RESERVEDREG32B_32; 3815 3816 /*Maintenance Interrupt Enable.*/ 3817 __IO uint32_t MAINTENANCE_INTEN_CR; 3818 3819 /*PLL Status interrupt enables*/ 3820 __IO uint32_t PLL_STATUS_INTEN_CR; 3821 3822 /*Maintenance interrupt indicates fault and status events.*/ 3823 __IO uint32_t MAINTENANCE_INT_SR; 3824 3825 /*PLL interrupt register*/ 3826 __IO uint32_t PLL_STATUS_SR; 3827 3828 /*Enable to CFM Timer */ 3829 __IO uint32_t CFM_TIMER_CR; 3830 3831 /*Miscellaneous Register*/ 3832 uint32_t MISC_SR; 3833 3834 /*DLL Interrupt enables*/ 3835 __IO uint32_t DLL_STATUS_CR; 3836 3837 /*DLL interrupt register*/ 3838 __IO uint32_t DLL_STATUS_SR; 3839 3840 /* Padding reserved 32-bit registers.*/ 3841 __I uint32_t RESERVEDREG32B_33; 3842 __I uint32_t RESERVEDREG32B_34; 3843 3844 /*Puts all the RAMS in that block into low leakage mode. RAM contents a 3845 nd Q value preserved.*/ 3846 __IO uint32_t RAM_LIGHTSLEEP_CR; 3847 3848 /*Puts all the RAMS in that block into deep sleep mode. RAM contents pr 3849 eserved. Powers down the periphery circuits.*/ 3850 __IO uint32_t RAM_DEEPSLEEP_CR; 3851 3852 /*Puts all the RAMS in that block into shut down mode. RAM contents not 3853 preserved. Powers down the RAM and periphery circuits.*/ 3854 __IO uint32_t RAM_SHUTDOWN_CR; 3855 3856 /*Allows each bank of the L2 Cache to be powered down ORed with global 3857 shutdown */ 3858 __IO uint32_t L2_SHUTDOWN_CR; 3859 3860 /* Padding reserved 32-bit registers.*/ 3861 __I uint32_t RESERVEDREG32B_35; 3862 __I uint32_t RESERVEDREG32B_36; 3863 __I uint32_t RESERVEDREG32B_37; 3864 __I uint32_t RESERVEDREG32B_38; 3865 __I uint32_t RESERVEDREG32B_39; 3866 __I uint32_t RESERVEDREG32B_40; 3867 __I uint32_t RESERVEDREG32B_41; 3868 __I uint32_t RESERVEDREG32B_42; 3869 __I uint32_t RESERVEDREG32B_43; 3870 __I uint32_t RESERVEDREG32B_44; 3871 __I uint32_t RESERVEDREG32B_45; 3872 __I uint32_t RESERVEDREG32B_46; 3873 __I uint32_t RESERVEDREG32B_47; 3874 __I uint32_t RESERVEDREG32B_48; 3875 __I uint32_t RESERVEDREG32B_49; 3876 __I uint32_t RESERVEDREG32B_50; 3877 __I uint32_t RESERVEDREG32B_51; 3878 __I uint32_t RESERVEDREG32B_52; 3879 __I uint32_t RESERVEDREG32B_53; 3880 __I uint32_t RESERVEDREG32B_54; 3881 __I uint32_t RESERVEDREG32B_55; 3882 __I uint32_t RESERVEDREG32B_56; 3883 __I uint32_t RESERVEDREG32B_57; 3884 __I uint32_t RESERVEDREG32B_58; 3885 __I uint32_t RESERVEDREG32B_59; 3886 __I uint32_t RESERVEDREG32B_60; 3887 __I uint32_t RESERVEDREG32B_61; 3888 __I uint32_t RESERVEDREG32B_62; 3889 __I uint32_t RESERVEDREG32B_63; 3890 __I uint32_t RESERVEDREG32B_64; 3891 __I uint32_t RESERVEDREG32B_65; 3892 __I uint32_t RESERVEDREG32B_66; 3893 __I uint32_t RESERVEDREG32B_67; 3894 __I uint32_t RESERVEDREG32B_68; 3895 3896 /*Selects whether the peripheral is connected to the Fabric or IOMUX st 3897 ructure.*/ 3898 __IO uint32_t IOMUX0_CR; 3899 3900 /*Configures the IO Mux structure for each IO pad. See the MSS MAS spec 3901 ification for for description.*/ 3902 __IO uint32_t IOMUX1_CR; 3903 3904 /*Configures the IO Mux structure for each IO pad. See the MSS MAS spec 3905 ification for for description.*/ 3906 __IO uint32_t IOMUX2_CR; 3907 3908 /*Configures the IO Mux structure for each IO pad. See the MSS MAS spec 3909 ification for for description.*/ 3910 __IO uint32_t IOMUX3_CR; 3911 3912 /*Configures the IO Mux structure for each IO pad. See the MSS MAS spec 3913 ification for for description.*/ 3914 __IO uint32_t IOMUX4_CR; 3915 3916 /*Configures the IO Mux structure for each IO pad. See the MSS MAS spec 3917 ification for for description.*/ 3918 __IO uint32_t IOMUX5_CR; 3919 3920 /*Sets whether the MMC/SD Voltage select lines are inverted on entry to 3921 the IOMUX structure*/ 3922 __IO uint32_t IOMUX6_CR; 3923 3924 /* Padding reserved 32-bit registers.*/ 3925 __I uint32_t RESERVEDREG32B_69; 3926 __I uint32_t RESERVEDREG32B_70; 3927 __I uint32_t RESERVEDREG32B_71; 3928 __I uint32_t RESERVEDREG32B_72; 3929 __I uint32_t RESERVEDREG32B_73; 3930 3931 /*Configures the MSSIO block*/ 3932 __IO uint32_t MSSIO_BANK4_CFG_CR; 3933 3934 /*IO electrical configuration for MSSIO pad*/ 3935 __IO uint32_t MSSIO_BANK4_IO_CFG_0_1_CR; 3936 3937 /*IO electrical configuration for MSSIO pad*/ 3938 __IO uint32_t MSSIO_BANK4_IO_CFG_2_3_CR; 3939 3940 /*IO electrical configuration for MSSIO pad*/ 3941 __IO uint32_t MSSIO_BANK4_IO_CFG_4_5_CR; 3942 3943 /*IO electrical configuration for MSSIO pad*/ 3944 __IO uint32_t MSSIO_BANK4_IO_CFG_6_7_CR; 3945 3946 /*IO electrical configuration for MSSIO pad*/ 3947 __IO uint32_t MSSIO_BANK4_IO_CFG_8_9_CR; 3948 3949 /*IO electrical configuration for MSSIO pad*/ 3950 __IO uint32_t MSSIO_BANK4_IO_CFG_10_11_CR; 3951 3952 /*IO electrical configuration for MSSIO pad*/ 3953 __IO uint32_t MSSIO_BANK4_IO_CFG_12_13_CR; 3954 3955 /*Configures the MSSIO block*/ 3956 __IO uint32_t MSSIO_BANK2_CFG_CR; 3957 3958 /*IO electrical configuration for MSSIO pad*/ 3959 __IO uint32_t MSSIO_BANK2_IO_CFG_0_1_CR; 3960 3961 /*IO electrical configuration for MSSIO pad*/ 3962 __IO uint32_t MSSIO_BANK2_IO_CFG_2_3_CR; 3963 3964 /*IO electrical configuration for MSSIO pad*/ 3965 __IO uint32_t MSSIO_BANK2_IO_CFG_4_5_CR; 3966 3967 /*IO electrical configuration for MSSIO pad*/ 3968 __IO uint32_t MSSIO_BANK2_IO_CFG_6_7_CR; 3969 3970 /*IO electrical configuration for MSSIO pad*/ 3971 __IO uint32_t MSSIO_BANK2_IO_CFG_8_9_CR; 3972 3973 /*IO electrical configuration for MSSIO pad*/ 3974 __IO uint32_t MSSIO_BANK2_IO_CFG_10_11_CR; 3975 3976 /*IO electrical configuration for MSSIO pad*/ 3977 __IO uint32_t MSSIO_BANK2_IO_CFG_12_13_CR; 3978 3979 /*IO electrical configuration for MSSIO pad*/ 3980 __IO uint32_t MSSIO_BANK2_IO_CFG_14_15_CR; 3981 3982 /*IO electrical configuration for MSSIO pad*/ 3983 __IO uint32_t MSSIO_BANK2_IO_CFG_16_17_CR; 3984 3985 /*IO electrical configuration for MSSIO pad*/ 3986 __IO uint32_t MSSIO_BANK2_IO_CFG_18_19_CR; 3987 3988 /*IO electrical configuration for MSSIO pad*/ 3989 __IO uint32_t MSSIO_BANK2_IO_CFG_20_21_CR; 3990 3991 /*IO electrical configuration for MSSIO pad*/ 3992 __IO uint32_t MSSIO_BANK2_IO_CFG_22_23_CR; 3993 3994 /* Padding reserved 32-bit registers.*/ 3995 __I uint32_t RESERVEDREG32B_74; 3996 __I uint32_t RESERVEDREG32B_75; 3997 __I uint32_t RESERVEDREG32B_76; 3998 __I uint32_t RESERVEDREG32B_77; 3999 __I uint32_t RESERVEDREG32B_78; 4000 __I uint32_t RESERVEDREG32B_79; 4001 __I uint32_t RESERVEDREG32B_80; 4002 __I uint32_t RESERVEDREG32B_81; 4003 __I uint32_t RESERVEDREG32B_82; 4004 4005 /*Sets H2F [31:0] Spares out signals*/ 4006 __IO uint32_t MSS_SPARE0_CR; 4007 4008 /*Sets H2F [37:32] Spares out signals*/ 4009 __IO uint32_t MSS_SPARE1_CR; 4010 4011 /*Read H2F [31:0] Spares out signals*/ 4012 __IO uint32_t MSS_SPARE0_SR; 4013 4014 /*Read H2F [37:32] Spares out signals*/ 4015 __IO uint32_t MSS_SPARE1_SR; 4016 4017 /*Read F2H [31:0] Spares in1 signals*/ 4018 __IO uint32_t MSS_SPARE2_SR; 4019 4020 /*Read F2H [37:32] Spares in1 signals*/ 4021 __IO uint32_t MSS_SPARE3_SR; 4022 4023 /*Read F2H [31:0] Spares in2 signals*/ 4024 __IO uint32_t MSS_SPARE4_SR; 4025 4026 /*Read F2H [37:32] Spares in2 signals*/ 4027 __IO uint32_t MSS_SPARE5_SR; 4028 4029 /* Padding reserved 32-bit registers.*/ 4030 __I uint32_t RESERVEDREG32B_83; 4031 __I uint32_t RESERVEDREG32B_84; 4032 4033 /*Register for ECO usage*/ 4034 __IO uint32_t SPARE_REGISTER_RW; 4035 4036 /*Register for ECO usage*/ 4037 __IO uint32_t SPARE_REGISTER_W1P; 4038 4039 /*Register for ECO usage*/ 4040 __I uint32_t SPARE_REGISTER_RO; 4041 4042 /*Spare signal back to G5C*/ 4043 __IO uint32_t SPARE_PERIM_RW; 4044 4045 /*Unused FIC resets*/ 4046 __I uint32_t SPARE_FIC; 4047 } mss_sysreg_t; 4048 4049 #define SYSREG_ATHENACR_RESET (1U << 0U) 4050 #define SYSREG_ATHENACR_PURGE (1U << 1U) 4051 #define SYSREG_ATHENACR_GO (1U << 2U) 4052 #define SYSREG_ATHENACR_RINGOSCON (1U << 3U) 4053 #define SYSREG_ATHENACR_COMPLETE (1U << 8U) 4054 #define SYSREG_ATHENACR_ALARM (1U << 9U) 4055 #define SYSREG_ATHENACR_BUSERROR (1U << 10U) 4056 #define SYSREG_SOFTRESET_ENVM (1U << 0U) 4057 #define SYSREG_SOFTRESET_TIMER (1U << 4U) 4058 #define SYSREG_SOFTRESET_MMUART0 (1U << 5U) 4059 #define SYSREG_SOFTRESET_DDRC (1U << 23U) 4060 #define SYSREG_SOFTRESET_FIC3 (1U << 27U) 4061 #define SYSREG_SOFTRESET_ATHENA (1U << 28U) 4062 4063 #define SYSREG ((volatile mss_sysreg_t * const) BASE32_ADDR_MSS_SYSREG) 4064 4065 #ifdef __cplusplus 4066 } 4067 #endif 4068 4069 #endif /*MSS_SYSREG_H*/ 4070
