1 /* 2 * Copyright (c) 2024 Microchip Technology Inc. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 */ 6 #ifndef _MEC5_BTMR_V1_H 7 #define _MEC5_BTMR_V1_H 8 9 /** @addtogroup Device_Peripheral_peripherals 10 * @{ 11 */ 12 13 /** 14 * @brief Basic Timer: Instances 0-3 16-bit, 4-5 32-bit (MEC_BTMR0) 15 */ 16 17 typedef struct mec_btmr_regs { /*!< (@ 0x40000C00) MEC_BTMR0 Structure */ 18 __IOM uint32_t COUNT; /*!< (@ 0x00000000) Basic timer counter register */ 19 __IOM uint32_t PRELOAD; /*!< (@ 0x00000004) 16-bit Basic timer preload value */ 20 __IOM uint32_t STATUS; /*!< (@ 0x00000008) Basic timer status */ 21 __IOM uint32_t IEN; /*!< (@ 0x0000000C) Basic timer interrupt enable */ 22 __IOM uint32_t CTRL; /*!< (@ 0x00000010) Basic timer control */ 23 } MEC_BTMR_Type; /*!< Size = 20 (0x14) */ 24 25 /** @} */ /* End of group Device_Peripheral_peripherals */ 26 27 /** @addtogroup PosMask_peripherals 28 * @{ 29 */ 30 /* ========================================================= COUNT ========================================================= */ 31 /* ======================================================== PRELOAD ======================================================== */ 32 /* ======================================================== STATUS ========================================================= */ 33 #define MEC_BTMR_STATUS_EVENT_Pos (0UL) /*!< EVENT (Bit 0) */ 34 #define MEC_BTMR_STATUS_EVENT_Msk (0x1UL) /*!< EVENT (Bitfield-Mask: 0x01) */ 35 /* ========================================================== IEN ========================================================== */ 36 #define MEC_BTMR_IEN_EVENT_Pos (0UL) /*!< EVENT (Bit 0) */ 37 #define MEC_BTMR_IEN_EVENT_Msk (0x1UL) /*!< EVENT (Bitfield-Mask: 0x01) */ 38 /* ========================================================= CTRL ========================================================== */ 39 #define MEC_BTMR_CTRL_ENABLE_Pos (0UL) /*!< ENABLE (Bit 0) */ 40 #define MEC_BTMR_CTRL_ENABLE_Msk (0x1UL) /*!< ENABLE (Bitfield-Mask: 0x01) */ 41 #define MEC_BTMR_CTRL_CNT_DIR_Pos (2UL) /*!< CNT_DIR (Bit 2) */ 42 #define MEC_BTMR_CTRL_CNT_DIR_Msk (0x4UL) /*!< CNT_DIR (Bitfield-Mask: 0x01) */ 43 #define MEC_BTMR_CTRL_RESTART_Pos (3UL) /*!< RESTART (Bit 3) */ 44 #define MEC_BTMR_CTRL_RESTART_Msk (0x8UL) /*!< RESTART (Bitfield-Mask: 0x01) */ 45 #define MEC_BTMR_CTRL_RESET_Pos (4UL) /*!< RESET (Bit 4) */ 46 #define MEC_BTMR_CTRL_RESET_Msk (0x10UL) /*!< RESET (Bitfield-Mask: 0x01) */ 47 #define MEC_BTMR_CTRL_START_Pos (5UL) /*!< START (Bit 5) */ 48 #define MEC_BTMR_CTRL_START_Msk (0x20UL) /*!< START (Bitfield-Mask: 0x01) */ 49 #define MEC_BTMR_CTRL_RELOAD_Pos (6UL) /*!< RELOAD (Bit 6) */ 50 #define MEC_BTMR_CTRL_RELOAD_Msk (0x40UL) /*!< RELOAD (Bitfield-Mask: 0x01) */ 51 #define MEC_BTMR_CTRL_HALT_Pos (7UL) /*!< HALT (Bit 7) */ 52 #define MEC_BTMR_CTRL_HALT_Msk (0x80UL) /*!< HALT (Bitfield-Mask: 0x01) */ 53 #define MEC_BTMR_CTRL_PRESCALE_Pos (16UL) /*!< PRESCALE (Bit 16) */ 54 #define MEC_BTMR_CTRL_PRESCALE_Msk (0xffff0000UL) /*!< PRESCALE (Bitfield-Mask: 0xffff) */ 55 56 /** @} */ /* End of group PosMask_peripherals */ 57 58 /** @addtogroup EnumValue_peripherals 59 * @{ 60 */ 61 /* ========================================================= COUNT ========================================================= */ 62 /* ======================================================== PRELOAD ======================================================== */ 63 /* ======================================================== STATUS ========================================================= */ 64 /* ============================================= MEC_BTMR STATUS EVENT [0..0] ============================================= */ 65 typedef enum { /*!< MEC_BTMR_STATUS_EVENT */ 66 MEC_BTMR_STATUS_EVENT_nACTIVE = 0, /*!< nACTIVE : Basic Timer interrupt event not active */ 67 MEC_BTMR_STATUS_EVENT_ACTIVE = 1, /*!< ACTIVE : Basic Timer interrupt event active */ 68 } MEC_BTMR_STATUS_EVENT_Enum; 69 70 /* ========================================================== IEN ========================================================== */ 71 /* ============================================== MEC_BTMR IEN EVENT [0..0] =============================================== */ 72 typedef enum { /*!< MEC_BTMR_IEN_EVENT */ 73 MEC_BTMR_IEN_EVENT_DIS = 0, /*!< DIS : Disable interrupt generation for Basic Timer interrupt 74 event */ 75 MEC_BTMR_IEN_EVENT_EN = 1, /*!< EN : Disable interrupt generation for Basic Timer interrupt 76 event */ 77 } MEC_BTMR_IEN_EVENT_Enum; 78 79 /* ========================================================= CTRL ========================================================== */ 80 /* ============================================= MEC_BTMR CTRL ENABLE [0..0] ============================================== */ 81 typedef enum { /*!< MEC_BTMR_CTRL_ENABLE */ 82 MEC_BTMR_CTRL_ENABLE_OFF = 0, /*!< OFF : Basic Timer peripheral block is off (clocks gated) */ 83 MEC_BTMR_CTRL_ENABLE_ON = 1, /*!< ON : Basic Timer peripheral block is on (clocks ungated) */ 84 } MEC_BTMR_CTRL_ENABLE_Enum; 85 86 /* ============================================= MEC_BTMR CTRL CNT_DIR [2..2] ============================================= */ 87 typedef enum { /*!< MEC_BTMR_CTRL_CNT_DIR */ 88 MEC_BTMR_CTRL_CNT_DIR_DOWN = 0, /*!< DOWN : Basic Timer counts down from preload value to 0 */ 89 MEC_BTMR_CTRL_CNT_DIR_UP = 1, /*!< UP : Basic Timer counts up from preload value to maximum */ 90 } MEC_BTMR_CTRL_CNT_DIR_Enum; 91 92 /* ============================================= MEC_BTMR CTRL RESTART [3..3] ============================================= */ 93 typedef enum { /*!< MEC_BTMR_CTRL_RESTART */ 94 MEC_BTMR_CTRL_RESTART_DIS = 0, /*!< DIS : One shot mode. Do not reload counter from preload register */ 95 MEC_BTMR_CTRL_RESTART_EN = 1, /*!< EN : Reload counter from preload register when counter reaches 96 limit */ 97 } MEC_BTMR_CTRL_RESTART_Enum; 98 99 /* ============================================== MEC_BTMR CTRL RESET [4..4] ============================================== */ 100 typedef enum { /*!< MEC_BTMR_CTRL_RESET */ 101 MEC_BTMR_CTRL_RESET_DIS = 0, /*!< DIS : No soft-reset */ 102 MEC_BTMR_CTRL_RESET_EN = 1, /*!< EN : Trigger Basic Timer soft-reset. Bit is self-clearing after 103 one AHB clock */ 104 } MEC_BTMR_CTRL_RESET_Enum; 105 106 /* ============================================== MEC_BTMR CTRL START [5..5] ============================================== */ 107 typedef enum { /*!< MEC_BTMR_CTRL_START */ 108 MEC_BTMR_CTRL_START_OFF = 0, /*!< OFF : Stop timer current operation */ 109 MEC_BTMR_CTRL_START_ON = 1, /*!< ON : Start configured timer operation */ 110 } MEC_BTMR_CTRL_START_Enum; 111 112 /* ============================================= MEC_BTMR CTRL RELOAD [6..6] ============================================== */ 113 typedef enum { /*!< MEC_BTMR_CTRL_RELOAD */ 114 MEC_BTMR_CTRL_RELOAD_NOW = 1, /*!< NOW : When written to 1 reload counter from preload register */ 115 } MEC_BTMR_CTRL_RELOAD_Enum; 116 117 /* ============================================== MEC_BTMR CTRL HALT [7..7] =============================================== */ 118 typedef enum { /*!< MEC_BTMR_CTRL_HALT */ 119 MEC_BTMR_CTRL_HALT_OFF = 0, /*!< OFF : Unhalt timer count */ 120 MEC_BTMR_CTRL_HALT_ON = 1, /*!< ON : Halt timer count */ 121 } MEC_BTMR_CTRL_HALT_Enum; 122 123 /** @} */ /* End of group EnumValue_peripherals */ 124 125 #endif /* _MEC5_BTMR_V1_H */ 126
