1 /** 2 * 3 * Copyright (c) 2019 Microchip Technology Inc. and its subsidiaries. 4 * 5 * \asf_license_start 6 * 7 * \page License 8 * 9 * SPDX-License-Identifier: Apache-2.0 10 * 11 * Licensed under the Apache License, Version 2.0 (the "License"); you may 12 * not use this file except in compliance with the License. 13 * You may obtain a copy of the Licence at 14 * 15 * http://www.apache.org/licenses/LICENSE-2.0 16 * 17 * Unless required by applicable law or agreed to in writing, software 18 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 19 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 20 * See the License for the specific language governing permissions and 21 * limitations under the License. 22 * 23 * \asf_license_stop 24 * 25 */ 26 27 /** @file espi_io.h 28 *MEC1501 eSPI IO Component definitions 29 */ 30 /** @defgroup MEC1501 Peripherals eSPI IO Component 31 */ 32 33 #ifndef _ESPI_IO_H 34 #define _ESPI_IO_H 35 36 #include <stdint.h> 37 #include <stddef.h> 38 39 #include "regaccess.h" 40 41 /*------------------------------------------------------------------*/ 42 43 #define MCHP_ESPI_IO_BASE_ADDR 0x400F3400u 44 45 /* Offsets from base for various register groups */ 46 #define MCHP_ESPI_IO_PC_OFS 0x0100u 47 #define MCHP_ESPI_IO_HOST_BAR_OFS 0x0120u 48 #define MCHP_ESPI_IO_LTR_OFS 0x0220u 49 #define MCHP_ESPI_IO_OOB_OFS 0x0240u 50 #define MCHP_ESPI_IO_FC_OFS 0x0280u 51 #define MCHP_ESPI_IO_CAP_OFS 0x02b0u 52 #define MCHP_ESPI_IO_SIRQ_OFS 0x03a0u 53 54 /* 55 * ESPI IO Component interrupts 56 */ 57 #define MCHP_ESPI_IO_GIRQ 19u 58 #define MCHP_ESPI_IO_GIRQ_NVIC 11u 59 60 /* Direct mode NVIC inputs */ 61 #define MCHP_ESPI_PC_NVIC 103u 62 #define MCHP_ESPI_BM1_NVIC 104u 63 #define MCHP_ESPI_BM2_NVIC 105u 64 #define MCHP_ESPI_LTR_NVIC 106u 65 #define MCHP_ESPI_OOB_UP_NVIC 107u 66 #define MCHP_ESPI_OOB_DN_NVIC 108u 67 #define MCHP_ESPI_FC_NVIC 109u 68 #define MCHP_ESPI_ESPI_RST_NVIC 110u 69 #define MCHP_ESPI_VW_EN_NVIC 156u 70 71 /* GIRQ Source, Enable_Set/Clr, Result registers bit positions */ 72 #define MCHP_ESPI_PC_GIRQ_POS 0 73 #define MCHP_ESPI_BM1_GIRQ_POS 1 74 #define MCHP_ESPI_BM2_GIRQ_POS 2 75 #define MCHP_ESPI_LTR_GIRQ_POS 3 76 #define MCHP_ESPI_OOB_UP_GIRQ_POS 4 77 #define MCHP_ESPI_OOB_DN_GIRQ_POS 5 78 #define MCHP_ESPI_FC_GIRQ_POS 6 79 #define MCHP_ESPI_ESPI_RST_GIRQ_POS 7 80 #define MCHP_ESPI_VW_EN_GIRQ_POS 8 81 /* 82 * !!!! NOTE !!!! 83 * eSPI SAF Done and Error interrupt signals do not 84 * have direct mode NVIC connections. 85 * GIRQ19 cannot be configured for direct mode unless 86 * SAF interrupt are not used. 87 */ 88 #define MCHP_ESPI_SAF_DONE_GIRQ_POS 9 89 #define MCHP_ESPI_SAF_ERR_GIRQ_POS 10 90 91 #define MCHP_ESPI_PC_GIRQ_VAL BIT(0) 92 #define MCHP_ESPI_BM1_GIRQ_VAL BIT(1) 93 #define MCHP_ESPI_BM2_GIRQ_VAL BIT(2) 94 #define MCHP_ESPI_LTR_GIRQ_VAL BIT(3) 95 #define MCHP_ESPI_OOB_UP_GIRQ_VAL BIT(4) 96 #define MCHP_ESPI_OOB_DN_GIRQ_VAL BIT(5) 97 #define MCHP_ESPI_FC_GIRQ_VAL BIT(6) 98 #define MCHP_ESPI_ESPI_RST_GIRQ_VAL BIT(7) 99 #define MCHP_ESPI_VW_EN_GIRQ_VAL BIT(8) 100 #define MCHP_ESPI_SAF_DONE_GIRQ_VAL BIT(9) 101 #define MCHP_ESPI_SAF_ERR_GIRQ_VAL BIT(10) 102 103 /* eSPI Global Capabilities 0 */ 104 #define MCHP_ESPI_GBL_CAP0_MASK 0x0fu 105 #define MCHP_ESPI_GBL_CAP0_PC_SUPP BIT(0) 106 #define MCHP_ESPI_GBL_CAP0_VW_SUPP BIT(1) 107 #define MCHP_ESPI_GBL_CAP0_OOB_SUPP BIT(2) 108 #define MCHP_ESPI_GBL_CAP0_FC_SUPP BIT(3) 109 110 /* eSPI Global Capabilities 1 */ 111 #define MCHP_ESPI_GBL_CAP1_MASK 0xffu 112 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_POS 0u 113 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_MASK 0x07u 114 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_20M 0x00u 115 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_25M 0x01u 116 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_33M 0x02u 117 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_50M 0x03u 118 #define MCHP_ESPI_GBL_CAP1_MAX_FREQ_66M 0x04u 119 #define MCHP_ESPI_GBL_CAP1_ALERT_POS 3 /* Read-Only */ 120 #define MCHP_ESPI_GBL_CAP1_ALERT_DED_PIN \ 121 (1u << (MCHP_ESPI_GBL_CAP1_ALERT_POS)) 122 #define MCHP_ESPI_GBL_CAP1_ALERT_ON_IO1 \ 123 (0u << (MCHP_ESPI_GBL_CAP1_ALERT_POS)) 124 #define MCHP_ESPI_GBL_CAP1_IO_MODE_POS 4 125 #define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0 0x03u 126 #define MCHP_ESPI_GBL_CAP1_IO_MODE_MASK \ 127 ((MCHP_ESPI_GBL_CAP1_IO_MODE_MASK0) << \ 128 (MCHP_ESPI_GBL_CAP1_IO_MODE_POS)) 129 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_1 0u 130 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_12 1u 131 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_14 2u 132 #define MCHP_ESPI_GBL_CAP1_IO_MODE0_124 3u 133 #define MCHP_ESPI_GBL_CAP1_IO_MODE_1 \ 134 ((MCHP_ESPI_GBL_CAP1_IO_MODE0_1) << \ 135 (MCHP_ESPI_GBL_CAP1_IO_MODE_POS)) 136 #define MCHP_ESPI_GBL_CAP1_IO_MODE_12 \ 137 ((MCHP_ESPI_GBL_CAP1_IO_MODE0_12) << \ 138 (MCHP_ESPI_GBL_CAP1_IO_MODE_POS)) 139 #define MCHP_ESPI_GBL_CAP1_IO_MODE_14 \ 140 ((MCHP_ESPI_GBL_CAP1_IO_MODE0_14) << \ 141 (MCHP_ESPI_GBL_CAP1_IO_MODE_POS)) 142 #define MCHP_ESPI_GBL_CAP1_IO_MODE_124 \ 143 ((MCHP_ESPI_GBL_CAP1_IO_MODE0_124) << \ 144 (MCHP_ESPI_GBL_CAP1_IO_MODE_POS)) 145 /* 146 * Support Open Drain ALERT pin configuration 147 * EC sets this bit if it can support open-drain ESPI_ALERT# 148 */ 149 #define MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS 6u 150 #define MCHP_ESPI_GBL_CAP1_ALERT_ODS \ 151 (1u << (MCHP_ESPI_GBL_CAP1_ALERT_ODS_POS)) 152 153 /* 154 * Read-Only ALERT Open Drain select. 155 * If EC has indicated it can support open-drain ESPI_ALERT# then 156 * the Host can enable open-drain ESPI_ALERT# by sending a configuraiton 157 * message. This read-only bit relects the configuration selection. 158 */ 159 #define MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS 7u 160 #define MCHP_ESPI_GBL_CAP1_ALERT_SEL_ODS \ 161 (1u << (MCHP_ESPI_GBL_CAP1_ALERT_ODS_SEL_POS)) 162 163 /* Peripheral Channel(PC) Capabilites */ 164 #define MCHP_ESPI_PC_CAP_MASK 0x07u 165 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_MASK 0x07u 166 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_64 0x01u 167 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_128 0x02u 168 #define MCHP_ESPI_PC_CAP_MAX_PLD_SZ_256 0x03u 169 170 /* Virtual Wire(VW) Capabilities */ 171 #define MCHP_ESPI_VW_CAP_MASK 0x3fu 172 #define MCHP_ESPI_VW_CAP_MAX_VW_CNT_MASK 0x3fu 173 174 /* Out-of-Band(OOB) Capabilities */ 175 #define MCHP_ESPI_OOB_CAP_MASK 0x07u 176 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_MASK 0x07u 177 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_73 0x01u 178 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_137 0x02u 179 #define MCHP_ESPI_OOB_CAP_MAX_PLD_SZ_265 0x03u 180 181 /* Flash Channel(FC) Capabilities */ 182 #define MCHP_ESPI_FC_CAP_MASK 0xffu 183 #define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_MASK 0x07u 184 #define MCHP_ESPI_FC_CAP_MAX_PLD_SZ_64 0x01u 185 #define MCHP_ESPI_FC_CAP_SHARE_POS 3u 186 #define MCHP_ESPI_FC_CAP_SHARE_MASK0 0x03u 187 #define MCHP_ESPI_FC_CAP_SHARE_MASK \ 188 ((MCHP_ESPI_FC_CAP_SHARE_MASK0) << \ 189 (MCHP_ESPI_FC_CAP_SHARE_POS)) 190 #define MCHP_ESPI_FC_CAP_SHARE_MAF_ONLY 0 191 #define MCHP_ESPI_FC_CAP_SHARE_MAF2_ONLY \ 192 (1u << (MCHP_ESPI_FC_CAP_SHARE_POS)) 193 #define MCHP_ESPI_FC_CAP_SHARE_SAF_ONLY \ 194 (2u << (MCHP_ESPI_FC_CAP_SHARE_POS)) 195 #define MCHP_ESPI_FC_CAP_SHARE_MAF_SAF \ 196 (3u << (MCHP_ESPI_FC_CAP_SHARE_POS)) 197 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS 5u 198 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0 0x07u 199 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK \ 200 ((MCHP_ESPI_FC_CAP_MAX_RD_SZ_MASK0) << \ 201 (MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS)) 202 #define MCHP_ESPI_FC_CAP_MAX_RD_SZ_64 \ 203 (1u << (MCHP_ESPI_FC_CAP_MAX_RD_SZ_POS)) 204 205 /* PC Ready */ 206 #define MCHP_ESPI_PC_READY_MASK 0x01u; 207 #define MCHP_ESPI_PC_READY 0x01u; 208 209 /* OOB Ready */ 210 #define MCHP_ESPI_OOB_READY_MASK 0x01u; 211 #define MCHP_ESPI_OOB_READY 0x01u; 212 213 /* FC Ready */ 214 #define MCHP_ESPI_FC_READY_MASK 0x01u; 215 #define MCHP_ESPI_FC_READY 0x01u; 216 217 /* ESPI_RESET# Interrupt Status */ 218 #define MCHP_ESPI_RST_ISTS_MASK 0x03u; 219 #define MCHP_ESPI_RST_ISTS_POS 0u 220 #define MCHP_ESPI_RST_ISTS (1u << (MCHP_ESPI_RST_ISTS_POS)) 221 #define MCHP_ESPI_RST_ISTS_PIN_RO_POS 1u 222 #define MCHP_ESPI_RST_ISTS_PIN_RO_HI \ 223 (1u << (MCHP_ESPI_RST_ISTS_PIN_RO_POS)) 224 225 /* ESPI_RESET# Interrupt Enable */ 226 #define MCHP_ESPI_RST_IEN_MASK 0x01u 227 #define MCHP_ESPI_RST_IEN 0x01u 228 229 /* eSPI Platform Reset Source */ 230 #define MCHP_ESPI_PLTRST_SRC_MASK 0x01u 231 #define MCHP_ESPI_PLTRST_SRC_POS 0 232 #define MCHP_ESPI_PLTRST_SRC_IS_PIN 0x01u 233 #define MCHP_ESPI_PLTRST_SRC_IS_VW 0x00u 234 235 /* VW Ready */ 236 #define MCHP_ESPI_VW_READY_MASK 0x01u 237 #define MCHP_ESPI_VW_READY 0x01u 238 239 /* SAF Erase Block size */ 240 #define MCHP_ESPI_SERASE_SZ_1K_BITPOS 0 241 #define MCHP_ESPI_SERASE_SZ_2K_BITPOS 1 242 #define MCHP_ESPI_SERASE_SZ_4K_BITPOS 2 243 #define MCHP_ESPI_SERASE_SZ_8K_BITPOS 3 244 #define MCHP_ESPI_SERASE_SZ_16K_BITPOS 4 245 #define MCHP_ESPI_SERASE_SZ_32K_BITPOS 5 246 #define MCHP_ESPI_SERASE_SZ_64K_BITPOS 6 247 #define MCHP_ESPI_SERASE_SZ_128K_BITPOS 7 248 #define MCHP_ESPI_SERASE_SZ_1K BIT(0) 249 #define MCHP_ESPI_SERASE_SZ_2K BIT(1) 250 #define MCHP_ESPI_SERASE_SZ_4K BIT(2) 251 #define MCHP_ESPI_SERASE_SZ_8K BIT(3) 252 #define MCHP_ESPI_SERASE_SZ_16K BIT(4) 253 #define MCHP_ESPI_SERASE_SZ_32K BIT(5) 254 #define MCHP_ESPI_SERASE_SZ_64K BIT(6) 255 #define MCHP_ESPI_SERASE_SZ_128K BIT(7) 256 #define MCHP_ESPI_SERASE_SZ(bitpos) BIT((bitpos)+10) 257 258 /* VW Error Status */ 259 #define MCHP_ESPI_VW_ERR_STS_MASK 0x33u 260 #define MCHP_ESPI_VW_ERR_STS_FATAL_POS 0u 261 #define MCHP_ESPI_VW_ERR_STS_FATAL_RO \ 262 BIT(MCHP_ESPI_VW_ERR_STS_FATAL_POS) 263 #define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS 1u 264 #define MCHP_ESPI_VW_ERR_STS_FATAL_CLR_WO \ 265 BIT(MCHP_ESPI_VW_ERR_STS_FATAL_CLR_POS) 266 #define MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS 4u 267 #define MCHP_ESPI_VW_ERR_STS_NON_FATAL_RO \ 268 BIT(MCHP_ESPI_VW_ERR_STS_NON_FATAL_POS) 269 #define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS 5u 270 #define MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_WO \ 271 BIT(MCHP_ESPI_VW_ERR_STS_NON_FATAL_CLR_POS) 272 273 /* VW Channel Enable Status */ 274 #define MCHP_ESPI_VW_EN_STS_MASK 0x01u 275 #define MCHP_ESPI_VW_EN_STS_RO 0x01u 276 277 /** 278 * @brief ESPI Host interface IO Component (MCHP_ESPI_IO) 279 */ 280 281 /* 282 * ESPI_IO_CAP - eSPI IO capabilities, channel ready, activate, 283 * registers @ 0x400F36B0 284 * VW_EN_STS (@ 0x36B0) Virtual Wire Enable Status 285 * CAP_ID (@ 0x36E0) Capabilities ID 286 * GLB_CAP0 (@ 0x36E1) Global Capabilities 0 287 * GLB_CAP1 (@ 0x36E2) Global Capabilities 1 288 * PC_CAP (@ 0x36E3) Periph Chan Capabilities 289 * VW_CAP (@ 0x36E4) Virtual Wire Chan Capabilities 290 * OOB_CAP (@ 0x36E5) OOB Chan Capabilities 291 * FC_CAP (@ 0x36E6) Flash Chan Capabilities 292 * PC_RDY (@ 0x36E7) PC ready 293 * OOB_RDY (@ 0x36E8) OOB ready 294 * FC_RDY (@ 0x36E9) OOB ready 295 * ERST_STS (@ 0x36EA) eSPI Reset interrupt status 296 * ERST_IEN (@ 0x36EB) eSPI Reset interrupt enable 297 * PLTRST_SRC (@ 0x36EC) Platform Reset Source 298 * VW_RDY (@ 0x36ED) VW ready 299 * FC_SERBZ (@ 0x36EE) S-Erase Block Size 300 * VW_ERR_STS (@ 0x37F0) IO Virtual Wire Error 301 */ 302 typedef struct espi_io_cap_regs { 303 __IOM uint32_t VW_EN_STS; 304 uint8_t RSVD1[0x36e0 - 0x36b4]; 305 __IOM uint8_t CAP_ID; 306 __IOM uint8_t GLB_CAP0; 307 __IOM uint8_t GLB_CAP1; 308 __IOM uint8_t PC_CAP; 309 __IOM uint8_t VW_CAP; 310 __IOM uint8_t OOB_CAP; 311 __IOM uint8_t FC_CAP; 312 __IOM uint8_t PC_RDY; 313 __IOM uint8_t OOB_RDY; 314 __IOM uint8_t FC_RDY; 315 __IOM uint8_t ERST_STS; 316 __IOM uint8_t ERST_IEN; 317 __IOM uint8_t PLTRST_SRC; 318 __IOM uint8_t VW_RDY; 319 __IOM uint8_t FC_SERBZ; 320 uint8_t RSVD2[0x37f0u - 0x36ee]; 321 __IOM uint32_t VW_ERR_STS; 322 } ESPI_IO_CAP_Type; 323 324 /* 325 * MCHP_ESPI_IO_PC - eSPI IO Peripheral Channel registers @ 0x400F3500 326 */ 327 328 /* 329 * Peripheral Channel Last Cycle length, type, and tag. 330 */ 331 #define MCHP_ESPI_PC_LC_LEN_POS 0u 332 #define MCHP_ESPI_PC_LC_LEN_MASK0 0x0fffu 333 #define MCHP_ESPI_PC_LC_LEN_MASK 0x0fffu 334 #define MCHP_ESPI_PC_LC_TYPE_POS 12u 335 #define MCHP_ESPI_PC_LC_TYPE_MASK0 0xffu 336 #define MCHP_ESPI_PC_LC_TYPE_MASK (0xffu << 12) 337 #define MCHP_ESPI_PC_LC_TAG_POS 20u 338 #define MCHP_ESPI_PC_LC_TAG_MASK0 0x0fu 339 #define MCHP_ESPI_PC_LC_TAG_MASK (0x0fu << 20) 340 341 /* 342 * Peripheral Channel Status 343 * Bus error, Channel enable change, and Bus master enable change. 344 */ 345 #define MCHP_ESPI_PC_STS_BUS_ERR_POS 16u 346 #define MCHP_ESPI_PC_STS_BUS_ERR BIT(16) /* RW1C */ 347 #define MCHP_ESPI_PC_STS_EN_POS 24u 348 #define MCHP_ESPI_PC_STS_EN BIT(24) /* RO */ 349 #define MCHP_ESPI_PC_STS_EN_CHG_POS 25u 350 #define MCHP_ESPI_PC_STS_EN_CHG BIT(25) /* RW1C */ 351 #define MCHP_ESPI_PC_STS_BM_EN_POS 27u 352 #define MCHP_ESPI_PC_STS_BM_EN BIT(27) /* RO */ 353 #define MCHP_ESPI_PC_STS_BM_EN_CHG_POS 28u 354 #define MCHP_ESPI_PC_STS_BM_EN_CHG BIT(28) /* RW1C */ 355 356 /* 357 * Peripheral Channel Interrupt Enables for 358 * Bus error, Channel enable change, and Bus master enable change. 359 * PC_LC_ADDR_LSW (@ 0x0000) Periph Chan Last Cycle address LSW 360 * PC_LC_ADDR_MSW (@ 0x0004) Periph Chan Last Cycle address MSW 361 * PC_LC_LEN_TYPE_TAG (@ 0x0008) Periph Chan Last Cycle length/type/tag 362 * PC_ERR_ADDR_LSW (@ 0x000C) Periph Chan Error Address LSW 363 * PC_ERR_ADDR_MSW (@ 0x0010) Periph Chan Error Address MSW 364 * PC_STATUS (@ 0x0014) Periph Chan Status 365 * PC_IEN (@ 0x0018) Periph Chan IEN 366 */ 367 #define MCHP_ESPI_PC_IEN_BUS_ERR_POS 16u 368 #define MCHP_ESPI_PC_IEN_BUS_ERR BIT(16) 369 #define MCHP_ESPI_PC_IEN_EN_CHG_POS 25u 370 #define MCHP_ESPI_PC_IEN_EN_CHG BIT(25) 371 #define MCHP_ESPI_PC_IEN_BM_EN_CHG_POS 28u 372 #define MCHP_ESPI_PC_IEN_BM_EN_CHG BIT(28) 373 374 typedef struct espi_io_pc_regs 375 { 376 __IOM uint32_t PC_LC_ADDR_LSW; 377 __IOM uint32_t PC_LC_ADDR_MSW; 378 __IOM uint32_t PC_LC_LEN_TYPE_TAG; 379 __IOM uint32_t PC_ERR_ADDR_LSW; 380 __IOM uint32_t PC_ERR_ADDR_MSW; 381 __IOM uint32_t PC_STATUS; 382 __IOM uint32_t PC_IEN; 383 } ESPI_IO_PC_Type; 384 385 /* ESPI_IO_LTR - eSPI IO LTR registers */ 386 #define MCHP_ESPI_LTR_STS_TX_DONE_POS 0u 387 #define MCHP_ESPI_LTR_STS_TX_DONE BIT(0) /* RW1C */ 388 #define MCHP_ESPI_LTR_STS_OVRUN_POS 3u 389 #define MCHP_ESPI_LTR_STS_OVRUN BIT(3) /* RW1C */ 390 #define MCHP_ESPI_LTR_STS_HDIS_POS 4u 391 #define MCHP_ESPI_LTR_STS_HDIS BIT(4) /* RW1C */ 392 #define MCHP_ESPI_LTR_STS_TX_BUSY_POS 8u 393 #define MCHP_ESPI_LTR_STS_TX_BUSY BIT(8) /* RO */ 394 395 #define MCHP_ESPI_LTR_IEN_TX_DONE_POS 0u 396 #define MCHP_ESPI_LTR_IEN_TX_DONE BIT(0) 397 398 #define MCHP_ESPI_LTR_CTRL_START_POS 0u 399 #define MCHP_ESPI_LTR_CTRL_START BIT(0) 400 #define MCHP_ESPI_LTR_CTRL_TAG_POS 8u 401 #define MCHP_ESPI_LTR_CTRL_TAG_MASK0 0x0fu 402 #define MCHP_ESPI_LTR_CTRL_TAG_MASK (0x0fu << 8) 403 404 #define MCHP_ESPI_LTR_MSG_VAL_POS 0u 405 #define MCHP_ESPI_LTR_MSG_VAL_MASK0 0x3ffu 406 #define MCHP_ESPI_LTR_MSG_VAL_MASK (0x3ffu << 0) 407 #define MCHP_ESPI_LTR_MSG_SC_POS 10u 408 #define MCHP_ESPI_LTR_MSG_SC_MASK0 0x07u 409 #define MCHP_ESPI_LTR_MSG_SC_MASK (0x07u << 10) 410 #define MCHP_ESPI_LTR_MSG_RT_POS 13u 411 #define MCHP_ESPI_LTR_MSG_RT_MASK0 0x03u 412 #define MCHP_ESPI_LTR_MSG_RT_MASK (0x03u << 13) 413 /* eSPI specification indicates RT field must be 00b */ 414 #define MCHP_ESPI_LTR_MSG_RT_VAL 0 415 #define MCHP_ESPI_LTR_MSG_REQ_POS 15u 416 /* inifinite latency(default) */ 417 #define MCHP_ESPI_LTR_MSG_REQ_INF 0 418 /* latency computed from VAL and SC(scale) fields */ 419 #define MCHP_ESPI_LTR_MSG_REQ_VAL BIT(15) 420 421 /* 422 * eSPI IO Component LTR registers @ 0x400F3620 423 * LTR_STS (@ 0x0000) LTR peripheral ptatus 424 * LTR_IEN (@ 0x0004) LTR peripheral interrupt enable 425 * LTR_CTRL (@ 0x0008) LTR peripheral control 426 * LTR_MSG (@ 0x000C) LTR peripheral message 427 */ 428 typedef struct espi_io_ltr_regs 429 { 430 __IOM uint32_t LTR_STS; 431 __IOM uint32_t LTR_IEN; 432 __IOM uint32_t LTR_CTRL; 433 __IOM uint32_t LTR_MSG; 434 } ESPI_IO_LTR_Type; 435 436 /* ESPI_IO_OOB - eSPI IO OOB registers */ 437 #define MCHP_ESPI_OOB_RX_ADDR_LSW_MASK 0xfffffffcu 438 #define MCHP_ESPI_OOB_TX_ADDR_LSW_MASK 0xfffffffcu 439 440 /* RX_LEN register */ 441 /* Number of bytes received (RO) */ 442 #define MCHP_ESPI_OOB_RX_LEN_POS 0u 443 #define MCHP_ESPI_OOB_RX_LEN_MASK 0x1fffu 444 /* Recieve buffer length field (RW) */ 445 #define MCHP_ESPI_OOB_RX_BUF_LEN_POS 16u 446 #define MCHP_ESPI_OOB_RX_BUF_LEN_MASK0 0x1fffu 447 #define MCHP_ESPI_OOB_RX_BUF_LEN_MASK (0x1fffu << 16) 448 449 /* TX_LEN register */ 450 #define MCHP_ESPI_OOB_TX_MSG_LEN_POS 0u 451 #define MCHP_ESPI_OOB_TX_MSG_LEN_MASK 0x1fffu 452 453 /* RX_CTRL */ 454 /* Set AVAIL bit to indicate SRAM Buffer and size has been configured */ 455 #define MCHP_ESPI_OOB_RX_CTRL_AVAIL_POS 0u 456 #define MCHP_ESPI_OOB_RX_CTRL_AVAIL BIT(0) /* WO */ 457 #define MCHP_ESPI_OOB_RX_CTRL_CHEN_POS 9u 458 #define MCHP_ESPI_OOB_RX_CTRL_CHEN BIT(9) /* RO */ 459 /* Copy of eSPI OOB Capabilities max. payload size */ 460 #define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_POS 16u 461 #define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK0 0x07u 462 #define MCHP_ESPI_OOB_RX_CTRL_MAX_SZ_MASK (0x07u << 16) /* RO */ 463 464 /* RX_IEN */ 465 #define MCHP_ESPI_OOB_RX_IEN_POS 0u 466 #define MCHP_ESPI_OOB_RX_IEN BIT(0) 467 468 /* RX_STS */ 469 #define MCHP_ESPI_OOB_RX_STS_DONE_POS 0u 470 #define MCHP_ESPI_OOB_RX_STS_DONE BIT(0) /* RW1C */ 471 #define MCHP_ESPI_OOB_RX_STS_IBERR_POS 1u 472 #define MCHP_ESPI_OOB_RX_STS_IBERR BIT(1) /* RW1C */ 473 #define MCHP_ESPI_OOB_RX_STS_OVRUN_POS 2u 474 #define MCHP_ESPI_OOB_RX_STS_OVRUN BIT(2) /* RW1C */ 475 #define MCHP_ESPI_OOB_RX_STS_RXEN_POS 3u 476 #define MCHP_ESPI_OOB_RX_STS_RXEN BIT(3) /* RO */ 477 #define MCHP_ESPI_OOB_RX_STS_TAG_POS 8u 478 #define MCHP_ESPI_OOB_RX_STS_TAG_MASK0 0x0fu 479 #define MCHP_ESPI_OOB_RX_STS_TAG_MASK (0x0fu << 8) /* RO */ 480 481 #define MCHP_ESPI_OOB_RX_STS_ALL_RW1C 0x07u 482 #define MCHP_ESPI_OOB_RX_STS_ALL 0x0fu 483 484 /* TX_CTRL */ 485 #define MCHP_ESPI_OOB_TX_CTRL_START_POS 0u 486 #define MCHP_ESPI_OOB_TX_CTRL_START BIT(0) /* WO */ 487 #define MCHP_ESPI_OOB_TX_CTRL_TAG_POS 8u 488 #define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK0 0x0fu 489 #define MCHP_ESPI_OOB_TX_CTRL_TAG_MASK (0x0fu << 8) /* RW */ 490 491 /* TX_IEN */ 492 #define MCHP_ESPI_OOB_TX_IEN_DONE_POS 0u 493 #define MCHP_ESPI_OOB_TX_IEN_DONE BIT(0) 494 #define MCHP_ESPI_OOB_TX_IEN_CHG_EN_POS 1u 495 #define MCHP_ESPI_OOB_TX_IEN_CHG_EN BIT(1) 496 #define MCHP_ESPI_OOB_TX_IEN_ALL 0x03u 497 498 /* TX_STS */ 499 #define MCHP_ESPI_OOB_TX_STS_DONE_POS 0u 500 #define MCHP_ESPI_OOB_TX_STS_DONE BIT(0) /* RW1C */ 501 #define MCHP_ESPI_OOB_TX_STS_CHG_EN_POS 1u 502 #define MCHP_ESPI_OOB_TX_STS_CHG_EN BIT(1) /* RW1C */ 503 #define MCHP_ESPI_OOB_TX_STS_IBERR_POS 2u 504 #define MCHP_ESPI_OOB_TX_STS_IBERR BIT(2) /* RW1C */ 505 #define MCHP_ESPI_OOB_TX_STS_OVRUN_POS 3u 506 #define MCHP_ESPI_OOB_TX_STS_OVRUN BIT(3) /* RW1C */ 507 #define MCHP_ESPI_OOB_TX_STS_BADREQ_POS 5u 508 #define MCHP_ESPI_OOB_TX_STS_BADREQ BIT(5) /* RW1C */ 509 #define MCHP_ESPI_OOB_TX_STS_BUSY_POS 8u 510 #define MCHP_ESPI_OOB_TX_STS_BUSY BIT(8) /* RO */ 511 /* Read-only copy of OOB Channel Enabled bit */ 512 #define MCHP_ESPI_OOB_TX_STS_CHEN_POS 9u 513 #define MCHP_ESPI_OOB_TX_STS_CHEN BIT(9) /* RO */ 514 515 #define MCHP_ESPI_OOB_TX_STS_ALL_RW1C 0x2fu 516 517 /* 518 * eSPI IO Component OOB registers @ 0x400F3640 519 * RX_ADDR_LSW (@ 0x0000) OOB Receive Address bits[31:0] 520 * RX_ADDR_MSW (@ 0x0004) OOB Receive Address bits[63:32] 521 * TX_ADDR_LSW (@ 0x0008) OOB Transmit Address bits[31:0] 522 * TX_ADDR_MSW (@ 0x000C) OOB Transmit Address bits[63:32] 523 * RX_LEN (@ 0x0010) OOB Receive length 524 * TX_LEN (@ 0x0014) OOB Transmit length 525 * RX_CTRL (@ 0x0018) OOB Receive control 526 * RX_IEN (@ 0x001C) OOB Receive interrupt enable 527 * RX_STS (@ 0x0020) OOB Receive interrupt status 528 * TX_CTRL (@ 0x0024) OOB Transmit control 529 * TX_IEN (@ 0x0028) OOB Transmit interrupt enable 530 * TX_STS (@ 0x002C) OOB Transmit interrupt status 531 */ 532 typedef struct espi_io_oob_regs 533 { 534 __IOM uint32_t RX_ADDR_LSW; 535 __IOM uint32_t RX_ADDR_MSW; 536 __IOM uint32_t TX_ADDR_LSW; 537 __IOM uint32_t TX_ADDR_MSW; 538 __IOM uint32_t RX_LEN; 539 __IOM uint32_t TX_LEN; 540 __IOM uint32_t RX_CTRL; 541 __IOM uint32_t RX_IEN; 542 __IOM uint32_t RX_STS; 543 __IOM uint32_t TX_CTRL; 544 __IOM uint32_t TX_IEN; 545 __IOM uint32_t TX_STS; 546 } ESPI_IO_OOB_Type; 547 548 /* MCHP_ESPI_IO_FC - eSPI IO Flash channel registers */ 549 /* MEM_ADDR_LSW */ 550 #define MCHP_ESPI_FC_MEM_ADDR_LSW_MASK 0xfffffffcu 551 552 /* CTRL */ 553 #define MCHP_ESPI_FC_CTRL_START_POS 0u 554 #define MCHP_ESPI_FC_CTRL_START BIT(0) /* WO */ 555 #define MCHP_ESPI_FC_CTRL_FUNC_POS 2u 556 #define MCHP_ESPI_FC_CTRL_FUNC_MASK0 0x03u 557 #define MCHP_ESPI_FC_CTRL_FUNC_MASK (0x03u << 2) /* RW */ 558 #define MCHP_ESPI_FC_CTRL_RD0 0x00u 559 #define MCHP_ESPI_FC_CTRL_WR0 0x01u 560 #define MCHP_ESPI_FC_CTRL_ERS0 0x02u 561 #define MCHP_ESPI_FC_CTRL_ERL0 0x03u 562 #define MCHP_ESPI_FC_CTRL_FUNC(f) \ 563 (((uint32_t)(f) & MCHP_ESPI_FC_CTRL_FUNC_MASK0) \ 564 << MCHP_ESPI_FC_CTRL_FUNC_POS) 565 #define MCHP_ESPI_FC_CTRL_TAG_POS 4u 566 #define MCHP_ESPI_FC_CTRL_TAG_MASK0 0x0fu 567 #define MCHP_ESPI_FC_CTRL_TAG_MASK (0x0fu << 4) 568 #define MCHP_ESPI_FC_CTRL_TAG(t) \ 569 (((uint32_t)(t) & MCHP_ESPI_FC_CTRL_TAG_MASK0) \ 570 << MCHP_ESPI_FC_CTRL_TAG_POS) 571 #define MCHP_ESPI_FC_CTRL_ABORT_POS 16u 572 #define MCHP_ESPI_FC_CTRL_ABORT BIT(16) /* WO */ 573 574 /* IEN */ 575 #define MCHP_ESPI_FC_IEN_DONE_POS 0u 576 #define MCHP_ESPI_FC_IEN_DONE BIT(0) 577 #define MCHP_ESPI_FC_IEN_CHG_EN_POS 1u 578 #define MCHP_ESPI_FC_IEN_CHG_EN BIT(1) 579 580 /* CFG */ 581 #define MCHP_ESPI_FC_CFG_BUSY_POS 0u 582 #define MCHP_ESPI_FC_CFG_BUSY BIT(0) /* RO */ 583 #define MCHP_ESPI_FC_CFG_ERBSZ_POS 2u 584 #define MCHP_ESPI_FC_CFG_ERBSZ_MASK0 0x07u 585 #define MCHP_ESPI_FC_CFG_ERBSZ_MASK (0x07u << 2) /* RO */ 586 #define MCHP_ESPI_FC_CFG_ERBSZ_4K (0x01u << 2) 587 #define MCHP_ESPI_FC_CFG_ERBSZ_64K (0x02u << 2) 588 #define MCHP_ESPI_FC_CFG_ERBSZ_4K_64K (0x03u << 2) 589 #define MCHP_ESPI_FC_CFG_ERBSZ_128K (0x04u << 2) 590 #define MCHP_ESPI_FC_CFG_ERBSZ_256K (0x05u << 2) 591 #define MCHP_ESPI_FC_CFG_MAXPLD_POS 8u 592 #define MCHP_ESPI_FC_CFG_MAXPLD_MASK0 0x07u 593 #define MCHP_ESPI_FC_CFG_MAXPLD_MASK (0x07u << 8) /* RO */ 594 #define MCHP_ESPI_FC_CFG_MAXPLD_64B (0x01u << 8) 595 #define MCHP_ESPI_FC_CFG_MAXPLD_128B (0x02u << 8) 596 #define MCHP_ESPI_FC_CFG_MAXPLD_256B (0x03u << 8) 597 #define MCHP_ESPI_FC_CFG_SAFS_SEL_POS 11u 598 #define MCHP_ESPI_FC_CFG_SAFS_SEL (1u << 11) 599 #define MCHP_ESPI_FC_CFG_MAXRD_POS 12u 600 #define MCHP_ESPI_FC_CFG_MAXRD_MASK0 0x07u 601 #define MCHP_ESPI_FC_CFG_MAXRD_MASK (0x07u << 12) /* RO */ 602 #define MCHP_ESPI_FC_CFG_MAXRD_64B (0x01u << 12) 603 #define MCHP_ESPI_FC_CFG_MAXRD_128B (0x02u << 12) 604 #define MCHP_ESPI_FC_CFG_MAXRD_256B (0x03u << 12) 605 #define MCHP_ESPI_FC_CFG_MAXRD_512B (0x04u << 12) 606 #define MCHP_ESPI_FC_CFG_MAXRD_1K (0x05u << 12) 607 #define MCHP_ESPI_FC_CFG_MAXRD_2K (0x06u << 12) 608 #define MCHP_ESPI_FC_CFG_MAXRD_4K (0x07u << 12) 609 #define MCHP_ESPI_FC_CFG_FORCE_MS_POS 28u 610 #define MCHP_ESPI_FC_CFG_FORCE_MS_MASK0 0x03u 611 #define MCHP_ESPI_FC_CFG_FORCE_MS_MASK (0x03u << 28) /* RW */ 612 /* Host (eSPI Master) can select MAFS or SAFS */ 613 #define MCHP_ESPI_FC_CFG_FORCE_NONE 0 614 /* EC forces eSPI slave HW to only allow MAFS */ 615 #define MCHP_ESPI_FC_CFG_FORCE_MAFS (0x02u << 28) 616 /* EC forces eSPI slave HW to only allow SAFS */ 617 #define MCHP_ESPI_FC_CFG_FORCE_SAFS (0x03u << 28) 618 619 /* STS */ 620 #define MCHP_ESPI_FC_STS_CHAN_EN_POS 0u 621 #define MCHP_ESPI_FC_STS_CHAN_EN BIT(0) /* RO */ 622 #define MCHP_ESPI_FC_STS_CHAN_EN_CHG_POS 1u 623 #define MCHP_ESPI_FC_STS_CHAN_EN_CHG BIT(1) /* RW1C */ 624 #define MCHP_ESPI_FC_STS_DONE_POS 2u 625 #define MCHP_ESPI_FC_STS_DONE BIT(2) /* RW1C */ 626 #define MCHP_ESPI_FC_STS_MDIS_POS 3u 627 #define MCHP_ESPI_FC_STS_MDIS BIT(3) /* RW1C */ 628 #define MCHP_ESPI_FC_STS_IBERR_POS 4u 629 #define MCHP_ESPI_FC_STS_IBERR BIT(4) /* RW1C */ 630 #define MCHP_ESPI_FC_STS_ABS_POS 5u 631 #define MCHP_ESPI_FC_STS_ABS BIT(5) /* RW1C */ 632 #define MCHP_ESPI_FC_STS_OVRUN_POS 6u 633 #define MCHP_ESPI_FC_STS_OVRUN BIT(6) /* RW1C */ 634 #define MCHP_ESPI_FC_STS_INC_POS 7u 635 #define MCHP_ESPI_FC_STS_INC BIT(7) /* RW1C */ 636 #define MCHP_ESPI_FC_STS_FAIL_POS 8u 637 #define MCHP_ESPI_FC_STS_FAIL BIT(8) /* RW1C */ 638 #define MCHP_ESPI_FC_STS_OVFL_POS 9u 639 #define MCHP_ESPI_FC_STS_OVFL BIT(9) /* RW1C */ 640 #define MCHP_ESPI_FC_STS_BADREQ_POS 11u 641 #define MCHP_ESPI_FC_STS_BADREQ BIT(11) /* RW1C */ 642 643 #define MCHP_ESPI_FC_STS_ALL_RW1C 0x0bfeu 644 645 /* 646 * eSPI IO Flash Channel registers @ 0x40003680 647 * FL_ADDR_LSW (@ 0x0000) FC flash address bits[31:0] 648 * FL_ADDR_MSW (@ 0x0004) FC flash address bits[63:32] 649 * MEM_ADDR_LSW (@ 0x0008) FC EC Memory address bits[31:0] 650 * MEM_ADDR_MSW (@ 0x000C) FC EC Memory address bits[63:32] 651 * XFR_LEN (@ 0x0010) FC transfer length 652 * CTRL (@ 0x0014) FC Control 653 * IEN (@ 0x0018) FC interrupt enable 654 * CFG (@ 0x001C) FC configuration 655 * STS (@ 0x0020) FC status 656 */ 657 typedef struct espi_io_fc_regs { 658 __IOM uint32_t FL_ADDR_LSW; 659 __IOM uint32_t FL_ADDR_MSW; 660 __IOM uint32_t MEM_ADDR_LSW; 661 __IOM uint32_t MEM_ADDR_MSW; 662 __IOM uint32_t XFR_LEN; 663 __IOM uint32_t CTRL; 664 __IOM uint32_t IEN; 665 __IOM uint32_t CFG; 666 __IOM uint32_t STS; 667 } ESPI_IO_FC_Type; 668 669 /* MCHP_ESPI_IO_BAR_HOST - eSPI IO Host visible BAR registers */ 670 671 /* 672 * IOBAR_INH_LSW/MSW 64-bit register: each bit = 1 inhibits an I/O BAR 673 * independent of the BAR's Valid bit. 674 * Logical Device Number = bit position. 675 */ 676 #define MCHP_ESPI_IOBAR_LDN_MBOX 0x00u 677 #define MCHP_ESPI_IOBAR_LDN_KBC 0x01u 678 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_0 0x02u 679 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_1 0x03u 680 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_2 0x04u 681 #define MCHP_ESPI_IOBAR_LDN_ACPI_EC_3 0x05u 682 #define MCHP_ESPI_IOBAR_LDN_ACPI_PM1 0x07u 683 #define MCHP_ESPI_IOBAR_LDN_PORT92 0x08u 684 #define MCHP_ESPI_IOBAR_LDN_UART_0 0x09u 685 #define MCHP_ESPI_IOBAR_LDN_UART_1 0x0au 686 #define MCHP_ESPI_IOBAR_LDN_UART_2 0x0bu 687 #define MCHP_ESPI_IOBAR_LDN_IOC 0x0du 688 #define MCHP_ESPI_IOBAR_LDN_MEM 0x0eu 689 #define MCHP_ESPI_IOBAR_LDN_GLUE_LOG 0x0fu 690 #define MCHP_ESPI_IOBAR_LDN_EMI_0 0x10u 691 #define MCHP_ESPI_IOBAR_LDN_EMI_1 0x11u 692 #define MCHP_ESPI_IOBAR_LDN_RTC 0x14u 693 #define MCHP_ESPI_IOBAR_LDN_P80CAP_0 0x20u 694 #define MCHP_ESPI_IOBAR_LDN_P80CAP_1 0x21u 695 #define MCHP_ESPI_IOBAR_LDN_T32B 0x2fu 696 697 /* 698 * IOBAR_INIT: Default address of I/O Plug and Play Super-IO index/data 699 * configuration registers. (Defaults to 0x2E/0x2F) 700 */ 701 #define MCHP_ESPI_IOBAR_INIT_DFLT 0x2eu 702 703 /* 704 * EC_IRQ: A write to bit[0] triggers EC SERIRQ. The actual 705 * SERIRQ slot is configured in MCHP_ESPI_IO_SIRQ.EC_SIRQ 706 */ 707 #define MCHP_ESPI_EC_IRQ_GEN BIT(0) 708 709 /* 710 * 32-bit Host IO BAR 711 */ 712 #define MCHP_ESPI_IO_BAR_HOST_VALID_POS 0u 713 #define MCHP_ESPI_IO_BAR_HOST_VALID BIT(0) 714 #define MCHP_ESPI_IO_BAR_HOST_ADDR_POS 16 715 #define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK0 0xffffu 716 #define MCHP_ESPI_IO_BAR_HOST_ADDR_MASK (0xffffu << 16) 717 718 /* 719 * eSPI IO BAR Host registers. 720 * These registers contain the Host side IO address for each peripheral. 721 * IOBAR_INH_LSW (@ 0x0000) BAR Inhibit LSW 722 * IOBAR_INH_MSW (@ 0x0004) BAR Inhibit MSW 723 * IOBAR_INIT (@ 0x0008) BAR Init 724 * EC_IRQ (@ 0x000C) EC IRQ 725 * HOST_BAR_IOC (@ 0x0014) Host IO Component BAR 726 * HOST_BAR_MEM (@ 0x0018) Host IO Compoent Mem BAR 727 * HOST_BAR_MBOX (@ 0x001C) Host IO Mailbox BAR 728 * HOST_BAR_KBC (@ 0x0020) Host IO KBC BAR 729 * HOST_BAR_ACPI_EC_0 (@ 0x0024) Host IO ACPI_EC 0 BAR 730 * HOST_BAR_ACPI_EC_1 (@ 0x0028) Host IO ACPI_EC 1 BAR 731 * HOST_BAR_ACPI_EC_2 (@ 0x002C) Host IO ACPI_EC 2 BAR 732 * HOST_BAR_ACPI_EC_3 (@ 0x0030) Host IO ACPI_EC 3 BAR 733 * HOST_BAR_ACPI_PM1 (@ 0x0038) Host IO ACPI_PM1 BAR 734 * HOST_BAR_PORT92 (@ 0x003C) Host IO PORT92 BAR 735 * HOST_BAR_UART_0 (@ 0x0040) Host IO UART 0 BAR 736 * HOST_BAR_UART_1 (@ 0x0044) Host IO UART 1 BAR 737 * HOST_BAR_EMI_0 (@ 0x0048) Host IO EMI 0 BAR 738 * HOST_BAR_EMI_1 (@ 0x004C) Host IO EMI 1 BAR 739 * HOST_BAR_P80CAP_0 (@ 0x0054) Host IO Port80 Capture 0 BAR 740 * HOST_BAR_P80CAP_1 (@ 0x0058) Host IO Port80 Capture 1 BAR 741 * HOST_BAR_RTC (@ 0x005C) Host IO RTC BAR 742 * HOST_BAR_T32B (@ 0x0064) Host IO Test 32 byte BAR 743 * HOST_BAR_UART_2 (@ 0x0068) Host IO UART 2 BAR 744 * HOST_BAR_GLUE_LOG (@ 0x006C) Host IO Glue Logic BAR 745 */ 746 typedef struct espi_io_bar_host_regs 747 { 748 __IOM uint32_t IOBAR_INH_LSW; 749 __IOM uint32_t IOBAR_INH_MSW; 750 __IOM uint32_t IOBAR_INIT; 751 __IOM uint32_t EC_IRQ; 752 uint8_t RSVD1[4]; 753 __IOM uint32_t HOST_BAR_IOC; 754 __IOM uint32_t HOST_BAR_MEM; 755 __IOM uint32_t HOST_BAR_MBOX; 756 __IOM uint32_t HOST_BAR_KBC; 757 __IOM uint32_t HOST_BAR_ACPI_EC_0; 758 __IOM uint32_t HOST_BAR_ACPI_EC_1; 759 __IOM uint32_t HOST_BAR_ACPI_EC_2; 760 __IOM uint32_t HOST_BAR_ACPI_EC_3; 761 uint8_t RSVD2[4]; 762 __IOM uint32_t HOST_BAR_ACPI_PM1; 763 __IOM uint32_t HOST_BAR_PORT92; 764 __IOM uint32_t HOST_BAR_UART_0; 765 __IOM uint32_t HOST_BAR_UART_1; 766 __IOM uint32_t HOST_BAR_EMI_0; 767 __IOM uint32_t HOST_BAR_EMI_1; 768 uint8_t RSVD3[4]; 769 __IOM uint32_t HOST_BAR_P80CAP_0; 770 __IOM uint32_t HOST_BAR_P80CAP_1; 771 __IOM uint32_t HOST_BAR_RTC; 772 uint8_t RSVD4[4]; 773 __IOM uint32_t HOST_BAR_T32B; 774 __IOM uint32_t HOST_BAR_UART_2; 775 __IOM uint32_t HOST_BAR_GLUE_LOG; 776 } ESPI_IO_BAR_HOST_Type; 777 778 /* 779 * ESPI_IO_BAR_EC - eSPI IO EC-only component of IO BAR @ 0x400F3730 780 * All fields are Read-Only 781 * Address mask in bits[7:0] 782 * Logical device number in bits[13:8] 783 * IO_ACTV (@ 0x0000) ESPI IO Component Activate 784 * EC_BAR_IOC (@ 0x0004) Host IO Component BAR 785 * EC_BAR_MEM (@ 0x0008) Host IO Compoent Mem BAR 786 * EC_BAR_MBOX (@ 0x000C) Host IO Mailbox BAR 787 * EC_BAR_KBC (@ 0x0010) Host IO KBC BAR 788 * EC_BAR_ACPI_EC_0 (@ 0x0014) Host IO ACPI_EC 0 BAR 789 * EC_BAR_ACPI_EC_1 (@ 0x0018) Host IO ACPI_EC 1 BAR 790 * EC_BAR_ACPI_EC_2 (@ 0x001C) Host IO ACPI_EC 2 BAR 791 * EC_BAR_ACPI_EC_3 (@ 0x0020) Host IO ACPI_EC 3 BAR 792 * EC_BAR_ACPI_PM1 (@ 0x0028) Host IO ACPI_PM1 BAR 793 * EC_BAR_PORT92 (@ 0x002C) Host IO PORT92 BAR 794 * EC_BAR_UART_0 (@ 0x0030) Host IO UART 0 BAR 795 * EC_BAR_UART_1 (@ 0x0034) Host IO UART 1 BAR 796 * EC_BAR_EMI_0 (@ 0x0038) Host IO EMI 0 BAR 797 * EC_BAR_EMI_1 (@ 0x003C) Host IO EMI 1 BAR 798 * EC_BAR_P80CAP_0 (@ 0x0044) Host IO Port80 Capture 0 BAR 799 * EC_BAR_P80CAP_1 (@ 0x0048) Host IO Port80 Capture 1 BAR 800 * EC_BAR_RTC (@ 0x004C) Host IO RTC BAR 801 * EC_BAR_T32B (@ 0x0054) Host IO Test 32 byte BAR 802 * EC_BAR_UART_2 (@ 0x0058) Host IO UART 2 BAR 803 * EC_BAR_GLUE_LOG (@ 0x005C) Host IO Glue Logic BAR 804 */ 805 typedef struct espi_io_bar_ec_regs 806 { 807 __IOM uint32_t IO_ACTV; 808 __IOM uint32_t EC_BAR_IOC; 809 __IOM uint32_t EC_BAR_MEM; 810 __IOM uint32_t EC_BAR_MBOX; 811 __IOM uint32_t EC_BAR_KBC; 812 __IOM uint32_t EC_BAR_ACPI_EC_0; 813 __IOM uint32_t EC_BAR_ACPI_EC_1; 814 __IOM uint32_t EC_BAR_ACPI_EC_2; 815 __IOM uint32_t EC_BAR_ACPI_EC_3; 816 uint8_t RSVD2[4]; 817 __IOM uint32_t EC_BAR_ACPI_PM1; 818 __IOM uint32_t EC_BAR_PORT92; 819 __IOM uint32_t EC_BAR_UART_0; 820 __IOM uint32_t EC_BAR_UART_1; 821 __IOM uint32_t EC_BAR_EMI_0; 822 __IOM uint32_t EC_BAR_EMI_1; 823 uint8_t RSVD3[4]; 824 __IOM uint32_t EC_BAR_P80CAP_0; 825 __IOM uint32_t EC_BAR_P80CAP_1; 826 __IOM uint32_t EC_BAR_RTC; 827 uint8_t RSVD4[4]; 828 __IOM uint32_t EC_BAR_T32B; 829 __IOM uint32_t EC_BAR_UART_2; 830 __IOM uint32_t EC_BAR_GLUE_LOG; 831 } ESPI_IO_BAR_EC_Type; 832 833 /* Offsets from first SIRQ */ 834 #define MCHP_ESPI_SIRQ_MBOX_SIRQ 0u 835 #define MCHP_ESPI_SIRQ_MBOX_SMI 1u 836 #define MCHP_ESPI_SIRQ_KBC_KIRQ 2u 837 #define MCHP_ESPI_SIRQ_KBC_MIRQ 3u 838 #define MCHP_ESPI_SIRQ_ACPI_EC0 4u 839 #define MCHP_ESPI_SIRQ_ACPI_EC1 5u 840 #define MCHP_ESPI_SIRQ_ACPI_EC2 6u 841 #define MCHP_ESPI_SIRQ_ACPI_EC3 7u 842 #define MCHP_ESPI_SIRQ_RSVD8 8u 843 #define MCHP_ESPI_SIRQ_UART0 9u 844 #define MCHP_ESPI_SIRQ_UART1 10u 845 #define MCHP_ESPI_SIRQ_EMI0_HOST 11u 846 #define MCHP_ESPI_SIRQ_EMI0_E2H 12u 847 #define MCHP_ESPI_SIRQ_EMI1_HOST 13u 848 #define MCHP_ESPI_SIRQ_EMI1_E2H 14u 849 #define MCHP_ESPI_SIRQ_RSVD15 15u 850 #define MCHP_ESPI_SIRQ_RSVD16 16u 851 #define MCHP_ESPI_SIRQ_RTC 17u 852 #define MCHP_ESPI_SIRQ_EC 18u 853 #define MCHP_ESPI_SIRQ_UART2 19u 854 #define MCHP_ESPI_SIRQ_MAX 20u 855 856 /* 857 * eSPI IO Component Logical Device Serial IRQ configuration @ 0x400F37A0 858 * MBOX_SIRQ_0 (@ 0x000C) Mailbox SIRQ 0 config 859 * MBOX_SIRQ_1 (@ 0x000D) Mailbox SIRQ 1 config 860 * KBC_SIRQ_0 (@ 0x000E) KBC SIRQ 0 config 861 * KBC_SIRQ_1 (@ 0x000F) KBC SIRQ 1 config 862 * ACPI_EC_0_SIRQ (@ 0x0010) ACPI EC 0 SIRQ config 863 * ACPI_EC_1_SIRQ (@ 0x0011) ACPI EC 1 SIRQ config 864 * ACPI_EC_2_SIRQ (@ 0x0012) ACPI EC 2 SIRQ config 865 * ACPI_EC_3_SIRQ (@ 0x0013) ACPI EC 3 SIRQ config 866 * UART_0_SIRQ (@ 0x0015) UART 0 SIRQ config 867 * UART_1_SIRQ (@ 0x0016) UART 1 SIRQ config 868 * EMI_0_SIRQ_0 (@ 0x0017) EMI 0 SIRQ 0 config 869 * EMI_0_SIRQ_1 (@ 0x0018) EMI 0 SIRQ 1 config 870 * EMI_1_SIRQ_0 (@ 0x0019) EMI 1 SIRQ 0 config 871 * EMI_1_SIRQ_1 (@ 0x001A) EMI 1 SIRQ 1 config 872 * RTC_SIRQ (@ 0x001D) RTC SIRQ config 873 * EC_SIRQ (@ 0x001E) EC SIRQ config 874 * UART_2_SIRQ (@ 0x001F) UART 2 SIRQ config 875 */ 876 /* 877 * Values for Logical Device SIRQ registers. 878 * Unless disabled each logical device must have a unique value 879 * programmed to its SIRQ register. 880 * Values 0x00u through 0x7Fu are sent using VWire host index 0x00 881 * Values 0x80h through 0xFEh are sent using VWire host index 0x01 882 * All registers reset default is 0xFFu (disabled). 883 */ 884 #define MCHP_ESPI_IO_SIRQ_DIS 0xffu 885 886 typedef struct espi_io_sirq_regs 887 { 888 uint8_t RSVD1[12]; 889 __IOM uint8_t MBOX_SIRQ_0; 890 __IOM uint8_t MBOX_SIRQ_1; 891 __IOM uint8_t KBC_SIRQ_0; 892 __IOM uint8_t KBC_SIRQ_1; 893 __IOM uint8_t ACPI_EC_0_SIRQ; 894 __IOM uint8_t ACPI_EC_1_SIRQ; 895 __IOM uint8_t ACPI_EC_2_SIRQ; 896 __IOM uint8_t ACPI_EC_3_SIRQ; 897 uint8_t RSVD2[1]; 898 __IOM uint8_t UART_0_SIRQ; 899 __IOM uint8_t UART_1_SIRQ; 900 __IOM uint8_t EMI_0_SIRQ_0; 901 __IOM uint8_t EMI_0_SIRQ_1; 902 __IOM uint8_t EMI_1_SIRQ_0; 903 __IOM uint8_t EMI_1_SIRQ_1; 904 uint8_t RSVD3[2]; 905 __IOM uint8_t RTC_SIRQ; 906 __IOM uint8_t EC_SIRQ; 907 __IOM uint8_t UART_2_SIRQ; 908 } ESPI_IO_SIRQ_Type; 909 910 /* All eSPI IO registers in one structure */ 911 struct espi_io_mbar { /* 80-bit register */ 912 volatile uint16_t LDN_MASK; 913 volatile uint16_t RESERVED[4]; 914 }; /* Size = 10 (0xa) */ 915 916 struct espi_sram_bar { 917 volatile uint16_t VACCSZ; /* valid, access type, and size */ 918 volatile uint16_t EC_SRAM_BASE_LSH; /* EC SRAM base address b[15:0] */ 919 volatile uint16_t EC_SRAM_BASE_MSH; /* EC SRAM base address b[31:16] */ 920 volatile uint16_t RESERVED[2]; 921 }; /* Size = 10 (0xa) */ 922 923 struct espi_mbar_host { 924 volatile uint16_t VALID; 925 volatile uint16_t HADDR_LSH; 926 volatile uint16_t HADDR_MSH; 927 volatile uint16_t RESERVED[2]; 928 }; /* Size = 10 (0xa) */ 929 930 struct espi_sram_host_bar { 931 volatile uint16_t ACCSZ; /* read-only copy of EC access type and size */ 932 volatile uint16_t HBASE_LSH; /* Host memory base b[15:0] */ 933 volatile uint16_t HBASE_MSH; /* Host memory base b[31:16] */ 934 volatile uint16_t RESERVED[2]; 935 }; /* Size = 10 (0xa) */ 936 937 struct espi_io_regs { /* @ 0x400F3400 */ 938 volatile uint8_t RTIDX; /* @ 0x0000 */ 939 volatile uint8_t RTDAT; /* @ 0x0001 */ 940 volatile uint16_t RESERVED; 941 volatile uint32_t RESERVED1[63]; 942 volatile uint32_t PCLC[3]; /* @ 0x0100 */ 943 volatile uint32_t PCERR[2]; /* @ 0x010C */ 944 volatile uint32_t PCSTS; /* @ 0x0114 */ 945 volatile uint32_t PCIEN; /* @ 0x0118 */ 946 volatile uint32_t RESERVED2; 947 volatile uint32_t PCBINH[2]; /* @ 0x0120 */ 948 volatile uint32_t PCBINIT; /* @ 0x0128 */ 949 volatile uint32_t PCECIRQ; /* @ 0x012C */ 950 volatile uint32_t PCCKNP; /* @ 0x0130 */ 951 volatile uint32_t IOBAR[23]; /* @ 0x0134 */ 952 volatile uint32_t RESERVED3[36]; 953 volatile uint32_t PCLTRSTS; /* @ 0x0220 */ 954 volatile uint32_t PCLTREN; /* @ 0x0224 */ 955 volatile uint32_t PCLTRCTL; /* @ 0x0228 */ 956 volatile uint32_t PCLTRM; /* @ 0x022C */ 957 volatile uint32_t RESERVED4[4]; 958 volatile uint32_t OOBRXA[2]; /* @ 0x0240 */ 959 volatile uint32_t OOBTXA[2]; /* @ 0x0248 */ 960 volatile uint32_t OOBRXL; /* @ 0x0250 */ 961 volatile uint32_t OOBTXL; /* @ 0x0254 */ 962 volatile uint32_t OOBRXC; /* @ 0x0258 */ 963 volatile uint32_t OOBRXIEN; /* @ 0x025C */ 964 volatile uint32_t OOBRXSTS; /* @ 0x0260 */ 965 volatile uint32_t OOBTXC; /* @ 0x0264 */ 966 volatile uint32_t OOBTXIEN; /* @ 0x0268 */ 967 volatile uint32_t OOBTXSTS; /* @ 0x026C */ 968 volatile uint32_t RESERVED5[4]; 969 volatile uint32_t FCFA[2]; /* @ 0x0280 */ 970 volatile uint32_t FCBA[2]; /* @ 0x0288 */ 971 volatile uint32_t FCLEN; /* @ 0x0290 */ 972 volatile uint32_t FCCTL; /* @ 0x0294 */ 973 volatile uint32_t FCIEN; /* @ 0x0298 */ 974 volatile uint32_t FCCFG; /* @ 0x029C */ 975 volatile uint32_t FCSTS; /* @ 0x02A0 */ 976 volatile uint32_t RESERVED6[3]; 977 volatile uint32_t VWSTS; /* @ 0x02B0 */ 978 volatile uint32_t RESERVED7[11]; 979 volatile uint8_t CAPID; /* @ 0x02E0 */ 980 volatile uint8_t CAP0; /* @ 0x02E1 */ 981 volatile uint8_t CAP1; /* @ 0x02E2 */ 982 volatile uint8_t CAPPC; /* @ 0x02E3 */ 983 volatile uint8_t CAPVW; /* @ 0x02E4 */ 984 volatile uint8_t CAPOOB; /* @ 0x02E5 */ 985 volatile uint8_t CAPFC; /* @ 0x02E6 */ 986 volatile uint8_t PCRDY; /* @ 0x02E7 */ 987 volatile uint8_t OOBRDY; /* @ 0x02E8 */ 988 volatile uint8_t FCRDY; /* @ 0x02E9 */ 989 volatile uint8_t ERIS; /* @ 0x02EA */ 990 volatile uint8_t ERIE; /* @ 0x02EB */ 991 volatile uint8_t PLTSRC; /* @ 0x02EC */ 992 volatile uint8_t VWRDY; /* @ 0x02ED */ 993 volatile uint8_t SAFEBS; /* @ 0x02EE */ 994 volatile uint8_t RESERVED8; 995 volatile uint32_t RESERVED9[16]; 996 volatile uint32_t ACTV; /* @ 0x0330 */ 997 volatile uint32_t IOHBAR[23]; /* @ 0x0334 */ 998 volatile uint8_t SIRQ[20]; /* @ 0x03AC */ 999 volatile uint32_t RESERVED10[12]; 1000 volatile uint32_t VWERREN; /* @ 0x03F0 */ 1001 volatile uint32_t RESERVED11[79]; 1002 struct espi_io_mbar MBAR[8]; /* @ 0x0530 */ 1003 volatile uint32_t RESERVED12[11]; 1004 struct espi_sram_bar SRAMBAR[2]; /* @ 0x05AC */ 1005 volatile uint32_t RESERVED13[16]; 1006 volatile uint32_t BM_STATUS; /* @ 0x0600 */ 1007 volatile uint32_t BM_IEN; /* @ 0x0604 */ 1008 volatile uint32_t BM_CONFIG; /* @ 0x0608 */ 1009 volatile uint32_t RESERVED14; 1010 volatile uint32_t BM_CTRL1; /* @ 0x0610 */ 1011 volatile uint32_t BM_HADDR1_LSW; /* @ 0x0614 */ 1012 volatile uint32_t BM_HADDR1_MSW; /* @ 0x0618 */ 1013 volatile uint32_t BM_EC_ADDR1_LSW; /* @ 0x061C */ 1014 volatile uint32_t BM_EC_ADDR1_MSW; /* @ 0x0620 */ 1015 volatile uint32_t BM_CTRL2; /* @ 0x0624 */ 1016 volatile uint32_t BM_HADDR2_LSW; /* @ 0x0628 */ 1017 volatile uint32_t BM_HADDR2_MSW; /* @ 0x062C */ 1018 volatile uint32_t BM_EC_ADDR2_LSW; /* @ 0x0630 */ 1019 volatile uint32_t BM_EC_ADDR2_MSW; /* @ 0x0634 */ 1020 volatile uint32_t RESERVED15[62]; 1021 struct espi_mbar_host HMBAR[8]; /* @ 0x0730 */ 1022 volatile uint32_t RESERVED16[11]; 1023 struct espi_sram_host_bar HSRAMBAR[2]; /* @ 0x07AC */ 1024 }; /* Size = 1984 (0x7c0) */ 1025 1026 #endif /* #ifndef _ESPI_IO_H */ 1027 /* end espi_io.h */ 1028 /** @} 1029 */ 1030
