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Searched refs:IOSCB_BANKCONT_DDR (Results 1 – 2 of 2) sorted by relevance

/hal_microchip-3.7.0/mpfs/mpfs_hal/common/nwc/
Dmss_ddr.c801 IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ in ddr_setup()
1155 IOSCB_BANKCONT_DDR->soft_reset = 0U; /* DPC_BITS NV_MAP reset */ in ddr_setup()
1161 IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ in ddr_setup()
1307 IOSCB_BANKCONT_DDR->soft_reset = 0U; /* DPC_BITS NV_MAP reset */ in ddr_setup()
1325 IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ in ddr_setup()
1601 IOSCB_BANKCONT_DDR->soft_reset = 0U; /* DPC_BITS NV_MAP reset */ in ddr_setup()
1607 IOSCB_BANKCONT_DDR->soft_reset = 1U; /* DPC_BITS NV_MAP reset */ in ddr_setup()
3701 IOSCB_BANKCONT_DDR->dpc_bits = (IOSCB_BANKCONT_DDR->dpc_bits &\ in FPGA_VREFDQ_calibration_using_mtc()
3703 IOSCB_BANKCONT_DDR->dpc_bits = (IOSCB_BANKCONT_DDR->dpc_bits &\ in FPGA_VREFDQ_calibration_using_mtc()
3744 IOSCB_BANKCONT_DDR->dpc_bits = (IOSCB_BANKCONT_DDR->dpc_bits &\ in FPGA_VREFDQ_calibration_using_mtc()
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Dmss_ddr.h996 #define IOSCB_BANKCONT_DDR ((volatile IOSCB_BANKCONT_DDR_STRUCT *) IOSCB_BANKCONT_DDR_BASE) macro