1 /******************************************************************************* 2 * Copyright 2019-2021 Microchip FPGA Embedded Systems Solutions. 3 * 4 * SPDX-License-Identifier: MIT 5 * 6 * MPFS HAL Embedded Software 7 * 8 */ 9 10 /******************************************************************************* 11 * @file mss_ddr.h 12 * @author Microchip-FPGA Embedded Systems Solutions 13 * @brief DDR related defines 14 * 15 */ 16 17 /*=========================================================================*//** 18 @page DDR setup and monitoring 19 ============================================================================== 20 @section intro_sec Introduction 21 ============================================================================== 22 The MPFS microcontroller subsystem (MSS) includes a number of hard core 23 components physically located in the north west corner of the MSS on the die. 24 This includes the DDR Phy. 25 26 ============================================================================== 27 @section Items located in the north west corner 28 ============================================================================== 29 - MSS PLL 30 - SGMII 31 - DDR phy 32 - MSSIO 33 34 ============================================================================== 35 @section Overview of DDR related hardware 36 ============================================================================== 37 38 Simplified IP diagram 39 40 41 +--+ 42 +--++ +-----+ +---v--+ |o | 43 |H0 | |H1-H4+--------> AXI | |t | 44 ++--+ +-+---+ |switch<---+h | 45 | | | | |e | 46 | | +--+---+ |r | 47 +v------v-------+ | | | 48 |L2 cache | non-cache |m | 49 +------------+--+ | |a | 50 +---v----+ +---v---+ |s | 51 |seg 0 | | seg 1 | |t | 52 +----^---+ +---^---+ |e | 53 | | |r | 54 +-----------+------+----v---------v---+ |s | 55 |Training IP|MTC |DDR controller | +--+ 56 +-----------+------+--------+---------+ 57 |DFI 58 | 59 +---------v--------+ 60 | DDR Phy | 61 +------------------+ 62 | Bank 6 I/O | 63 +-------+----------+ 64 | 65 +----------v---------------+ 66 | +--+ +--+ +--+ +--+ +--+ | 67 | |D | |D | |R | | | | | | 68 | +--+ +--+ +--+ +--+ +--+ | 69 +--------------------------+ 70 71 72 ----------- 73 Hart0 E51 74 ----------- 75 In most systems, the E51 will will setup and monitor the DDR 76 77 ----------- 78 L2 Cache 79 ----------- 80 Specific address range is used to access DDR via cache 81 82 ----------- 83 AXI switch 84 ----------- 85 DDR access via AXI switch for non-cached read/write 86 87 ----------- 88 SEG regs 89 ----------- 90 Used to map internal DDR address range to external fixed mapping. 91 Note: DDR address ranges are at 32 bit and 64 bits 92 93 ----------- 94 DDR controller 95 ----------- 96 Manages DDR, refresh rates etc 97 98 ----------- 99 DDR Training IP 100 ----------- 101 Used to carry out training using IP state machines 102 - BCLKSCLK_TIP_TRAINING . 103 - addcmd_TIP_TRAINING 104 - wrlvl_TIP_TRAINING 105 - rdgate_TIP_TRAINING 106 - dq_dqs_opt_TIP_TRAINING 107 108 ----------- 109 DDR MTC - Memory test controller 110 ----------- 111 Sends/receives test patterns to DDR. More efficient than using software. 112 Used during write calibration and in DDR test routines. 113 114 ----------- 115 DFI 116 ----------- 117 Industry standard interface between phy, DDRC 118 119 ----------- 120 DDR phy 121 ----------- 122 PolarFire-SoC DDR phy manges data paath between pins and DFI 123 124 ============================================================================== 125 @section Overview of DDR embedded software 126 ============================================================================== 127 128 ----------- 129 Setup 130 ----------- 131 - phy and IO 132 - DDRC 133 134 ----------- 135 Use Training IP 136 ----------- 137 - kick-off RTL training IP state machine 138 - Verify all training complete 139 - BCLKSCLK_TIP_TRAINING . 140 - addcmd_TIP_TRAINING 141 This is a coarse training that moves the DDRCLK with PLL phase 142 rotations in relation to the Address/Command bits to achieve the 143 desired offset on the FPGA side. 144 - wrlvl_TIP_TRAINING 145 - rdgate_TIP_TRAINING 146 - dq_dqs_opt_TIP_TRAINING 147 148 Test this reg to determine training status: 149 DDRCFG->DFI.STAT_DFI_TRAINING_COMPLETE.STAT_DFI_TRAINING_COMPLETE; 150 151 ----------- 152 Write Calibration 153 ----------- 154 The Memory Test Core plugged in to the front end of the DDR controller is used 155 to perform lane-based writes and read backs and increment write calibration 156 offset for each lane until data match occurs. The settings are recorded by the 157 driver and available to be read using by an API function call. 158 159 ----------- 160 VREF Calibration (optional) 161 ----------- 162 VREF (DDR4 + LPDDR4 only) Set Remote VREF via mode register writes (MRW). 163 In DDR4 and LPDDR4, VREF training may be done by writing to Mode Register 6 as 164 defined by the JEDEC spec and, for example, Micron's datasheet for its 4Gb 165 DDR4 RAM's: 166 167 MR6 register definition from DDR4 datasheet 168 169 | Mode Reg | Description | 170 | ------------- |:---------------------------------------------------:| 171 | 13,9,8 | DQ RX EQ must be 000 | 172 | 7 | Vref calib enable = => disables, 1 ==> enabled | 173 | 6 | Vref Calibration range 0 = Range 0, 1 - Range 2 | 174 | 5:0 | Vref Calibration value | 175 176 This step is not implemented in the current driver. It can be implemented in 177 the same way as write Calibration and will be added during board verification. 178 179 ----------- 180 FPGA VREF (Local VREF training) (optional) 181 ----------- 182 In addition to memory VREFDQ training, or remote training, it is possible to 183 train the VREFDQ on the FPGA device. WE refer to this training as local VREF 184 training. 185 Train FPGA VREF using the vrgen_h and vrgen_v registers 186 To manipulate the FPGA VREF value, firmware must write to the DPC_BITS 187 register, located at physical address 0x2000 7184. 188 CFG_DDR_SGMII_PHY->DPC_BITS.bitfield.dpc_vrgen_h; 189 CFG_DDR_SGMII_PHY->DPC_BITS.bitfield.dpc_vrgen_v; 190 Like memory VREFDQ training, FPGA VREFDQ training seeks to find an average/ 191 optimal VREF value by sweeping across the full range and finding a left edge 192 and a right edge. 193 This step is not implemented in the current driver. It can be implemented in 194 the same way as write Calibration and will be added during board verification. 195 196 ----------- 197 DQ Write Offset 198 ----------- 199 (LPDDR4 only) ), there must be an offset at the input to the LPDDR4 memory 200 device between DQ and DQS. Unlike other flavors of DDR, which match DQ and DQS 201 at the SDRAM, for LPDDR4 this relationship must be trained, because it will 202 vary between 200ps and 600ps, which, depending on the data rate, could be as 203 much as one whole bit period. 204 This training is integrated with write calibration, because it, too, is done 205 on a per-lane basis. That is, each lane is trained separately by sweeping the 206 DQ output delay to find a valid range and of DQ output delays and center it. 207 DQ output delays are swept using the expert_dlycnt_move_reg0 register located 208 in the MSS DDR TIP. 209 210 211 ----------- 212 Overview Flow diagram of Embedded software setup 213 ----------- 214 215 +--------------------------------------------+ 216 | Some Preconditions | 217 | DCE, CORE_UP, FLASH VALID, MSS_IO_EN | 218 | MSS PLL setup, Clks to MSS setup | 219 +--------------------+-----------------------+ 220 | 221 +--------------------v-----------------------+ 222 | Check if in off mode, ret if so | 223 +--------------------+-----------------------+ 224 | 225 +--------------------v-----------------------+ 226 | set ddr mode and VS bits | 227 +--------------------+-----------------------+ 228 | 229 +--------------------v-----------------------+ 230 | soft reset I/O decoders | 231 +--------------------+-----------------------+ 232 | 233 +--------------------v-----------------------+ 234 | Set RPC registers that need manual setup | 235 +--------------------+-----------------------+ 236 | 237 +--------------------v-----------------------+ 238 | Soft reset IP- to load RPC ->SCB regs | 239 +--------------------+-----------------------+ 240 | 241 +--------------------v-----------------------+ 242 | Calibrate I/O - as they are now setup | 243 +--------------------+-----------------------+ 244 | 245 +--------------------v-----------------------+ 246 | Configure the DDR PLL - Using SCB writes | 247 +--------------------+-----------------------+ 248 | 249 +--------------------v-----------------------+ 250 | Setup the SEG regs - NB May move this down| 251 +--------------------+-----------------------+ 252 | 253 +--------------------v-----------------------+ 254 | Set-up the DDRC - Using Libero values | 255 +--------------------+-----------------------+ 256 | 257 +--------------------v-----------------------+ 258 | Reset training IP | 259 +--------------------+-----------------------+ 260 | 261 +----------------- --v-----------------------+ 262 | Rotate BCLK by programmed amount (degrees)| 263 +--------------------+-----------------------+ 264 | 265 +--------------------v-----------------------+ 266 | Set training parameters | 267 +--------------------+-----------------------+ 268 | 269 +--------------------v-----------------------+ 270 | Assert traing reset | 271 +--------------------+-----------------------+ 272 | 273 +--------------------v-----------------------+ 274 | Wait until traing complete | 275 +--------------------+-----------------------+ 276 | 277 +--------------------v-----------------------+ 278 | Write calibrate | 279 +--------------------+-----------------------+ 280 | 281 +--------------------v-----------------------+ 282 | If LPDDR4, calibrate DQ | 283 +--------------------+-----------------------+ 284 | 285 +--------------------v-----------------------+ 286 | Sanity check training | 287 +--------------------+-----------------------+ 288 | 289 +--------------------v-----------------------+ 290 | Return 0 if all went OK | 291 +--------------------------------------------+ 292 293 *//*=========================================================================*/ 294 295 296 #ifndef __MSS_DDRC_H_ 297 #define __MSS_DDRC_H_ 1 298 299 #include <stddef.h> 300 #include <stdint.h> 301 302 303 #ifdef __cplusplus 304 extern "C" { 305 #endif 306 307 /***************************************************************************//** 308 309 */ 310 typedef enum DDR_TYPE_ 311 { 312 313 DDR3 = 0x00, /*!< 0 DDR3 */ 314 DDR3L = 0x01, /*!< 1 DDR3L */ 315 DDR4 = 0x02, /*!< 2 DDR4 */ 316 LPDDR3 = 0x03, /*!< 3 LPDDR3 */ 317 LPDDR4 = 0x04, /*!< 4 LPDDR4 */ 318 DDR_OFF_MODE = 0x07 /*!< 4 LPDDR4 */ 319 } DDR_TYPE; 320 321 typedef enum DDR_MEMORY_ACCESS_ 322 { 323 DDR_NC_256MB, 324 DDR_NC_WCB_256MB, 325 DDR_NC_2GB, 326 DDR_NC_WCB_2GB, 327 } DDR_MEMORY_ACCESS; 328 329 /* this is a fixed value, currently only 5 supported in the TIP */ 330 #define MAX_POSSIBLE_TIP_TRAININGS 0x05U 331 332 /* LIBERO_SETTING_TIP_CFG_PARAMS 333 * ADDCMD_OFFSET [0:3] RW value */ 334 #define ADDRESS_CMD_OFFSETT_MASK (0x7U<<0U) 335 336 #define BCLK_SCLK_OFFSET_SHIFT (3U) 337 #define BCLK_SCLK_OFFSET_MASK (0x7U<<3U) 338 339 #define BCLK_DPC_VRGEN_V_SHIFT (12U) 340 #define BCLK_DPC_VRGEN_V_MASK (0x3FU<<12U) 341 342 #define BCLK_DPC_VRGEN_H_SHIFT (4U) 343 #define BCLK_DPC_VRGEN_H_MASK (0xFU<<4U) 344 345 #define BCLK_DPC_VRGEN_VS_SHIFT (0U) 346 #define BCLK_DPC_VRGEN_VS_MASK (0xFU<<0U) 347 348 349 /* masks and associated values used with DDRPHY_MODE register */ 350 #define DDRPHY_MODE_MASK 0x7U 351 /* ECC */ 352 #define DDRPHY_MODE_ECC_MASK (0x1U<<3U) 353 #define DDRPHY_MODE_ECC_ON (0x1U<<3U) 354 /* Bus width */ 355 #define DDRPHY_MODE_BUS_WIDTH_4_LANE (0x1U<<5U) 356 #define DDRPHY_MODE_BUS_WIDTH_MASK (0x7U<<5U) 357 /* Number of ranks, 1 or 2 supported */ 358 #define DDRPHY_MODE_RANK_MASK (0x1U<<26U) 359 #define DDRPHY_MODE_ONE_RANK (0x0U<<26U) 360 #define DDRPHY_MODE_TWO_RANKS (0x1U<<26U) 361 362 #define DMI_DBI_MASK (~(0x1U<<8U)) 363 364 /* Write latency min/max settings If write calibration fails 365 * For Libero setting, we iterate through these values looking for a 366 * Calibration pass */ 367 #define MIN_LATENCY 0UL 368 #define MAX_LATENCY 3UL //ML fixme- agree this value with Alister 369 370 #define MTC_TIMEOUT_ERROR 0x02U 371 372 #define DDR_MODE_REG_VREF 0xCU 373 374 #define CALIBRATION_PASSED 0xFF 375 #define CALIBRATION_FAILED 0xFE 376 #define CALIBRATION_SUCCESS 0xFC 377 378 /* 379 * Some settings that are only used during testing in new DDR setup 380 */ 381 /* #define LANE_ALIGNMENT_RESET_REQUIRED leave commented, not required */ 382 #define ABNORMAL_RETRAIN_CA_DECREASE_COUNT 2U 383 #define ABNORMAL_RETRAIN_CA_DLY_DECREASE_COUNT 2U 384 #define DQ_DQS_NUM_TAPS 5U 385 /* #define SW_CONFIG_LPDDR_WR_CALIB_FN */ 386 387 #if !defined (LIBERO_SETTING_MAX_MANUAL_REF_CLK_PHASE_OFFSET) 388 #define LIBERO_SETTING_MAX_MANUAL_REF_CLK_PHASE_OFFSET 4U 389 #endif 390 #if !defined (LIBERO_SETTING_MIN_MANUAL_REF_CLK_PHASE_OFFSET) 391 #define LIBERO_SETTING_MIN_MANUAL_REF_CLK_PHASE_OFFSET 2U 392 #endif 393 #if !defined (LIBERO_SETTING_MANUAL_REF_CLK_PHASE_OFFSET) 394 /* If skipping add/cmd training, this value is used */ 395 /* The value used may be trained. The value here should be determined */ 396 /* for the board design by performing a manual sweep. */ 397 #define LIBERO_SETTING_MANUAL_REF_CLK_PHASE_OFFSET 0x00000006UL 398 /* CA_BUS_RX_OFF_POST_TRAINING [0:1] RW value= 0x1 */ 399 #endif 400 401 /* 402 * We currently need at least one retrain, otherwise driver can get stuck in 403 * sanity check state 404 */ 405 #if !defined (EN_RETRY_ON_FIRST_TRAIN_PASS) 406 #define EN_RETRY_ON_FIRST_TRAIN_PASS 0 407 #endif 408 409 #if !defined (DDR_FULL_32BIT_NC_CHECK_EN) 410 #define DDR_FULL_32BIT_NC_CHECK_EN 1 411 #endif 412 413 #if !defined (DDR_FULL_32BIT_CACHED_CHECK_EN) 414 #define DDR_FULL_32BIT_CACHED_CHECK_EN 0 415 #endif 416 417 #if !defined (NO_PATTERN_IN_CACHE_READS) 418 #define NO_PATTERN_IN_CACHE_READS 1 419 #endif 420 421 #if !defined (SIZE_OF_PATTERN_TEST) 422 #define SIZE_OF_PATTERN_TEST 0x02000000UL 423 #endif 424 425 #if !defined (SIZE_OF_PATTERN_OFFSET) 426 #define SIZE_OF_PATTERN_OFFSET 12U 427 #endif 428 429 #if !defined (DEFAULT_RPC_166_VALUE) 430 #define DEFAULT_RPC_166_VALUE 2UL 431 #endif 432 433 /* set to 0 if you want to turn off tuning */ 434 #if !defined (TUNE_RPC_166_VALUE) 435 #define TUNE_RPC_166_VALUE 1 436 #endif 437 438 #if !defined (MIN_RPC_166_VALUE) 439 #define MIN_RPC_166_VALUE 2UL 440 #endif 441 442 #if !defined (MAX_RPC_166_VALUE) 443 #define MAX_RPC_166_VALUE 4UL 444 #endif 445 446 #define NUM_RPC_166_VALUES (MAX_RPC_166_VALUE - MIN_RPC_166_VALUE) 447 448 /* This is a fixed setting, will move into driver in next commit */ 449 #if !defined (SW_TRAING_BCLK_SCLK_OFFSET) 450 #define SW_TRAING_BCLK_SCLK_OFFSET 0x00000000UL 451 #endif 452 /* 453 * 0x6DU => setting vref_ca to 40% 454 * This (0x6DU) is the default setting. 455 * Currently not being used, here for possible future use. 456 * */ 457 #if !defined (DDR_MODE_REG_VREF_VALUE) 458 #define DDR_MODE_REG_VREF_VALUE 0x6DU 459 #endif 460 461 /* number of test writes to perform */ 462 #if !defined (SW_CFG_NUM_READS_WRITES) 463 #define SW_CFG_NUM_READS_WRITES 0x20000U 464 #endif 465 /* 466 * what test patterns to write/read on start-up 467 * */ 468 #if !defined (SW_CONFIG_PATTERN) 469 #define SW_CONFIG_PATTERN (PATTERN_INCREMENTAL|\ 470 PATTERN_WALKING_ONE|\ 471 PATTERN_WALKING_ZERO|\ 472 PATTERN_RANDOM|\ 473 PATTERN_0xCCCCCCCC|\ 474 PATTERN_0x55555555) 475 #endif 476 477 /* 478 * Sweep offsets 479 * They currently are not coming from MSS Configurator (v12.7 and earlier) 480 * They may at some point 481 * 482 * Determined ( 5th Feb 2021 ) 483 * DDR3@1066 = 3,2,1 484 * DDR4@1600 = 7,0,1 485 * LPDDR3@1066 = 7,0,1 486 * LPDDR4@1600 = 5,4,6,3 487 * 488 * DDR3@1333 = 0,1 //1,7,0,2 489 * DDR4@1333 = 0,7,1 490 * LPDDR3@1333 = 0,1 //7,0,6 491 * LPDDR4@1333 = 1,2,3 492 * 493 */ 494 #if !defined (VREF_TRAINING_MIN) 495 #define VREF_TRAINING_MIN 5U 496 #endif 497 #if !defined (VREF_TRAINING_MAX) 498 #define VREF_TRAINING_MAX 30U 499 #endif 500 #if !defined (CA_SWEEP_START) 501 #define CA_SWEEP_START 0U 502 #endif 503 #if !defined (CA_SWEEP_END) 504 #define CA_SWEEP_END 30U 505 #endif 506 #if !defined (CA_SWEEP_INCREMENT) 507 #define CA_SWEEP_INCREMENT 5U 508 #endif 509 510 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS) 511 #define LIBERO_SETTING_REFCLK_DDR3_1333_NUM_OFFSETS 3U 512 #endif 513 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS) 514 #define LIBERO_SETTING_REFCLK_DDR3L_1333_NUM_OFFSETS 3U 515 #endif 516 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_NUM_OFFSETS) 517 #define LIBERO_SETTING_REFCLK_DDR4_1600_NUM_OFFSETS 2U 518 #endif 519 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1600_NUM_OFFSETS) 520 #define LIBERO_SETTING_REFCLK_LPDDR3_1600_NUM_OFFSETS 3U 521 #endif 522 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_NUM_OFFSETS) 523 #define LIBERO_SETTING_REFCLK_LPDDR4_1600_NUM_OFFSETS 4U 524 #endif 525 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_NUM_OFFSETS) 526 #define LIBERO_SETTING_REFCLK_DDR3_1067_NUM_OFFSETS 2U 527 #endif 528 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_NUM_OFFSETS) 529 #define LIBERO_SETTING_REFCLK_DDR3L_1067_NUM_OFFSETS 2U 530 #endif 531 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_NUM_OFFSETS) 532 #define LIBERO_SETTING_REFCLK_DDR4_1333_NUM_OFFSETS 3U 533 #endif 534 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_NUM_OFFSETS) 535 #define LIBERO_SETTING_REFCLK_LPDDR3_1333_NUM_OFFSETS 2U 536 #endif 537 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_NUM_OFFSETS) 538 #define LIBERO_SETTING_REFCLK_LPDDR4_1333_NUM_OFFSETS 3U 539 #endif 540 541 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0) 542 #define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_0 0U 543 #endif 544 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1) 545 #define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_1 1U 546 #endif 547 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2) 548 #define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_2 0U 549 #endif 550 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3) 551 #define LIBERO_SETTING_REFCLK_DDR3_1333_OFFSET_3 1U 552 #endif 553 554 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0) 555 #define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_0 0U 556 #endif 557 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1) 558 #define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_1 1U 559 #endif 560 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2) 561 #define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_2 0U 562 #endif 563 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_3) 564 #define LIBERO_SETTING_REFCLK_DDR3L_1333_OFFSET_3 0U 565 #endif 566 567 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_0) 568 #define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_0 7U 569 #endif 570 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_1) 571 #define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_1 0U 572 #endif 573 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_2) 574 #define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_2 7U 575 #endif 576 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_3) 577 #define LIBERO_SETTING_REFCLK_DDR4_1600_OFFSET_3 0U 578 #endif 579 580 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_0) 581 #define LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_0 7U 582 #endif 583 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_1) 584 #define LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_1 0U 585 #endif 586 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_2) 587 #define LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_2 1U 588 #endif 589 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_3) 590 #define LIBERO_SETTING_REFCLK_LPDDR3_1600_OFFSET_3 0U 591 #endif 592 //LPDDR4@1600 = 5,4,6,3 changed to 5,4,6,2 16th Feb Alister 593 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_0) 594 #define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_0 1U 595 #endif 596 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_1) 597 #define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_1 5U 598 #endif 599 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_2) 600 #define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_2 1U 601 #endif 602 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_3) 603 #define LIBERO_SETTING_REFCLK_LPDDR4_1600_OFFSET_3 5U 604 #endif 605 606 /* 607 * 1333 offset 608 */ 609 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_0) 610 #define LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_0 1U 611 #endif 612 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_1) 613 #define LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_1 2U 614 #endif 615 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_2) 616 #define LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_2 0U 617 #endif 618 #if !defined (LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_3) 619 #define LIBERO_SETTING_REFCLK_DDR3_1067_OFFSET_3 2U 620 #endif 621 622 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_0) 623 #define LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_0 1U 624 #endif 625 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_1) 626 #define LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_1 2U 627 #endif 628 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_2) 629 #define LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_2 0U 630 #endif 631 #if !defined (LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_3) 632 #define LIBERO_SETTING_REFCLK_DDR3L_1067_OFFSET_3 2U 633 #endif 634 635 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_0) 636 #define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_0 0U 637 #endif 638 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_1) 639 #define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_1 1U 640 #endif 641 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_2) 642 #define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_2 7U 643 #endif 644 #if !defined (LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_3) 645 #define LIBERO_SETTING_REFCLK_DDR4_1333_OFFSET_3 0U 646 #endif 647 648 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_0) 649 #define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_0 0U 650 #endif 651 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_1) 652 #define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_1 1U 653 #endif 654 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_2) 655 #define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_2 6U 656 #endif 657 #if !defined (LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_3) 658 #define LIBERO_SETTING_REFCLK_LPDDR3_1333_OFFSET_3 0U 659 #endif 660 661 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_0) 662 #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_0 1U 663 #endif 664 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_1) 665 #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_1 2U 666 #endif 667 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2) 668 #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_2 3U 669 #endif 670 #if !defined (LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3) 671 #define LIBERO_SETTING_REFCLK_LPDDR4_1333_OFFSET_3 0U 672 #endif 673 674 #define DDR_1067_MHZ 1067000000UL 675 #define DDR_1333_MHZ 1333333333UL 676 #define DDR_1600_MHZ 1600000000UL 677 #define DDR_FREQ_MARGIN 10UL 678 679 /* DDR clk frequency - should come from */ 680 #if !defined (LIBERO_SETTING_DDR_CLK) 681 #define LIBERO_SETTING_DDR_CLK 1600000000UL 682 #endif 683 684 #ifndef NOT_A_FULL_RETRAIN 685 #define NOT_A_FULL_RETRAIN 686 #endif 687 688 #if !defined (RPC_OVERRIDE_166_LANE_FIFO) 689 #define RPC_OVERRIDE_166_LANE_FIFO 0 690 #endif 691 692 #define ONE_GB_MTC 30U 693 #define HALF_GB_MTC 29U 694 #define ONE_MB_MTC 20U 695 696 697 /*Cached access at 0x00_8000_0000 (-0x80+0x00) */ 698 #define INIT_SETTING_SEG0_0 0x00007F80UL 699 /* ADDRESS_OFFSET [0:15] RW value= 0x7F80 */ 700 /* RESERVED [15:16] RW value= 0x0 */ 701 /* LOCKED [31:1] RW value= 0x0 */ 702 /*Cached access at 0x10_0000_000 */ 703 #define INIT_SETTING_SEG0_1 0x00007000UL 704 /* ADDRESS_OFFSET [0:15] RW value= 0x7000 */ 705 /* RESERVED [15:16] RW value= 0x0 */ 706 /* LOCKED [31:1] RW value= 0x0 */ 707 /*not used */ 708 #define INIT_SETTING_SEG0_2 0x00000000UL 709 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 710 /* RESERVED [15:16] RW value= 0x0 */ 711 /* LOCKED [31:1] RW value= 0x0 */ 712 /*not used */ 713 #define INIT_SETTING_SEG0_3 0x00000000UL 714 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 715 /* RESERVED [15:16] RW value= 0x0 */ 716 /* LOCKED [31:1] RW value= 0x0 */ 717 /*not used */ 718 #define INIT_SETTING_SEG0_4 0x00000000UL 719 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 720 /* RESERVED [15:16] RW value= 0x0 */ 721 /* LOCKED [31:1] RW value= 0x0 */ 722 /*not used */ 723 #define INIT_SETTING_SEG0_5 0x00000000UL 724 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 725 /* RESERVED [15:6] RW value= 0x0 */ 726 /* LOCKED [31:1] RW value= 0x0 */ 727 /*not used */ 728 #define INIT_SETTING_SEG0_6 0x00000000UL 729 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 730 /* RESERVED [15:16] RW value= 0x0 */ 731 /* LOCKED [31:1] RW value= 0x0 */ 732 /*not used */ 733 #define INIT_SETTING_SEG0_7 0x00000000UL 734 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 735 /* RESERVED [15:16] RW value= 0x0 */ 736 /* LOCKED [31:1] RW value= 0x0 */ 737 /*not used */ 738 #define INIT_SETTING_SEG1_0 0x00000000UL 739 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 740 /* RESERVED [15:16] RW value= 0x0 */ 741 /* LOCKED [31:1] RW value= 0x0 */ 742 /*not used */ 743 #define INIT_SETTING_SEG1_1 0x00000000UL 744 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 745 /* RESERVED [15:16] RW value= 0x0 */ 746 /* LOCKED [31:1] RW value= 0x0 */ 747 /*Non-Cached access at 0x00_c000_0000 */ 748 #define INIT_SETTING_SEG1_2 0x00007F40UL 749 /* ADDRESS_OFFSET [0:15] RW value= 0x7F40 */ 750 /* RESERVED [15:16] RW value= 0x0 */ 751 /* LOCKED [31:1] RW value= 0x0 */ 752 /*Non-Cached access at 0x14_0000_0000 */ 753 #define INIT_SETTING_SEG1_3 0x00006C00UL 754 /* ADDRESS_OFFSET [0:15] RW value= 0x6C00 */ 755 /* RESERVED [15:16] RW value= 0x0 */ 756 /* LOCKED [31:1] RW value= 0x0 */ 757 /*Non-Cached WCB access at 0x00_d000_0000 */ 758 #define INIT_SETTING_SEG1_4 0x00007F30UL 759 /* ADDRESS_OFFSET [0:15] RW value= 0x7F30 */ 760 /* RESERVED [15:16] RW value= 0x0 */ 761 /* LOCKED [31:1] RW value= 0x0 */ 762 /*Non-Cached WCB 0x18_0000_0000 */ 763 #define INIT_SETTING_SEG1_5 0x00006800UL 764 /* ADDRESS_OFFSET [0:15] RW value= 0x6800 */ 765 /* RESERVED [15:6] RW value= 0x0 */ 766 /* LOCKED [31:1] RW value= 0x0 */ 767 /*Trace - Trace not in use here so can be left as 0 */ 768 #define INIT_SETTING_SEG1_6 0x00000000UL 769 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 770 /* RESERVED [15:16] RW value= 0x0 */ 771 /* LOCKED [31:1] RW value= 0x0 */ 772 /*not used */ 773 #define INIT_SETTING_SEG1_7 0x00000000UL 774 /* ADDRESS_OFFSET [0:15] RW value= 0x0 */ 775 /* RESERVED [15:16] RW value= 0x0 */ 776 /* LOCKED [31:1] RW value= 0x0 */ 777 778 /***************************************************************************//** 779 780 */ 781 typedef enum MTC_PATTERN_ 782 { 783 MTC_COUNTING_PATTERN = 0x00, /*!< */ 784 MTC_WALKING_ONE = 0x01, /*!< */ 785 MTC_PSEUDO_RANDOM = 0x02, /*!< */ 786 MTC_NO_REPEATING_PSEUDO_RANDOM = 0x03, /*!< */ 787 MTC_ALT_ONES_ZEROS = 0x04, /*!< */ 788 MTC_ALT_5_A = 0x05, /*!< */ 789 MTC_USER = 0x06, /*!< */ 790 MTC_PSEUDO_RANDOM_16BIT = 0x07, /*!< */ 791 MTC_PSEUDO_RANDOM_8BIT = 0x08, /*!< */ 792 } MTC_PATTERN; 793 794 795 796 typedef enum MTC_ADD_PATTERN_ 797 { 798 MTC_ADD_SEQUENTIAL = 0x00, /*!< */ 799 MTC_ADD_RANDOM = 0x01, /*!< */ 800 } MTC_ADD_PATTERN; 801 802 /***************************************************************************//** 803 804 */ 805 typedef enum DDR_SM_STATES_ 806 { 807 808 DDR_STATE_INIT = 0x00, /*!< 0 DDR_STATE_INIT*/ 809 DDR_STATE_MONITOR = 0x01, /*!< 1 DDR_STATE_MONITOR */ 810 DDR_STATE_TRAINING = 0x02, /*!< 2 DDR_STATE_TRAINING */ 811 DDR_STATE_VERIFY = 0x03, /*!< 3 DDR_STATE_VERIFY */ 812 } DDR_SM_STATES; 813 814 /***************************************************************************//** 815 816 */ 817 typedef enum DDR_SS_COMMAND_ 818 { 819 820 DDR_SS__INIT = 0x00, /*!< 0 DDR_SS__INIT */ 821 DDR_SS_MONITOR = 0x01, /*!< 1 DDR_SS_MONITOR */ 822 } DDR_SS_COMMAND; 823 824 825 /***************************************************************************//** 826 827 */ 828 typedef enum DDR_SS_STATUS_ 829 { 830 831 DDR_SETUP_DONE = 0x01, /*!< 0 DDR_SETUP_DONE */ 832 DDR_SETUP_FAIL = 0x02, /*!< 1 DDR_SETUP_FAIL */ 833 DDR_SETUP_SUCCESS = 0x04, /*!< 2 DDR_SETUP_SUCCESS */ 834 DDR_SETUP_OFF_MODE = 0x08, /*!< 4 DDR_SETUP_OFF_MODE */ 835 } DDR_SS_STATUS; 836 837 838 /***************************************************************************//** 839 840 */ 841 typedef enum DDR_TRAINING_SM_ 842 { 843 844 DDR_TRAINING_INIT, /*!< DDR_TRAINING_INIT */ 845 DDR_TRAINING_FAIL, 846 DDR_CHECK_TRAINING_SWEEP, 847 DDR_TRAINING_SWEEP, 848 DDR_TRAINING_CHECK_FOR_OFFMODE, /*!< DDR_TRAINING_OFFMODE */ 849 DDR_TRAINING_SET_MODE_VS_BITS, 850 DDR_TRAINING_FLASH_REGS, 851 DDR_TRAINING_CORRECT_RPC, 852 DDR_TRAINING_SOFT_RESET, 853 DDR_TRAINING_CALIBRATE_IO, 854 DDR_TRAINING_CONFIG_PLL, 855 DDR_TRAINING_SETUP_SEGS, 856 DDR_TRAINING_VERIFY_PLL_LOCK, 857 DDR_TRAINING_SETUP_DDRC, 858 DDR_TRAINING_RESET, 859 DDR_TRAINING_ROTATE_CLK, 860 DDR_TRAINING_SET_TRAINING_PARAMETERS, 861 DDR_TRAINING_IP_SM_BCLKSCLK_SW, 862 DDR_MANUAL_ADDCMD_TRAINING_SW, 863 DDR_TRAINING_IP_SM_START, 864 DDR_TRAINING_IP_SM_START_CHECK, 865 DDR_TRAINING_IP_SM_BCLKSCLK, 866 DDR_TRAINING_IP_SM_ADDCMD, 867 DDR_TRAINING_IP_SM_WRLVL, 868 DDR_TRAINING_IP_SM_RDGATE, 869 DDR_TRAINING_IP_SM_DQ_DQS, 870 DDR_TRAINING_IP_SM_VERIFY, 871 DDR_TRAINING_SET_FINAL_MODE, 872 DDR_TRAINING_WRITE_CALIBRATION, 873 DDR_TRAINING_WRITE_CALIBRATION_RETRY, /*!< Retry on calibration fail */ 874 DDR_SWEEP_CHECK, 875 DDR_SANITY_CHECKS, 876 DDR_FULL_MTC_CHECK, 877 DDR_FULL_32BIT_NC_CHECK, 878 DDR_FULL_32BIT_CACHE_CHECK, 879 DDR_LOAD_PATTERN_TO_CACHE, 880 DDR_VERIFY_PATTERN_IN_CACHE, 881 DDR_FULL_32BIT_WRC_CHECK, 882 DDR_FULL_64BIT_NC_CHECK, 883 DDR_FULL_64BIT_CACHE_CHECK, 884 DDR_FULL_64BIT_WRC_CHECK, 885 DDR_TRAINING_VREFDQ_CALIB, 886 DDR_TRAINING_FPGA_VREFDQ_CALIB, 887 DDR_TRAINING_FINISH_CHECK, 888 DDR_TRAINING_FINISHED, 889 DDR_TRAINING_FAIL_SM2_VERIFY, 890 DDR_TRAINING_FAIL_SM_VERIFY, 891 DDR_TRAINING_FAIL_SM_DQ_DQS, 892 DDR_TRAINING_FAIL_SM_RDGATE, 893 DDR_TRAINING_FAIL_SM_WRLVL, 894 DDR_TRAINING_FAIL_SM_ADDCMD, 895 DDR_TRAINING_FAIL_SM_BCLKSCLK, 896 DDR_TRAINING_FAIL_BCLKSCLK_SW, 897 DDR_TRAINING_FAIL_FULL_32BIT_NC_CHECK, 898 DDR_TRAINING_FAIL_32BIT_CACHE_CHECK, 899 DDR_TRAINING_FAIL_MIN_LATENCY, 900 DDR_TRAINING_FAIL_START_CHECK, 901 DDR_TRAINING_FAIL_PLL_LOCK, 902 DDR_TRAINING_FAIL_DDR_SANITY_CHECKS, 903 DDR_SWEEP_AGAIN 904 } DDR_TRAINING_SM; 905 906 907 /***************************************************************************//** 908 909 */ 910 typedef enum { 911 912 USR_CMD_GET_DDR_STATUS = 0x00, //!< USR_CMD_GET_DDR_STATUS 913 USR_CMD_GET_MODE_SETTING = 0x01, //!< USR_CMD_GET_MODE_SETTING 914 USR_CMD_GET_W_CALIBRATION = 0x02, //!< USR_CMD_GET_W_CALIBRATION 915 USR_CMD_GET_GREEN_ZONE = 0x03, //!< USR_CMD_GET_GREEN_ZONE 916 USR_CMD_GET_REG = 0x04 //!< USR_CMD_GET_REG 917 } DDR_USER_GET_COMMANDS_t; 918 919 /***************************************************************************//** 920 921 */ 922 typedef enum { 923 USR_CMD_SET_GREEN_ZONE_DQ = 0x80, //!< USR_CMD_SET_GREEN_ZONE_DQ 924 USR_CMD_SET_GREEN_ZONE_DQS = 0x81, //!< USR_CMD_SET_GREEN_ZONE_DQS 925 USR_CMD_SET_GREEN_ZONE_VREF_MAX = 0x82, //!< USR_CMD_SET_GREEN_ZONE_VREF 926 USR_CMD_SET_GREEN_ZONE_VREF_MIN = 0x83, //!< USR_CMD_SET_GREEN_ZONE_VREF 927 USR_CMD_SET_RETRAIN = 0x84, //!< USR_CMD_SET_RETRAIN 928 USR_CMD_SET_REG = 0x85 //!< USR_CMD_SET_REG 929 } DDR_USER_SET_COMMANDS_t; 930 931 /***************************************************************************//** 932 933 */ 934 typedef enum SWEEP_STATES_{ 935 INIT_SWEEP, //!< start the sweep 936 ADDR_CMD_OFFSET_SWEEP, //!< sweep address command 937 BCLK_SCLK_OFFSET_SWEEP, //!< sweep bclk sclk 938 DPC_VRGEN_V_SWEEP, //!< sweep vgen_v 939 DPC_VRGEN_H_SWEEP, //!< sweep vgen_h 940 DPC_VRGEN_VS_SWEEP, //!< VS sweep 941 FINISHED_SWEEP, //!< finished sweep 942 } SWEEP_STATES; 943 944 /***************************************************************************//** 945 946 */ 947 typedef enum { 948 USR_OPTION_tip_register_dump = 0x00 //!< USR_OPTION_tip_register_dump 949 } USR_STATUS_OPTION_t; 950 951 952 #define MAX_LANES 5 953 954 /***************************************************************************//** 955 956 */ 957 typedef enum SEG_SETUP_{ 958 DEFAULT_SEG_SETUP = 0x00, 959 LIBERO_SEG_SETUP 960 } SEG_SETUP; 961 962 963 964 /***************************************************************************//** 965 966 */ 967 typedef struct mss_ddr_fpga_vref_{ 968 uint32_t status_lower; 969 uint32_t status_upper; 970 uint32_t lower; 971 uint32_t upper; 972 uint32_t vref_result; 973 } mss_ddr_vref; 974 975 /** 976 * \brief dll sgmii SCB regs 977 */ 978 typedef struct IOSCB_BANKCONT_DDR_ { 979 /* bit0 - This when asserted resets all the non-volatile register bits e.g. RW-P bits, the bit self clears i.e. is similar to a W1P bit */ 980 /* bit1 - This when asserted resets all the register bits apart from the non-volatile registers, the bit self clears. i.e. is similar to a W1P bit */ 981 __IO uint32_t soft_reset; /* bit8 - This asserts the functional reset of the block. It is asserted at power up. When written is stays asserted until written to 0. */ 982 983 __IO uint32_t dpc_bits; /* bit 3:0: dpc_vs bank voltage select for pvt calibration */ 984 /* : dpc_vrgen_h */ 985 /* : dpc_vrgen_en_h */ 986 /* : dpc_move_en_h */ 987 /* : dpc_vrgen_v */ 988 /* : dpc_vrgen_en_v */ 989 /* : dpc_move_en_v */ 990 __IO uint32_t bank_status; /* bit 0: Bank power on complete (active low for polling) */ 991 /* bit 1: Bank calibration complete (active low for polling) */ 992 } IOSCB_BANKCONT_DDR_STRUCT; 993 994 995 #define IOSCB_BANKCONT_DDR_BASE 0x3E020000UL 996 #define IOSCB_BANKCONT_DDR ((volatile IOSCB_BANKCONT_DDR_STRUCT *) IOSCB_BANKCONT_DDR_BASE) 997 998 /***************************************************************************//** 999 1000 */ 1001 typedef struct mss_ddr_write_calibration_{ 1002 uint32_t status_lower; 1003 uint32_t lower[MAX_LANES]; 1004 uint32_t lane_calib_result; 1005 } mss_ddr_write_calibration; 1006 1007 /***************************************************************************//** 1008 1009 */ 1010 typedef struct mss_lpddr4_dq_calibration_{ 1011 uint32_t lower[MAX_LANES]; 1012 uint32_t upper[MAX_LANES]; 1013 uint32_t calibration_found[MAX_LANES]; 1014 } mss_lpddr4_dq_calibration; 1015 1016 1017 /***************************************************************************//** 1018 Calibration settings derived during write training 1019 */ 1020 typedef struct mss_ddr_calibration_{ 1021 /* CMSIS related defines identifying the UART hardware. */ 1022 mss_ddr_write_calibration write_cal; 1023 mss_lpddr4_dq_calibration dq_cal; 1024 mss_ddr_vref fpga_vref; 1025 mss_ddr_vref mem_vref; 1026 } mss_ddr_calibration; 1027 1028 /***************************************************************************//** 1029 sweep index's 1030 */ 1031 typedef struct sweep_index_{ 1032 uint8_t cmd_index; 1033 uint8_t bclk_sclk_index; 1034 uint8_t dpc_vgen_index; 1035 uint8_t dpc_vgen_h_index; 1036 uint8_t dpc_vgen_vs_index; 1037 } sweep_index; 1038 1039 /***************************************************************************//** 1040 1041 */ 1042 uint8_t 1043 MSS_DDR_init_simulation 1044 ( 1045 void 1046 ); 1047 1048 /***************************************************************************//** 1049 1050 */ 1051 uint8_t 1052 MSS_DDR_training 1053 ( 1054 uint8_t ddr_type 1055 ); 1056 1057 1058 /***************************************************************************//** 1059 The ddr_state_machine() function runs a state machine which initializes and 1060 monitors the DDR 1061 1062 @return 1063 This function returns status, see DDR_SS_STATUS enum 1064 1065 Example: 1066 @code 1067 1068 uint32_t ddr_status; 1069 ddr_status = ddr_state_machine(DDR_SS__INIT); 1070 1071 while((ddr_status & DDR_SETUP_DONE) != DDR_SETUP_DONE) 1072 { 1073 ddr_status = ddr_state_machine(DDR_SS_MONITOR); 1074 } 1075 if ((ddr_status & DDR_SETUP_FAIL) != DDR_SETUP_FAIL) 1076 { 1077 error |= (0x1U << 2U); 1078 } 1079 1080 @endcode 1081 1082 */ 1083 uint32_t 1084 ddr_state_machine 1085 ( 1086 DDR_SS_COMMAND command 1087 ); 1088 1089 /***************************************************************************//** 1090 The debug_read_ddrcfg() prints out the ddrcfg register values 1091 1092 @return 1093 This function returns status, see DDR_SS_STATUS enum 1094 1095 Example: 1096 @code 1097 1098 debug_read_ddrcfg(); 1099 1100 @endcode 1101 1102 */ 1103 void 1104 debug_read_ddrcfg 1105 ( 1106 void 1107 ); 1108 1109 /***************************************************************************//** 1110 The setup_ddr_segments() sets up seg regs 1111 1112 @return 1113 none 1114 1115 Example: 1116 @code 1117 1118 setup_ddr_segments(DEFAULT_SEG_SETUP); 1119 1120 @endcode 1121 1122 */ 1123 void 1124 setup_ddr_segments 1125 ( 1126 SEG_SETUP option 1127 ); 1128 1129 1130 #ifdef __cplusplus 1131 } 1132 #endif 1133 1134 #endif /* __MSS_DDRC_H_ */ 1135 1136 1137
