Searched refs:__IO (Results 1 – 15 of 15) sorted by relevance
27 #define __IO volatile macro31 __IO uint32_t NETWORK_CONTROL; /* 0x0000 */32 __IO uint32_t NETWORK_CONFIG; /* 0x0004 */34 __IO uint32_t USER_IO; /* 0x000C */35 __IO uint32_t DMA_CONFIG; /* 0x0010 */36 __IO uint32_t TRANSMIT_STATUS; /* 0x0014 */37 __IO uint32_t RECEIVE_Q_PTR; /* 0x0018 */38 __IO uint32_t TRANSMIT_Q_PTR; /* 0x001C */39 __IO uint32_t RECEIVE_STATUS; /* 0x0020 */40 __IO uint32_t INT_STATUS; /* 0x0024 */[all …]
37 __IO uint32_t INPUT_VAL; /* 0x0000 */38 __IO uint32_t INPUT_EN; /* 0x0004 */39 __IO uint32_t OUTPUT_VAL; /* 0x0008 */40 __IO uint32_t OUTPUT_EN; /* 0x000C */41 __IO uint32_t PUE; /* 0x0010 */42 __IO uint32_t DS; /* 0x0014 */43 __IO uint32_t RISE_IE; /* 0x0018 */44 __IO uint32_t RISE_IP; /* 0x001C */45 __IO uint32_t FALL_IE; /* 0x0020 */46 __IO uint32_t FALL_IP; /* 0x0024 */[all …]
843 #define __IO volatile macro848 __IO uint32_t HFXOSCCFG; /* 0x0000 */849 __IO uint32_t COREPLLCFG0; /* 0x0004 */850 __IO uint32_t reserved0; /* 0x0008 */851 __IO uint32_t DDRPLLCFG0; /* 0x000C */852 __IO uint32_t DDRPLLCFG1; /* 0x0010 */853 __IO uint32_t reserved1; /* 0x0014 */854 __IO uint32_t reserved2; /* 0x0018 */855 __IO uint32_t GEMGXLPLLCFG0; /* 0x001C */856 __IO uint32_t GEMGXLPLLCFG1; /* 0x0020 */[all …]
45 __IO uint32_t CFG_MANUAL_ADDRESS_MAP;48 __IO uint32_t cfg_manual_address_map :1;54 __IO uint32_t CFG_CHIPADDR_MAP;57 __IO uint32_t cfg_chipaddr_map :24;63 __IO uint32_t CFG_CIDADDR_MAP;66 __IO uint32_t cfg_cidaddr_map :18;72 __IO uint32_t CFG_MB_AUTOPCH_COL_BIT_POS_LOW;75 __IO uint32_t cfg_mb_autopch_col_bit_pos_low :3;81 __IO uint32_t CFG_MB_AUTOPCH_COL_BIT_POS_HIGH;84 __IO uint32_t cfg_mb_autopch_col_bit_pos_high :4;[all …]
32 #ifndef __IO33 #define __IO volatile macro229 __IO uint32_t SOFT_RESET_DDR_PHY;242 __IO uint32_t DDRPHY_MODE;245 __IO uint32_t DDRMODE :3;246 __IO uint32_t ECC :1;247 __IO uint32_t CRC :1;248 __IO uint32_t Bus_width :3;249 __IO uint32_t DMI_DBI :1;250 __IO uint32_t DQ_drive :2;[all …]
31 #ifndef __IO32 #define __IO volatile macro41 __IO uint32_t SOFT_RESET; /*!< Offset: 0x0 */42 __IO uint32_t PLL_CTRL; /*!< Offset: 0x4 */43 __IO uint32_t PLL_REF_FB; /*!< Offset: 0x8 */44 __IO uint32_t PLL_FRACN; /*!< Offset: 0xc */45 __IO uint32_t PLL_DIV_0_1; /*!< Offset: 0x10 */46 __IO uint32_t PLL_DIV_2_3; /*!< Offset: 0x14 */47 __IO uint32_t PLL_CTRL2; /*!< Offset: 0x18 */48 __IO uint32_t PLL_CAL; /*!< Offset: 0x1c */[all …]
84 __IO uint32_t iomux0_cr; /* peripheral is connected to the Fabric or86 __IO uint32_t iomux1_cr; /* BNK4 SDV PAD 0 to 7 */87 __IO uint32_t iomux2_cr; /* BNK4 SDV PAD 8 to 13 */88 __IO uint32_t iomux3_cr; /* BNK2 SDV PAD 14 to 21 */89 __IO uint32_t iomux4_cr; /* BNK2 SDV PAD 22 to 29 */90 __IO uint32_t iomux5_cr; /* BNK2 PAD 30 to 37 */91 __IO uint32_t iomux6_cr; /* MMC/SD Voltage select lines are inverted on133 __IO uint32_t mssio_bank4_pcode_ncode_vs; /* bank 4- set pcode, ncode and135 __IO uint32_t mssio_bank2_pcode_ncode_vs; /* bank 2- set pcode, ncode and143 __IO uint32_t mssio_bank4_io_cfg_0_cr; /* x_vddi Ratio Rx<0-2> == 001[all …]
126 …__IO uint32_t soft_reset; /* bit8 - This asserts the functional reset of the block. It is as…128 __IO uint32_t dpc_bits; /* DPC Bits Register */129 __IO uint32_t bank_status; /* Bank Complete Registers */143 …__IO uint32_t soft_reset; /* bit8 - This asserts the functional reset of the block. It is as…145 __IO uint32_t dll_ctrl0; /* DPC Bits Register */146 __IO uint32_t dll_ctrl1; /* DPC Bits Register */147 __IO uint32_t dll_stat0; /* DLL control register 0 */148 __IO uint32_t dll_stat1; /* DLL control register 1 */149 __IO uint32_t dll_stat2; /* DLL control register 2 */163 …__IO uint32_t soft_reset; /* bit8 - This asserts the functional reset of the block. It is a…[all …]
80 __IO uint32_t controlReg; /* CFM Control Register */81 __IO uint32_t clkselReg; /* Clock Selection Register */82 __IO uint32_t runtimeReg; /* Reference Count Value */83 __IO uint32_t modelReg; /* Sets the measurement mode */
981 …__IO uint32_t soft_reset; /* bit8 - This asserts the functional reset of the block. It is as…983 …__IO uint32_t dpc_bits; /* bit 3:0: dpc_vs bank voltage select for pvt calibration …990 …__IO uint32_t bank_status; /* bit 0: Bank power on complete (active low for polling) …
258 …__IO uint32_t SYS_SLP_CNTRL; /*!< (@ 0x40080100) System Sleep Control …261 …__IO uint32_t SLEEP_MODE : 1; /*!< [0..0] Selects the System Sleep mode …263 …__IO uint32_t TEST : 1; /*!< [2..2] Test bit …264 …__IO uint32_t SLEEP_ALL : 1; /*!< [3..3] Initiates the System Sleep mode …269 …__IO uint32_t PROC_CLK_CNTRL; /*!< (@ 0x40080104) Processor Clock Control Regist…279 …__IO uint32_t PROCESSOR_CLOCK_DIVIDE: 8; /*!< [0..7] Selects the EC clock rate …284 …__IO uint32_t SLOW_CLK_CNTRL; /*!< (@ 0x40080108) Configures the EC_CLK clock do…287 …__IO uint32_t SLOW_CLOCK_DIVIDE: 10; /*!< [0..9] SLOW_CLOCK_DIVIDE. n=Divide by n; 0=Cloc…292 …__IO uint32_t OSC_ID; /*!< (@ 0x4008010C) Oscillator ID Register …295 …__IO uint32_t TEST : 8; /*!< [0..7] Test bits …[all …]
538 __IO uint32_t N_ID:3;539 __IO uint32_t ID:29;547 __IO uint32_t DATAHIGH;548 __IO uint32_t DATALOW;550 __IO int8_t DATA[8];557 __IO uint32_t L; /* 32 bit flag */561 __IO uint32_t NA0:16;562 __IO uint32_t DLC:4; 563 __IO uint32_t IDE:1; 564 __IO uint32_t RTR:1; [all …]
48 #ifndef __IO49 #define __IO volatile /*!< Defines 'read / write' per macro3599 __IO uint32_t TEMP0;3602 __IO uint32_t TEMP1;3605 __IO uint32_t CLOCK_CONFIG_CR;3608 __IO uint32_t RTC_CLOCK_CR;3611 __IO uint32_t FABRIC_RESET_CR;3614 __IO uint32_t BOOT_FAIL_CR;3620 __IO uint32_t MSS_RESET_CR;3623 __IO uint32_t CONFIG_LOCK_CR;[all …]
82 #ifndef __IO83 #define __IO volatile macro94 __IO uint64_t pmp : 38;95 __IO uint64_t rsrvd : 18;96 __IO uint64_t mode : 8;104 __IO uint64_t addr : 38;105 __IO uint64_t rw : 1;106 __IO uint64_t id : 4;107 __IO uint64_t failed : 1;108 __IO uint64_t padding : (64-44);[all …]
145 __IO uint32_t VID;146 __IO uint32_t HWCFG;147 __IO uint32_t CMD;148 __IO uint32_t DATA;
